diff options
| author | Saksham Jain <saksham.jain@nxp.com> | 2016-03-23 16:24:40 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-03-29 08:46:22 -0700 |
| commit | 4a97a0c91d25763d7c3af5530c5e89f53fee7643 (patch) | |
| tree | 7f49fd151c1329dccfb276ba4e72c03cf292fbe4 /arch/arm/include/asm/arch-fsl-layerscape | |
| parent | 809d343a1a778e68d519c04e01118bd8eb990eff (diff) | |
| download | talos-obmc-uboot-4a97a0c91d25763d7c3af5530c5e89f53fee7643.tar.gz talos-obmc-uboot-4a97a0c91d25763d7c3af5530c5e89f53fee7643.zip | |
armv8: fsl-lsch3: Disable SMMU during secure boot
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.
For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index e8e3b91d3d..4f0fdfd4b1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -83,6 +83,21 @@ /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +/* MMU 500 */ +#define SMMU_SCR0 (SMMU_BASE + 0x0) +#define SMMU_SCR1 (SMMU_BASE + 0x4) +#define SMMU_SCR2 (SMMU_BASE + 0x8) +#define SMMU_SACR (SMMU_BASE + 0x10) +#define SMMU_IDR0 (SMMU_BASE + 0x20) +#define SMMU_IDR1 (SMMU_BASE + 0x24) + +#define SMMU_NSCR0 (SMMU_BASE + 0x400) +#define SMMU_NSCR2 (SMMU_BASE + 0x408) +#define SMMU_NSACR (SMMU_BASE + 0x410) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) |
