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| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2016-06-03 18:41:31 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 14:12:50 -0700 |
| commit | b7f2bbfff6dcc2d5989bb1d20500c431f7927daf (patch) | |
| tree | 4398ed397455de7ea26c78867a1d827b1c95e0dd /arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | |
| parent | ddd8a08052052561af38ecbe30930001a2ae940b (diff) | |
| download | talos-obmc-uboot-b7f2bbfff6dcc2d5989bb1d20500c431f7927daf.tar.gz talos-obmc-uboot-b7f2bbfff6dcc2d5989bb1d20500c431f7927daf.zip | |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 57b99d4084..e98e055d9f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -60,7 +60,11 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ +#ifdef CONFIG_LS1012A +#define PCIE_LUT_BASE 0xC0000 +#else #define PCIE_LUT_BASE 0x10000 +#endif #define PCIE_LUT_LCTRL0 0x7F8 #define PCIE_LUT_DBG 0x7FC |
