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authorChandan Nath <chandan.nath@ti.com>2012-01-09 20:38:59 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-01-16 08:40:12 +0100
commit8a8f084e4ffa0e2357790cd92b69301eaeb2834d (patch)
treef29a8f6bb0d33ec4041d64f761623f4215fe8417 /arch/arm/include/asm/arch-am33xx/omap.h
parent876bdd6d460cfcb7dc3b3c52291e20d322a939d5 (diff)
downloadtalos-obmc-uboot-8a8f084e4ffa0e2357790cd92b69301eaeb2834d.tar.gz
talos-obmc-uboot-8a8f084e4ffa0e2357790cd92b69301eaeb2834d.zip
ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X platform. In this patch, MMC1 is configured as boot device for SPL and support for other devices will be added in the next patch series. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/omap.h')
-rw-r--r--arch/arm/include/asm/arch-am33xx/omap.h59
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
new file mode 100644
index 0000000000..fc2b7a5a28
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+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -0,0 +1,59 @@
+/*
+ * omap.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Author:
+ * Chandan Nath <chandan.nath@ti.com>
+ *
+ * Derived from OMAP4 work by
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _OMAP_H_
+#define _OMAP_H_
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_END 0x4030E000
+#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
+
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK 0xFF
+#define BOOT_DEVICE_OFFSET 0x8
+#define DEV_DESC_PTR_OFFSET 0x4
+#define DEV_DATA_PTR_OFFSET 0x18
+#define BOOT_MODE_OFFSET 0x8
+#define RESET_REASON_OFFSET 0x9
+#define CH_FLAGS_OFFSET 0xA
+
+#define CH_FLAGS_CHSETTINGS (0x1 << 0)
+#define CH_FLAGS_CHRAM (0x1 << 1)
+#define CH_FLAGS_CHFLASH (0x1 << 2)
+#define CH_FLAGS_CHMMCSD (0x1 << 3)
+
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+ char *boot_message;
+ unsigned int mem_boot_descriptor;
+ unsigned char omap_bootdevice;
+ unsigned char reset_reason;
+ unsigned char ch_flags;
+};
+#endif
+#endif
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