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authorChandan Nath <chandan.nath@ti.com>2011-10-14 02:58:23 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-10-27 21:56:36 +0200
commitf87fa62af9abd5f8196596d3ea4347999ec40e1e (patch)
tree353e4db95ba7292b6b947ef63eec490890564885 /arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
parent5655108a8215123bac7154f64c29109fd63d86be (diff)
downloadtalos-obmc-uboot-f87fa62af9abd5f8196596d3ea4347999ec40e1e.tar.gz
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ARM:AM33XX: Add clock definitions
This patch adds basic clock definition of am33xx SoC. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/clocks_am33xx.h')
-rw-r--r--arch/arm/include/asm/arch-am33xx/clocks_am33xx.h55
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
new file mode 100644
index 0000000000..abc5b6b411
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -0,0 +1,55 @@
+/*
+ * clocks_am33xx.h
+ *
+ * AM33xx clock define
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCKS_AM33XX_H_
+#define _CLOCKS_AM33XX_H_
+
+#define OSC 24
+
+/* MAIN PLL Fdll = 550 MHZ, */
+#define MPUPLL_M 550
+#define MPUPLL_N 23
+#define MPUPLL_M2 1
+
+/* Core PLL Fdll = 1 GHZ, */
+#define COREPLL_M 1000
+#define COREPLL_N 23
+
+#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
+#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
+#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
+
+/*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+#define PERPLL_M 960
+#define PERPLL_N 23
+#define PERPLL_M2 5
+
+/* DDR Freq is 266 MHZ for now */
+/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+#define DDRPLL_M 266
+#define DDRPLL_N 23
+#define DDRPLL_M2 1
+
+extern void pll_init(void);
+extern void enable_emif_clocks(void);
+
+#endif /* endif _CLOCKS_AM33XX_H_ */
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