diff options
| author | Matt Porter <mporter@ti.com> | 2013-03-15 10:07:04 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-24 12:49:11 -0400 |
| commit | b43c17cba66a8ba88f8a0abc98b2bbb561c54b08 (patch) | |
| tree | 4ace08f676868aea395e9d408ba44d302136d702 /arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | |
| parent | 3ba65f97cbedb39fb486f42f8daa9b9e0d36705a (diff) | |
| download | talos-obmc-uboot-b43c17cba66a8ba88f8a0abc98b2bbb561c54b08.tar.gz talos-obmc-uboot-b43c17cba66a8ba88f8a0abc98b2bbb561c54b08.zip | |
am33xx: refactor am33xx clocks and add ti814x support
Split clock.c for am335x and ti814x and add ti814x specific
clock support.
Signed-off-by: Matt Porter <mporter@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/clocks_am33xx.h')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 31 |
1 files changed, 2 insertions, 29 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 2d960070f1..89b63d9a8c 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -3,7 +3,7 @@ * * AM33xx clock define * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,40 +19,13 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ -#define OSC (V_OSCK/1000000) - /* MAIN PLL Fdll = 550 MHz, by default */ #ifndef CONFIG_SYS_MPUCLK #define CONFIG_SYS_MPUCLK 550 #endif -#define MPUPLL_M CONFIG_SYS_MPUCLK -#define MPUPLL_N (OSC-1) -#define MPUPLL_M2 1 - -/* Core PLL Fdll = 1 GHZ, */ -#define COREPLL_M 1000 -#define COREPLL_N (OSC-1) - -#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ -#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ -#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ - -/* - * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll - * frequency needs to be set to 960 MHZ. Hence, - * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below - */ -#define PERPLL_M 960 -#define PERPLL_N (OSC-1) -#define PERPLL_M2 5 - -/* DDR Freq is 266 MHZ for now */ -/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ -#define DDRPLL_M 266 -#define DDRPLL_N (OSC-1) -#define DDRPLL_M2 1 extern void pll_init(void); extern void enable_emif_clocks(void); +extern void enable_dmm_clocks(void); #endif /* endif _CLOCKS_AM33XX_H_ */ |
