Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

5 files changed, 111 insertions, 12 deletions

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 6c655773e8..25a9d4ce12 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
 obj-y	+= misc.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6))
 obj-$(CONFIG_CMD_SATA) += sata.o
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index a77c4decc9..5a09107c5a 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -58,6 +58,7 @@ char *get_reset_cause(void)
 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
 static const unsigned char bank_lookup[] = {3, 2};
 
+/* these MMDC registers are common to the IMX53 and IMX6 */
 struct esd_mmdc_regs {
 	uint32_t	ctl;
 	uint32_t	pdc;
@@ -66,15 +67,6 @@ struct esd_mmdc_regs {
 	uint32_t	cfg1;
 	uint32_t	cfg2;
 	uint32_t	misc;
-	uint32_t	scr;
-	uint32_t	ref;
-	uint32_t	rsvd1;
-	uint32_t	rsvd2;
-	uint32_t	rwd;
-	uint32_t	or;
-	uint32_t	mrr;
-	uint32_t	cfg3lp;
-	uint32_t	mr4;
 };
 
 #define ESD_MMDC_CTL_GET_ROW(mdctl)	((ctl >> 24) & 7)
@@ -83,6 +75,12 @@ struct esd_mmdc_regs {
 #define ESD_MMDC_CTL_GET_CS1(mdctl)	((ctl >> 30) & 1)
 #define ESD_MMDC_MISC_GET_BANK(mdmisc)	((misc >> 5) & 1)
 
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
 unsigned imx_ddr_size(void)
 {
 	struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 6e46ea8dcd..22cd11aa04 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -11,6 +11,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
+#include <asm/arch/sys_proto.h>
+#endif
 #include <asm/imx-common/iomux-v3.h>
 
 static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -54,12 +57,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 #endif
 }
 
+/* configures a list of pads within declared with IOMUX_PADS macro */
 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 				      unsigned count)
 {
 	iomux_v3_cfg_t const *p = pad_list;
+	int stride;
 	int i;
 
-	for (i = 0; i < count; i++)
-		imx_iomux_v3_setup_pad(*p++);
+#if defined(CONFIG_MX6QDL)
+	stride = 2;
+	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+		p += 1;
+#else
+	stride = 1;
+#endif
+	for (i = 0; i < count; i++) {
+		imx_iomux_v3_setup_pad(*p);
+		p += stride;
+	}
 }
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index 2e694866e0..c10dd28f61 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -8,13 +8,18 @@
 #include <asm/arch/iomux.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 
 int setup_sata(void)
 {
 	struct iomuxc_base_regs *const iomuxc_regs
 		= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+	int ret;
 
-	int ret = enable_sata_clock();
+	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+		return 1;
+
+	ret = enable_sata_clock();
 	if (ret)
 		return ret;
 
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
new file mode 100644
index 0000000000..9a02a644bc
--- /dev/null
+++ b/arch/arm/imx-common/spl.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/spl.h>
+#include <spl.h>
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+u32 spl_boot_device(void)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1);
+
+	/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+	switch ((reg & 0x000000FF) >> 4) {
+	 /* EIM: See 8.5.1, Table 8-9 */
+	case 0x0:
+		/* BOOT_CFG1[3]: NOR/OneNAND Selection */
+		if ((reg & 0x00000008) >> 3)
+			return BOOT_DEVICE_ONENAND;
+		else
+			return BOOT_DEVICE_NOR;
+		break;
+	/* SATA: See 8.5.4, Table 8-20 */
+	case 0x2:
+		return BOOT_DEVICE_SATA;
+	/* Serial ROM: See 8.5.5.1, Table 8-22 */
+	case 0x3:
+		/* BOOT_CFG4[2:0] */
+		switch ((reg & 0x07000000) >> 24) {
+		case 0x0 ... 0x4:
+			return BOOT_DEVICE_SPI;
+		case 0x5 ... 0x7:
+			return BOOT_DEVICE_I2C;
+		}
+		break;
+	/* SD/eSD: 8.5.3, Table 8-15  */
+	case 0x4:
+	case 0x5:
+		return BOOT_DEVICE_MMC1;
+	/* MMC/eMMC: 8.5.3 */
+	case 0x6:
+	case 0x7:
+		return BOOT_DEVICE_MMC1;
+	/* NAND Flash: 8.5.2 */
+	case 0x8 ... 0xf:
+		return BOOT_DEVICE_NAND;
+	}
+	return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	/* for MMC return either RAW or FAT mode */
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+		return MMCSD_MODE_FAT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	default:
+		puts("spl: ERROR:  unsupported device\n");
+		hang();
+	}
+}
+#endif