Merge branch 'master' of git://www.denx.de/git/u-boot-imx

5 files changed, 376 insertions, 110 deletions

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 10908c4c4a..dce7ffc022 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -25,17 +25,26 @@ config MX6SL
 config MX6SX
 	bool
 
+config MX6UL
+	select SYS_L2CACHE_OFF
+	bool
+
 choice
 	prompt "MX6 board select"
 	optional
 
+config TARGET_CM_FX6
+	bool "Support CM-FX6"
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_SECOMX6
 	bool "Support secomx6 boards"
-	select CPU_V7
 
 config TARGET_TQMA6
 	bool "TQ Systems TQMa6 board"
-	select CPU_V7
 
 endchoice
 
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ae99945304..9cf4eece13 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -81,43 +81,37 @@ void enable_usboh3_clk(unsigned char enable)
 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
 void enable_enet_clk(unsigned char enable)
 {
-	u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
+	u32 mask, *addr;
+
+	if (is_cpu_type(MXC_CPU_MX6UL)) {
+		mask = MXC_CCM_CCGR3_ENET_MASK;
+		addr = &imx_ccm->CCGR3;
+	} else {
+		mask = MXC_CCM_CCGR1_ENET_MASK;
+		addr = &imx_ccm->CCGR1;
+	}
 
 	if (enable)
-		setbits_le32(&imx_ccm->CCGR1, mask);
+		setbits_le32(addr, mask);
 	else
-		clrbits_le32(&imx_ccm->CCGR1, mask);
+		clrbits_le32(addr, mask);
 }
 #endif
 
 #ifdef CONFIG_MXC_UART
 void enable_uart_clk(unsigned char enable)
 {
-	u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
-
-	if (enable)
-		setbits_le32(&imx_ccm->CCGR5, mask);
-	else
-		clrbits_le32(&imx_ccm->CCGR5, mask);
-}
-#endif
-
-#ifdef CONFIG_SPI
-/* spi_num can be from 0 - 4 */
-int enable_cspi_clock(unsigned char enable, unsigned spi_num)
-{
 	u32 mask;
 
-	if (spi_num > 4)
-		return -EINVAL;
+	if (is_cpu_type(MXC_CPU_MX6UL))
+		mask = MXC_CCM_CCGR5_UART_MASK;
+	else
+		mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 
-	mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
 	if (enable)
-		setbits_le32(&imx_ccm->CCGR1, mask);
+		setbits_le32(&imx_ccm->CCGR5, mask);
 	else
-		clrbits_le32(&imx_ccm->CCGR1, mask);
-
-	return 0;
+		clrbits_le32(&imx_ccm->CCGR5, mask);
 }
 #endif
 
@@ -145,6 +139,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
 	u32 reg;
 	u32 mask;
+	u32 *addr;
 
 	if (i2c_num > 3)
 		return -EINVAL;
@@ -159,14 +154,19 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 			reg &= ~mask;
 		__raw_writel(reg, &imx_ccm->CCGR2);
 	} else {
-		mask = MXC_CCM_CCGR_CG_MASK
-			<< (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
-		reg = __raw_readl(&imx_ccm->CCGR1);
+		if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+			mask = MXC_CCM_CCGR6_I2C4_MASK;
+			addr = &imx_ccm->CCGR6;
+		} else {
+			mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
+			addr = &imx_ccm->CCGR1;
+		}
+		reg = __raw_readl(addr);
 		if (enable)
 			reg |= mask;
 		else
 			reg &= ~mask;
-		__raw_writel(reg, &imx_ccm->CCGR1);
+		__raw_writel(reg, addr);
 	}
 	return 0;
 }
@@ -227,9 +227,11 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
 	switch (pll) {
 	case PLL_BUS:
-		if (pfd_num == 3) {
-			/* No PFD3 on PPL2 */
-			return 0;
+		if (!is_cpu_type(MXC_CPU_MX6UL)) {
+			if (pfd_num == 3) {
+				/* No PFD3 on PPL2 */
+				return 0;
+			}
 		}
 		div = __raw_readl(&imx_ccm->analog_pfd_528);
 		freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
@@ -261,10 +263,12 @@ static u32 get_mcu_main_clk(void)
 
 u32 get_periph_clk(void)
 {
-	u32 reg, freq = 0;
+	u32 reg, div = 0, freq = 0;
 
 	reg = __raw_readl(&imx_ccm->cbcdr);
 	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+		div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
+		       MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 		reg = __raw_readl(&imx_ccm->cbcmr);
 		reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 		reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
@@ -304,7 +308,7 @@ u32 get_periph_clk(void)
 		}
 	}
 
-	return freq;
+	return freq / (div + 1);
 }
 
 static u32 get_ipg_clk(void)
@@ -323,10 +327,12 @@ static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-	if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
-		return MXC_HCLK; /* OSC 24Mhz */
-#endif
+	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+	    is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+		if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+			return MXC_HCLK; /* OSC 24Mhz */
+	}
+
 	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 
 	return get_ipg_clk() / (perclk_podf + 1);
@@ -337,10 +343,13 @@ static u32 get_uart_clk(void)
 	u32 reg, uart_podf;
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
-		freq = MXC_HCLK;
-#endif
+
+	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+	    is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+		if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+			freq = MXC_HCLK;
+	}
+
 	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
@@ -352,8 +361,14 @@ static u32 get_cspi_clk(void)
 	u32 reg, cspi_podf;
 
 	reg = __raw_readl(&imx_ccm->cscdr2);
-	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
+		     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+	if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
+	    is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+		if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+			return MXC_HCLK / (cspi_podf + 1);
+	}
 
 	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
@@ -405,47 +420,60 @@ static u32 get_emi_slow_clk(void)
 	return root_freq / (emi_slow_podf + 1);
 }
 
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
 static u32 get_mmdc_ch0_clk(void)
 {
 	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-	u32 freq, podf;
 
-	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
-			>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
-
-	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
-		MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
-	case 0:
-		freq = decode_pll(PLL_BUS, MXC_HCLK);
-		break;
-	case 1:
-		freq = mxc_get_pll_pfd(PLL_BUS, 2);
-		break;
-	case 2:
-		freq = mxc_get_pll_pfd(PLL_BUS, 0);
-		break;
-	case 3:
-		/* static / 2 divider */
-		freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+	u32 freq, podf, per2_clk2_podf;
+
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+	    is_cpu_type(MXC_CPU_MX6SL)) {
+		podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
+			MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+		if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
+			per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
+				MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
+			if (is_cpu_type(MXC_CPU_MX6SL)) {
+				if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+					freq = MXC_HCLK;
+				else
+					freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+			} else {
+				if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+					freq = decode_pll(PLL_BUS, MXC_HCLK);
+				else
+					freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+			}
+		} else {
+			per2_clk2_podf = 0;
+			switch ((cbcmr &
+				MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+				MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+			case 0:
+				freq = decode_pll(PLL_BUS, MXC_HCLK);
+				break;
+			case 1:
+				freq = mxc_get_pll_pfd(PLL_BUS, 2);
+				break;
+			case 2:
+				freq = mxc_get_pll_pfd(PLL_BUS, 0);
+				break;
+			case 3:
+				/* static / 2 divider */
+				freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+				break;
+			}
+		}
+		return freq / (podf + 1) / (per2_clk2_podf + 1);
+	} else {
+		podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+			MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+		return get_periph_clk() / (podf + 1);
 	}
-
-	return freq / (podf + 1);
-
-}
-#else
-static u32 get_mmdc_ch0_clk(void)
-{
-	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
-				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
-	return get_periph_clk() / (mmdc_ch0_podf + 1);
 }
-#endif
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_FSL_QSPI
 /* qspi_num can be from 0 - 1 */
 void enable_qspi_clk(int qspi_num)
 {
@@ -606,6 +634,7 @@ u32 imx_get_fecclk(void)
 	return mxc_get_clock(MXC_IPG_CLK);
 }
 
+#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 static int enable_enet_pll(uint32_t en)
 {
 	struct mxc_ccm_reg *const imx_ccm
@@ -630,8 +659,9 @@ static int enable_enet_pll(uint32_t en)
 	writel(reg, &imx_ccm->analog_pll_enet);
 	return 0;
 }
+#endif
 
-#ifndef CONFIG_MX6SX
+#ifdef CONFIG_CMD_SATA
 static void ungate_sata_clock(void)
 {
 	struct mxc_ccm_reg *const imx_ccm =
@@ -640,18 +670,7 @@ static void ungate_sata_clock(void)
 	/* Enable SATA clock. */
 	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 }
-#endif
 
-static void ungate_pcie_clock(void)
-{
-	struct mxc_ccm_reg *const imx_ccm =
-		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* Enable PCIe clock. */
-	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
-}
-
-#ifndef CONFIG_MX6SX
 int enable_sata_clock(void)
 {
 	ungate_sata_clock();
@@ -667,6 +686,16 @@ void disable_sata_clock(void)
 }
 #endif
 
+#ifdef CONFIG_PCIE_IMX
+static void ungate_pcie_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Enable PCIe clock. */
+	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
 int enable_pcie_clock(void)
 {
 	struct anatop_regs *anatop_regs =
@@ -706,7 +735,7 @@ int enable_pcie_clock(void)
 	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
 	/* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_MX6SX
+#ifdef CONFIG_CMD_SATA
 	ungate_sata_clock();
 #endif
 	ungate_pcie_clock();
@@ -714,6 +743,7 @@ int enable_pcie_clock(void)
 	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 			       BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
+#endif
 
 #ifdef CONFIG_SECURE_BOOT
 void hab_caam_clock_enable(unsigned char enable)
@@ -856,6 +886,11 @@ void enable_ipu_clock(void)
 	reg = readl(&mxc_ccm->CCGR3);
 	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
+
+	if (is_mx6dqp()) {
+		setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
+		setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
+	}
 }
 #endif
 /***************************************************/
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 86c8354217..b808627a42 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -71,6 +71,50 @@ void mx6sx_dram_iocfg(unsigned width,
 }
 #endif
 
+#ifdef CONFIG_MX6UL
+void mx6ul_dram_iocfg(unsigned width,
+		      const struct mx6ul_iomux_ddr_regs *ddr,
+		      const struct mx6ul_iomux_grp_regs *grp)
+{
+	struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
+	struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
+
+	mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
+	mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
+
+	/* DDR IO TYPE */
+	writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+	writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+	/* CLOCK */
+	writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+	/* ADDRESS */
+	writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+	writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+	writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+	/* Control */
+	writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+	writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+	writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+	writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+	writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+	/* Data Strobes */
+	writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+	writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+	writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+
+	/* Data */
+	writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+	writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+	writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+	writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+	writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+}
+#endif
+
 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
@@ -243,19 +287,17 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-#ifdef CONFIG_MX6SX
-#define MMDC1(entry, value)	do {} while (0)
-#else
-#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
-#endif
+#define MMDC1(entry, value) do {					  \
+	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))	  \
+		mmdc1->entry = value;					  \
+	} while (0)
+
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		  const struct mx6_mmdc_calibration *calib,
 		  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
 	volatile struct mmdc_p_regs *mmdc0;
-#ifndef CONFIG_MX6SX
 	volatile struct mmdc_p_regs *mmdc1;
-#endif
 	u32 val;
 	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -270,9 +312,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-#ifndef CONFIG_MX6SX
-	mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-#endif
+	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
+		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */
 	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c
index 8dee595eaf..27cabe477d 100644
--- a/arch/arm/cpu/armv7/mx6/hab.c
+++ b/arch/arm/cpu/armv7/mx6/hab.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -111,6 +111,153 @@
  * +------------+ + CSF_PAD_SIZE
  */
 
+#define MAX_RECORD_BYTES     (8*1024) /* 4 kbytes */
+
+struct record {
+	uint8_t  tag;						/* Tag */
+	uint8_t  len[2];					/* Length */
+	uint8_t  par;						/* Version */
+	uint8_t  contents[MAX_RECORD_BYTES];/* Record Data */
+	bool	 any_rec_flag;
+};
+
+char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
+				   "RSN = HAB_ENG_FAIL (0x30)\n",
+				   "RSN = HAB_INV_ADDRESS (0x22)\n",
+				   "RSN = HAB_INV_ASSERTION (0x0C)\n",
+				   "RSN = HAB_INV_CALL (0x28)\n",
+				   "RSN = HAB_INV_CERTIFICATE (0x21)\n",
+				   "RSN = HAB_INV_COMMAND (0x06)\n",
+				   "RSN = HAB_INV_CSF (0x11)\n",
+				   "RSN = HAB_INV_DCD (0x27)\n",
+				   "RSN = HAB_INV_INDEX (0x0F)\n",
+				   "RSN = HAB_INV_IVT (0x05)\n",
+				   "RSN = HAB_INV_KEY (0x1D)\n",
+				   "RSN = HAB_INV_RETURN (0x1E)\n",
+				   "RSN = HAB_INV_SIGNATURE (0x18)\n",
+				   "RSN = HAB_INV_SIZE (0x17)\n",
+				   "RSN = HAB_MEM_FAIL (0x2E)\n",
+				   "RSN = HAB_OVR_COUNT (0x2B)\n",
+				   "RSN = HAB_OVR_STORAGE (0x2D)\n",
+				   "RSN = HAB_UNS_ALGORITHM (0x12)\n",
+				   "RSN = HAB_UNS_COMMAND (0x03)\n",
+				   "RSN = HAB_UNS_ENGINE (0x0A)\n",
+				   "RSN = HAB_UNS_ITEM (0x24)\n",
+				   "RSN = HAB_UNS_KEY (0x1B)\n",
+				   "RSN = HAB_UNS_PROTOCOL (0x14)\n",
+				   "RSN = HAB_UNS_STATE (0x09)\n",
+				   "RSN = INVALID\n",
+				   NULL};
+
+char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
+				   "STS = HAB_FAILURE (0x33)\n",
+				   "STS = HAB_WARNING (0x69)\n",
+				   "STS = INVALID\n",
+				   NULL};
+
+char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
+				   "ENG = HAB_ENG_SCC (0x03)\n",
+				   "ENG = HAB_ENG_RTIC (0x05)\n",
+				   "ENG = HAB_ENG_SAHARA (0x06)\n",
+				   "ENG = HAB_ENG_CSU (0x0A)\n",
+				   "ENG = HAB_ENG_SRTC (0x0C)\n",
+				   "ENG = HAB_ENG_DCP (0x1B)\n",
+				   "ENG = HAB_ENG_CAAM (0x1D)\n",
+				   "ENG = HAB_ENG_SNVS (0x1E)\n",
+				   "ENG = HAB_ENG_OCOTP (0x21)\n",
+				   "ENG = HAB_ENG_DTCP (0x22)\n",
+				   "ENG = HAB_ENG_ROM (0x36)\n",
+				   "ENG = HAB_ENG_HDCP (0x24)\n",
+				   "ENG = HAB_ENG_RTL (0x77)\n",
+				   "ENG = HAB_ENG_SW (0xFF)\n",
+				   "ENG = INVALID\n",
+				   NULL};
+
+char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
+				   "CTX = HAB_CTX_FAB (0xFF)\n",
+				   "CTX = HAB_CTX_ENTRY (0xE1)\n",
+				   "CTX = HAB_CTX_TARGET (0x33)\n",
+				   "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
+				   "CTX = HAB_CTX_DCD (0xDD)\n",
+				   "CTX = HAB_CTX_CSF (0xCF)\n",
+				   "CTX = HAB_CTX_COMMAND (0xC0)\n",
+				   "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
+				   "CTX = HAB_CTX_ASSERT (0xA0)\n",
+				   "CTX = HAB_CTX_EXIT (0xEE)\n",
+				   "CTX = INVALID\n",
+				   NULL};
+
+uint8_t hab_statuses[5] = {
+	HAB_STS_ANY,
+	HAB_FAILURE,
+	HAB_WARNING,
+	HAB_SUCCESS,
+	-1
+};
+
+uint8_t hab_reasons[26] = {
+	HAB_RSN_ANY,
+	HAB_ENG_FAIL,
+	HAB_INV_ADDRESS,
+	HAB_INV_ASSERTION,
+	HAB_INV_CALL,
+	HAB_INV_CERTIFICATE,
+	HAB_INV_COMMAND,
+	HAB_INV_CSF,
+	HAB_INV_DCD,
+	HAB_INV_INDEX,
+	HAB_INV_IVT,
+	HAB_INV_KEY,
+	HAB_INV_RETURN,
+	HAB_INV_SIGNATURE,
+	HAB_INV_SIZE,
+	HAB_MEM_FAIL,
+	HAB_OVR_COUNT,
+	HAB_OVR_STORAGE,
+	HAB_UNS_ALGORITHM,
+	HAB_UNS_COMMAND,
+	HAB_UNS_ENGINE,
+	HAB_UNS_ITEM,
+	HAB_UNS_KEY,
+	HAB_UNS_PROTOCOL,
+	HAB_UNS_STATE,
+	-1
+};
+
+uint8_t hab_contexts[12] = {
+	HAB_CTX_ANY,
+	HAB_CTX_FAB,
+	HAB_CTX_ENTRY,
+	HAB_CTX_TARGET,
+	HAB_CTX_AUTHENTICATE,
+	HAB_CTX_DCD,
+	HAB_CTX_CSF,
+	HAB_CTX_COMMAND,
+	HAB_CTX_AUT_DAT,
+	HAB_CTX_ASSERT,
+	HAB_CTX_EXIT,
+	-1
+};
+
+uint8_t hab_engines[16] = {
+	HAB_ENG_ANY,
+	HAB_ENG_SCC,
+	HAB_ENG_RTIC,
+	HAB_ENG_SAHARA,
+	HAB_ENG_CSU,
+	HAB_ENG_SRTC,
+	HAB_ENG_DCP,
+	HAB_ENG_CAAM,
+	HAB_ENG_SNVS,
+	HAB_ENG_OCOTP,
+	HAB_ENG_DTCP,
+	HAB_ENG_ROM,
+	HAB_ENG_HDCP,
+	HAB_ENG_RTL,
+	HAB_ENG_SW,
+	-1
+};
+
 bool is_hab_enabled(void)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -122,6 +269,28 @@ bool is_hab_enabled(void)
 	return (reg & 0x2) == 0x2;
 }
 
+static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
+{
+	uint8_t idx = 0;
+	uint8_t element = list[idx];
+	while (element != -1) {
+		if (element == tgt)
+			return idx;
+		element = list[++idx];
+	}
+	return -1;
+}
+
+void process_event_record(uint8_t *event_data, size_t bytes)
+{
+	struct record *rec = (struct record *)event_data;
+
+	printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
+	printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
+	printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
+	printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
+}
+
 void display_event(uint8_t *event_data, size_t bytes)
 {
 	uint32_t i;
@@ -137,6 +306,8 @@ void display_event(uint8_t *event_data, size_t bytes)
 		else
 			printf(" 0x%02x", event_data[i]);
 	}
+
+	process_event_record(event_data, bytes);
 }
 
 int get_hab_status(void)
@@ -252,7 +423,8 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 					 * do cache flushes. don't think any
 					 * exist, so we ignore them.
 					 */
-					writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+					if (!is_mx6dqp())
+						writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
 				} else if (is_cpu_type(MXC_CPU_MX6DL) ||
 					   is_cpu_type(MXC_CPU_MX6SOLO)) {
 					writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 29de6243dc..8ad8da8465 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -62,12 +62,12 @@ u32 get_cpu_rev(void)
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&anatop->digprog_sololite);
 	u32 type = ((reg >> 16) & 0xff);
-	u32 major;
+	u32 major, cfg = 0;
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);
 		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-		u32 cfg = readl(&scu->config) & 3;
+		cfg = readl(&scu->config) & 3;
 		type = ((reg >> 16) & 0xff);
 		if (type == MXC_CPU_MX6DL) {
 			if (!cfg)
@@ -81,6 +81,13 @@ u32 get_cpu_rev(void)
 
 	}
 	major = ((reg >> 8) & 0xff);
+	if ((major >= 1) &&
+	    ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
+		major--;
+		type = MXC_CPU_MX6QP;
+		if (cfg == 1)
+			type = MXC_CPU_MX6DP;
+	}
 	reg &= 0xff;		/* mx6 silicon revision */
 	return (type << 12) | (reg + (0x10 * (major + 1)));
 }
@@ -309,11 +316,10 @@ static void imx_set_wdog_powerdown(bool enable)
 {
 	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
-
-#ifdef CONFIG_MX6SX
 	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
-	writew(enable, &wdog3->wmcr);
-#endif
+
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+		writew(enable, &wdog3->wmcr);
 
 	/* Write to the PDE (Power Down Enable) bit */
 	writew(enable, &wdog1->wmcr);
@@ -335,9 +341,12 @@ static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg;
+	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	writel(0, &mxc_ccm->ccdr);
+	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	writel(reg, &mxc_ccm->ccdr);
 }
 
 static void init_bandgap(void)
@@ -520,7 +529,7 @@ void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
-	if (is_cpu_type(MXC_CPU_MX6SX))
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
 		return;
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs