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| author | Stephen Warren <swarren@nvidia.com> | 2014-03-21 12:29:00 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-04-17 08:41:06 -0700 |
| commit | 1fa3a634137c9f40b207cff1079fe0dfbd9b3378 (patch) | |
| tree | 97f9c3acf7f6316007380d674c97514a769b302b /arch/arm/cpu/tegra114-common/funcmux.c | |
| parent | 803d01edc27b0ec23a0b0416a65a6106c8b79103 (diff) | |
| download | talos-obmc-uboot-1fa3a634137c9f40b207cff1079fe0dfbd9b3378.tar.gz talos-obmc-uboot-1fa3a634137c9f40b207cff1079fe0dfbd9b3378.zip | |
ARM: tegra: Tegra114 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra114-common/funcmux.c')
| -rw-r--r-- | arch/arm/cpu/tegra114-common/funcmux.c | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/arch/arm/cpu/tegra114-common/funcmux.c b/arch/arm/cpu/tegra114-common/funcmux.c index 5af755034d..52441c71e6 100644 --- a/arch/arm/cpu/tegra114-common/funcmux.c +++ b/arch/arm/cpu/tegra114-common/funcmux.c @@ -29,20 +29,24 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_UART4: switch (config) { case FUNCMUX_UART4_GMI: - pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD); - - pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT); - pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT); - pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT); - pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT); - - pinmux_tristate_disable(PINGRP_GMI_A16); - pinmux_tristate_disable(PINGRP_GMI_A17); - pinmux_tristate_disable(PINGRP_GMI_A18); - pinmux_tristate_disable(PINGRP_GMI_A19); + pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7, + PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0, + PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1, + PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7, + PMUX_FUNC_UARTD); + + pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT); + + pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7); break; } break; |
