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| author | Kuo-Jung Su <dantesu@faraday-tech.com> | 2013-07-29 13:51:43 +0800 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-09-14 12:08:00 +0200 |
| commit | 771f74c3d31a265bae103b2b407286ec03a4589b (patch) | |
| tree | b0b3137f121cb24281d450872803646e250a963c /arch/arm/cpu/s3c44b0/cache.c | |
| parent | fb8d49cb4492332066a2dc775ef3c57c49fd1eca (diff) | |
| download | talos-obmc-uboot-771f74c3d31a265bae103b2b407286ec03a4589b.tar.gz talos-obmc-uboot-771f74c3d31a265bae103b2b407286ec03a4589b.zip | |
arm: dma_alloc_coherent: malloc() -> memalign()
Even though the MMU/D-cache is off, some DMA engines still
expect strict address alignment.
For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet
controllers expect the tx/rx descriptors should always be aligned
to 16-bytes boundary.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Diffstat (limited to 'arch/arm/cpu/s3c44b0/cache.c')
0 files changed, 0 insertions, 0 deletions
