diff options
| author | Mike Williams <mike@mikebwilliams.com> | 2011-07-22 04:01:30 +0000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-07-28 21:27:36 +0200 |
| commit | 1626308797ac4184e73e56d275a1b8da11a62d5b (patch) | |
| tree | d12fd0d610303c3d2351d8ace314a643f20e0fc9 /arch/arm/cpu/ixp | |
| parent | 2469c4b2dbdd601a4e44ecf9925b99bd2cd1b43f (diff) | |
| download | talos-obmc-uboot-1626308797ac4184e73e56d275a1b8da11a62d5b.tar.gz talos-obmc-uboot-1626308797ac4184e73e56d275a1b8da11a62d5b.zip | |
cleanup: Fix typos and misspellings in various files.
Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address
Signed-off-by: Mike Williams <mike@mikebwilliams.com>
Diffstat (limited to 'arch/arm/cpu/ixp')
| -rw-r--r-- | arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/ixp/npe/include/IxNpeA.h | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/ixp/npe/include/IxQMgr.h | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c index 09f69ce322..642e67ae81 100644 --- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c +++ b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c @@ -386,7 +386,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId, &dispatchQInfo[qId].statusMask); - /* Set the interupt source is this queue is in the range 0-31 */ + /* Set the interrupt source is this queue is in the range 0-31 */ if (qId < IX_QMGR_MIN_QUEUPP_QID) { ixQMgrAqmIfIntSrcSelWrite (qId, srcSel); diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h index 0ee4123557..4e0de8235c 100644 --- a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h +++ b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h @@ -279,7 +279,7 @@ typedef struct BOOL portInitialized; UINT32 npeId; /**< NpeId for this port */ IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */ - IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */ + IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */ } IxEthAccPortDataInfo; extern IxEthAccPortDataInfo ixEthAccPortData[]; diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeA.h b/arch/arm/cpu/ixp/npe/include/IxNpeA.h index 7427cc41c8..90669c27e7 100644 --- a/arch/arm/cpu/ixp/npe/include/IxNpeA.h +++ b/arch/arm/cpu/ixp/npe/include/IxNpeA.h @@ -717,7 +717,7 @@ typedef struct */ typedef struct { - UINT32 rxBitField; /**< Recieved bit field */ + UINT32 rxBitField; /**< Received bit field */ UINT32 atmCellHeader; /**< ATM Cell Header */ UINT32 rsvdWord0; /**< Reserved field */ UINT16 currMbufLen; /**< Mbuf Length */ diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgr.h b/arch/arm/cpu/ixp/npe/include/IxQMgr.h index 165ed96e54..03d7e07092 100644 --- a/arch/arm/cpu/ixp/npe/include/IxQMgr.h +++ b/arch/arm/cpu/ixp/npe/include/IxQMgr.h @@ -570,7 +570,7 @@ typedef enum * @brief Queue interrupt source select. * * This enum defines the different source conditions on a queue that result in - * an interupt being fired by the AQM. Interrupt source is configurable for + * an interrupt being fired by the AQM. Interrupt source is configurable for * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the * NE(Nearly Empty) status flag. * diff --git a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h index f7194e72ec..b65d621e3b 100644 --- a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h +++ b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h @@ -404,7 +404,7 @@ * * @def IX_ETH_ACC_RX_FRAME_ETH_Q * -* @brief Eth0/Eth1 NPE Frame Recieve Q. +* @brief Eth0/Eth1 NPE Frame Receive Q. * * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration * |
