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| author | York Sun <yorksun@freescale.com> | 2015-03-20 19:28:08 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-23 08:55:55 -0700 |
| commit | 207774b213caa3c72ebd6c9f6d1e4a3a666938b7 (patch) | |
| tree | b0249e1f667a1c607cc1409dfbe7db7fb9b62840 /arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | |
| parent | 19f9175027b14f11b5a30df17ce76fb6f64dc724 (diff) | |
| download | talos-obmc-uboot-207774b213caa3c72ebd6c9f6d1e4a3a666938b7.tar.gz talos-obmc-uboot-207774b213caa3c72ebd6c9f6d1e4a3a666938b7.zip | |
armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 886576ef99..53bdb4487c 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -224,6 +224,9 @@ ENTRY(secondary_boot_func) /* physical address of this cpus spin table element */ add x11, x1, x0 + ldr x0, =__real_cntfrq + ldr x0, [x0] + msr cntfrq_el0, x0 /* set with real frequency */ str x9, [x11, #16] /* LPID */ mov x4, #1 str x4, [x11, #8] /* STATUS */ @@ -275,6 +278,9 @@ ENDPROC(secondary_switch_to_el1) /* 64 bit alignment for elements accessed as data */ .align 4 + .global __real_cntfrq +__real_cntfrq: + .quad COUNTER_FREQUENCY .globl __secondary_boot_code_size .type __secondary_boot_code_size, %object /* Secondary Boot Code ends here */ |
