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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:18:49 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:09:14 -0800 |
| commit | b87e6f88e9218da3de371bb6cc8a34924153178e (patch) | |
| tree | fe1c672d5af630646b8c1193b9f00c2132e857f8 /arch/arm/cpu/armv8/fsl-lsch3/cpu.c | |
| parent | 49fd1f3f265efc00d61effa995bd6a733bf273d8 (diff) | |
| download | talos-obmc-uboot-b87e6f88e9218da3de371bb6cc8a34924153178e.tar.gz talos-obmc-uboot-b87e6f88e9218da3de371bb6cc8a34924153178e.zip | |
armv8/fsl-lsch3: Add support for second DDR clock
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-lsch3/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 2aaac017d2..42cee65546 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -367,6 +367,7 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); + printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2)); puts("\n"); return 0; |
