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| author | York Sun <yorksun@freescale.com> | 2014-09-08 12:20:00 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-25 08:36:19 -0700 |
| commit | 40f8dec54d7803975aed1c88327002c95ea99908 (patch) | |
| tree | 83f7778c9179e518631ce308f3504a1e6e634c57 /arch/arm/cpu/armv8/fsl-lsch3/cpu.c | |
| parent | f43b4356a794be647011132f4f2dc970a29a9dd5 (diff) | |
| download | talos-obmc-uboot-40f8dec54d7803975aed1c88327002c95ea99908.tar.gz talos-obmc-uboot-40f8dec54d7803975aed1c88327002c95ea99908.zip | |
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-lsch3/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index c129d032f4..47b947f44f 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/arch-fsl-lsch3/immap_lsch3.h> #include "cpu.h" +#include "mp.h" #include "speed.h" #include <fsl_mc.h> @@ -434,3 +435,15 @@ int cpu_eth_init(bd_t *bis) #endif return error; } + + +int arch_early_init_r(void) +{ + int rv; + rv = fsl_lsch3_wake_seconday_cores(); + + if (rv) + printf("Did not wake secondary cores\n"); + + return 0; +} |
