tegra: Correct PLL access in ap20.c and clock.c

Correct this warning seen by Albert:

ap20.c:44:18: warning: array subscript is above array bounds

There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

2 files changed, 6 insertions, 4 deletions

diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index 698bfd0e17..24e582d95c 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -77,8 +77,10 @@ static int ap20_cpu_is_cortexa9(void)
 
 void init_pllx(void)
 {
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll_simple *pll =
+		&clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
 	u32 reg;
 
 	/* If PLLX is already enabled, just return */
diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c
index ccad351639..602589cde0 100644
--- a/arch/arm/cpu/armv7/tegra2/clock.c
+++ b/arch/arm/cpu/armv7/tegra2/clock.c
@@ -426,7 +426,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
 	struct clk_rst_ctlr *clkrst =
 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 
-	assert(clock_id_isvalid(clkid));
+	assert(clock_id_is_pll(clkid));
 	return &clkrst->crc_pll[clkid];
 }
 
@@ -439,7 +439,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
 	assert(clkid != CLOCK_ID_USB);
 
 	/* Safety check, adds to code size but is small */
-	if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB)
+	if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
 		return -1;
 	data = readl(&pll->pll_base);
 	*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;