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authorLokesh Vutla <lokeshvutla@ti.com>2013-02-04 04:22:05 +0000
committerTom Rini <trini@ti.com>2013-03-11 11:06:10 -0400
commitef1697e99f482b0e6a64df465ffff77251719abb (patch)
treeaee33c7b3d3aa89a16fdf4c41faca2fd01f2a674 /arch/arm/cpu/armv7/omap5/hw_data.c
parentc43c8339fedc86c6c23990eaabff6feaf6742e7b (diff)
downloadtalos-obmc-uboot-ef1697e99f482b0e6a64df465ffff77251719abb.tar.gz
talos-obmc-uboot-ef1697e99f482b0e6a64df465ffff77251719abb.zip
ARM: OMAP5: Clean up iosettings code
There is some code duplication in the ddr io settings code. This is avoided by moving the data to a Soc specific place and letting the code generic. This avoids unnessecary code addition for future socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 320d5bba68..7ca6709d0b 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -32,6 +32,7 @@
#include <asm/arch/clocks.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
+#include <asm/emif.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
@@ -414,6 +415,24 @@ void enable_non_essential_clocks(void)
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
+const struct ctrl_ioregs ioregs_omap5430 = {
+ .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es1 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
@@ -438,3 +457,20 @@ void hw_data_init(void)
*ctrl = &omap5_ctrl;
}
+
+void get_ioregs(const struct ctrl_ioregs **regs)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+ case OMAP5430_ES1_0:
+ *regs = &ioregs_omap5430;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = &ioregs_omap5432_es1;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+}
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