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| author | SRICHARAN R <r.sricharan@ti.com> | 2013-02-04 04:22:02 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 11:06:10 -0400 |
| commit | 3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301 (patch) | |
| tree | eba59f79109e214726acd882ae64083641700d82 /arch/arm/cpu/armv7/omap5/hw_data.c | |
| parent | ee9447bfe37a646a8dce182e6f625f27c10512a0 (diff) | |
| download | talos-obmc-uboot-3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301.tar.gz talos-obmc-uboot-3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301.zip | |
ARM: OMAP4+: Clean up the pmic code
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index df375f99a6..13e618d342 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -30,12 +30,15 @@ #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> #include <asm/arch/clocks.h> +#include <asm/omap_gpio.h> #include <asm/io.h> struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; struct dplls const **dplls_data = (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = + (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -179,6 +182,44 @@ struct dplls omap5_dplls_es1 = { .usb = usb_dpll_params_1920mhz }; +struct pmic_data palmas = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, +}; + +struct vcores_data omap5430_volts = { + .mpu.value = VDD_MPU, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + +struct vcores_data omap5432_volts = { + .mpu.value = VDD_MPU_5432, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE_5432, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM_5432, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -380,11 +421,13 @@ void hw_data_init(void) case OMAP5430_ES1_0: *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; + *omap_vcores = &omap5430_volts; break; case OMAP5432_ES1_0: *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; + *omap_vcores = &omap5432_volts; break; default: |
