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| author | Akshay Saraswat <akshay.s@samsung.com> | 2015-02-20 13:27:17 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-02-28 18:03:46 +0900 |
| commit | 7e514eef02d2508a19be13d3efdf747c4e7ef5c5 (patch) | |
| tree | aff4796e19e86f23d01e1392961984740cb1da6d /arch/arm/cpu/armv7/exynos/soc.c | |
| parent | f0f76b0a4c7181b2cbde39ec04eac8973cd4ad1f (diff) | |
| download | talos-obmc-uboot-7e514eef02d2508a19be13d3efdf747c4e7ef5c5.tar.gz talos-obmc-uboot-7e514eef02d2508a19be13d3efdf747c4e7ef5c5.zip | |
Exynos542x: add L2 control register configuration
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switching.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7/exynos/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/soc.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index 427f54c7e6..68eb8e7fc9 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -37,30 +37,32 @@ void enable_caches(void) */ static void exynos5_set_l2cache_params(void) { - unsigned int val = 0; + unsigned int l2ctlr = 0, l2actlr = 0; /* Read L2CTLR value */ - asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(l2ctlr)); - /* Set cache setup and latency cycles */ - val |= CACHE_TAG_RAM_SETUP | - CACHE_DATA_RAM_SETUP | - CACHE_TAG_RAM_LATENCY | + /* Set cache latency cycles */ + l2ctlr |= CACHE_TAG_RAM_LATENCY | CACHE_DATA_RAM_LATENCY; - /* Write new vlaue to L2CTLR */ - asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); - if (proid_is_exynos5420() || proid_is_exynos5800()) { /* Read L2ACTLR value */ - asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (l2actlr)); /* Disable clean/evict push to external */ - val |= CACHE_DISABLE_CLEAN_EVICT; + l2actlr |= CACHE_DISABLE_CLEAN_EVICT; /* Write new vlaue to L2ACTLR */ - asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); + asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (l2actlr)); + } else { + /* Set cache setup cycles */ + l2ctlr |= CACHE_TAG_RAM_SETUP | + CACHE_DATA_RAM_SETUP; } + + /* Write new vlaue to L2CTLR */ + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(l2ctlr)); } /* |
