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authorSteve Kipisz <s-kipisz2@ti.com>2013-03-08 07:40:58 +0000
committerTom Rini <trini@ti.com>2013-03-22 11:12:53 -0400
commit1e7e374b3577888ff6f9e3273fa0ad67e2dc45bf (patch)
tree81105e92c234be3141e32a5f950a7f29a6743b4d /arch/arm/cpu/armv7/am33xx/sys_info.c
parent951d582778a221a79682c4a2619dfcdb7d05d54e (diff)
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am33xx:ddr:Fix config_sdram to work for all DDR
The original write to sdram_config is correct for DDR3 but incorrect for DDR2 so SPL was hanging. For DDR2, the write to sdram_config should be after the writes to ref_ctrl. This was working for DDR3 because there was a write of 0x2800 to ref_ctrl before a write to sdram_config. Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3), Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3) Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/sys_info.c')
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