diff options
| author | Tom Rini <trini@ti.com> | 2015-06-05 15:51:11 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-06-15 10:57:26 -0400 |
| commit | 7c352cd38d0ad7a25f98592182704667dfde37a8 (patch) | |
| tree | ab155ec66d04a7a7e7096cb41fdf1eeaa1d200bb /arch/arm/cpu/armv7/am33xx/emif4.c | |
| parent | 37be54fd1351a177c061c2c351ffdd53efaebb59 (diff) | |
| download | talos-obmc-uboot-7c352cd38d0ad7a25f98592182704667dfde37a8.tar.gz talos-obmc-uboot-7c352cd38d0ad7a25f98592182704667dfde37a8.zip | |
am33xx: Re-enable SW levelling for DDR2
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet. In other cases
update the call to be as functional as before and check an already
programmed value in.
Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/emif4.c')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/emif4.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 9cf816c89a..27fa3fb462 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -124,8 +124,9 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); - /* Allow EMIF to control DDR_RESET */ - writel(0x00000000, &ddrctrl->ddrioctrl); + if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) + /* Allow EMIF to control DDR_RESET */ + writel(0x00000000, &ddrctrl->ddrioctrl); #endif /* Program EMIF instance */ |
