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authorJoel Stanley <joel@jms.id.au>2017-06-26 13:33:24 +0930
committerJoel Stanley <joel@jms.id.au>2017-06-26 13:33:52 +0930
commited9e4abbf3f0aab348bc64d5439aadda03f42e4c (patch)
treeb2e1b8829c772ff3a5dd1affa2d63d2f7d897310 /api/api_storage.c
parentf7ef560f809f140185b6241d83b76de80dcfcf37 (diff)
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aspeed: Update platform_g5.S to version 16
1.[P1] Add margin check/retry for DDR4 Vref training margin. 2.[P1] Add margin check/retry for DDR3/DDR4 read timing training margin. 3.[P2] Add initial sequence for LPC controller 4.[P2] Add initial full-chip reset option 5.[P3] Add 10ms delay after DDR reset Signed-off-by: Joel Stanley <joel@jms.id.au>
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