diff options
| author | Stefan Roese <sr@denx.de> | 2007-12-29 09:23:11 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-12-29 09:23:11 +0100 |
| commit | feaa43f3a8f465cbf01ffa1b23b6b52431819a52 (patch) | |
| tree | 3ee393d421c72a882d27b1de5978a2a9befce062 | |
| parent | 8697e6a19b10f514511b6a9c86de88bd108c4f8d (diff) | |
| parent | e174ac34adf5d5653df12bc3cf19c52063a71269 (diff) | |
| download | talos-obmc-uboot-feaa43f3a8f465cbf01ffa1b23b6b52431819a52.tar.gz talos-obmc-uboot-feaa43f3a8f465cbf01ffa1b23b6b52431819a52.zip | |
Merge branch 'for-1.3.2-ver2'
Conflicts:
cpu/ppc4xx/fdt.c
include/configs/kilauea.h
include/configs/sequoia.h
Signed-off-by: Stefan Roese <sr@denx.de>
236 files changed, 18051 insertions, 3537 deletions
@@ -1,3 +1,687 @@ +commit 467bcee11fe26ad422f2de971aa70866079870f2 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Fri Dec 14 15:36:18 2007 +0100 + + cfi_flash: Add manufacturer-specific fixups + + Run fixups based on the JEDEC manufacturer ID independent of the + command set ID. + + This changes current behaviour: Previously, geometry reversal for AMD + chips were done based on the command set ID, while they are now done + based on the JEDEC manufacturer and device ID. + + Also add fixup for top-boot Atmel chips. A fixup is needed for + AT49BV6416(T) too, but since u-boot currently only reads the low byte + of the device ID, there's no way to tell it apart from AT49BV642D, + which should not have this fixup. Since AT49BV642D support is + necessary to get ATNGW100 board support into mainline, I've commented + out the fixup for now. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 0ddf06ddf6b4bd057ad4c5f0dffea7870ba06a2a +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Fri Dec 14 15:36:17 2007 +0100 + + cfi_flash: Add cmdset-specific init functions + + Move things like reading JEDEC IDs and fixing up geometry reversal + into separate functions. The geometry reversal fixup is now performed + by altering the qry structure directly, which makes the sector init + code slightly cleaner. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit e23741f4a6d8047520ef0d4971762749b3587d32 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Fri Dec 14 15:36:16 2007 +0100 + + cfi_flash: Read whole QRY structure in one go + + Read out the whole CFI Standard Query structure after successful cfi + identification. This allows subsequent code to access this information + directly without having to go through flash_read_uchar() and friends. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit df9c25ea04b38a0e05d4f8c73c5cc144cdafa7db +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Mon Dec 17 11:02:44 2007 +0100 + + AVR32: Fix logic inversion in disable_interrupts() + + disable_interrupts() should return nonzero if interrupts were + _enabled_ before, not disabled. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit acac475212cbedb17b321a363a1c878e2b47b37f +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Fri Dec 14 16:51:22 2007 +0100 + + AVR32: Enable interrupts at bootup + + The timer code depends on the timer interrupt to keep track of the + upper 32 bits of the cycle counter. This obviously doesn't work when + interrupts are disabled the whole time. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 9570bcd87f4db255514f43b6701746c412f8fef0 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Thu Nov 15 10:03:45 2007 +0100 + + AVR32: Fix wrong pin setup for USART3 + + As reported by Gerhard Berghofer: + + in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18 + instead of PB18 and PB19. + + which is obviously correct. There's currently no code that uses + USART3, but custom boards may run into problems. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 09ea0de03dcc3ee7af045b0b572227bda2c1c918 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Thu Nov 1 12:44:20 2007 +0100 + + README: Remove ATSTK1000 daughterboard list + + As noted by Kim Phillips, these lists tend to become out of date. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit c81cbbad21cb0ae983e2e796211202234cdc8be2 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Tue Oct 30 14:56:36 2007 +0100 + + Add ATSTK100[234] to MAINTAINERS + + Add all the ATSTK1000 daughterboards to MAINTAINERS along with their + "mother". Also update the entry for ATSTK1000 to be not only about the + AP7000 CPU; it's intended to handle all CPUs in the AT32AP family. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 64ff2357b1727213803591813dbc779c924bf772 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Mon Oct 29 13:02:54 2007 +0100 + + AVR32: Add support for the ATSTK1004 board + + ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU, + which is a derivative of AT32AP7000. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 667568db157f374b85abd7e03596ddd1f0b25681 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Mon Oct 29 13:02:54 2007 +0100 + + AVR32: Add support for the ATSTK1003 board + + ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU, + which is a derivative of AT32AP7000. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 5fee84a794a51ec830548cda485a770efb018b92 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Mon Oct 29 13:23:33 2007 +0100 + + AVR32: Make some AT32AP700x peripherals optional + + Add a chip-features file providing definitions of the form + + AT32AP700x_CHIP_HAS_<peripheral> + + to indicate the availability of the given peripheral on the currently + selected chip. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 36f28f8a9605ee5dcfa330482cfc62171261af97 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Mon Oct 29 13:09:56 2007 +0100 + + AVR32: Rename at32ap7000 -> at32ap700x + + The SoC-specific code for all the AT32AP700x CPUs is practically + identical; the only difference is that some chips have less features + than others. By doing this rename, we can add support for the AP7000 + derivatives simply by making some features conditional. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 4d5fa99c73f354e7cf985efcf417ea55ca2f6a5e +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Fri Jun 29 18:22:34 2007 +0200 + + atmel_mci: Show SR when block read fails + + Show controller status as well as card status when an error occurs + during block read. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 12d30aa79779c2aa7a998bbae4c075f822a53004 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Thu Dec 13 12:56:34 2007 +0100 + + cfi_flash: Use map_physmem() and unmap_physmem() + + Use map_physmem() and unmap_physmem() to convert from physical to + virtual addresses. This gives the arch a chance to provide an uncached + mapping for flash accesses. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 4d7d6936eb29af7cca330937808312aa5f61454d +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Thu Dec 13 12:56:33 2007 +0100 + + Introduce map_physmem() and unmap_physmem() + + map_physmem() returns a virtual address which can be used to access a + given physical address without involving the cache. unmap_physmem() + should be called when the virtual address returned by map_physmem() is + no longer needed. + + This patch adds a stub implementation which simply returns the + physical address cast to a uchar * for all architectures except AVR32, + which converts the physical address to an uncached virtual mapping. + unmap_physmem() is a no-op on all architectures, but if any + architecture needs to do such mappings through the TLB, this is the + hook where those TLB entries can be invalidated. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit cdbaefb5f5f03e54455d0439dcf6dbd97ead1f9d +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Thu Dec 13 12:56:32 2007 +0100 + + cfi_flash: Introduce read and write accessors + + Introduce flash_read{8,16,32,64) and flash_write{8,16,32,64} and use + them to access the flash memory. This makes it clearer when the flash + is actually being accessed; merely dereferencing a volatile pointer + looks just like any other kind of access. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 812711ce6b3a386125dcf0d6a59588e461abbb87 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Thu Dec 13 12:56:31 2007 +0100 + + Implement __raw_{read,write}[bwl] on all architectures + + This adds implementations of __raw_read[bwl] and __raw_write[bwl] to + m68k, ppc, nios and nios2. The m68k and ppc implementations were taken + from Linux. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit be60a9021c82fc5aecd5b2b1fc96f70a9c81bbcd +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sat Oct 6 18:55:36 2007 +0200 + + cfi_flash: Reorder functions and eliminate extra prototypes + + Reorder the functions in cfi_flash.c so that each function only uses + functions that have been defined before it. This allows the static + prototype declarations near the top to be eliminated and might allow + gcc to do a better job inlining functions. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 3055793bcbdf24b1f8117f606ffb766d32eb766f +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Thu Dec 13 12:56:29 2007 +0100 + + cfi_flash: Make some needlessly global functions static + + Make functions not declared in any header file static. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 7e5b9b471518c5652febc68ba62b432193d6abf4 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Thu Dec 13 12:56:28 2007 +0100 + + cfi_flash: Break long lines + + This patch tries to keep all lines in the cfi_flash driver below 80 + columns. There are a few lines left which don't fit this requirement + because I couldn't find any trivial way to break them (i.e. it would + take some restructuring, which I intend to do in a later patch.) + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 42026c9cb3a76849b41e6e24abfb7b56807a5c1a +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Tue Dec 11 13:59:57 2007 +0100 + + CFI: synchronize command offsets with Linux CFI driver + + Fixes non-working CFI Flash on the Inka4x0 board. + + Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> + +commit 8ff3de61fc5f9b3b21647bce081a3b7f710f0d4d +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri Dec 7 12:17:34 2007 -0600 + + Handle MPC85xx PCIe reset errata (PCI-Ex 38) + + On the MPC85xx boards that have PCIe enable the PCIe errata fix. + (MPC8544DS, MPC8548CDS, MPC8568MDS). + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 82ac8c97145a4c3bf8b3dbfad00fa96e920f9b9c +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri Dec 7 12:04:30 2007 -0600 + + Update Freescale MPC85xx ADS/CDS/MDS board config + + * Enabled CONFIG_CMD_ELF + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit d435793229ce29a42797c1edc39f5b34f987f91a +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri Dec 7 04:59:26 2007 -0600 + + Handle Asynchronous DDR clock on 85xx + + The MPC8572 introduces the concept of an asynchronous DDR clock with + regards to the platform clock. + + Introduce get_ddr_freq() to report the DDR freq regardless of sync/async + mode. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 22abb2d2eaf7b795a6923c6273ec9cb53fda9a10 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 10:34:28 2007 -0600 + + Update Freescale MPC85xx ADS/CDS/MDS board config + + * Removed some misc environment setup + * Enabled CONFIG_CMDLINE_EDITING + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 415a613babb84d5e5d5b42e8e553868c71fc3a64 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 10:47:44 2007 -0600 + + Move the MPC8541/MPC8555/MPC8548 CDS board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit c2d943ffbfd3359b3b45d177b437379d2cb86fbf +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 10:16:18 2007 -0600 + + Move the MPC8540 ADS board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 870ceac5b3a3486c109396e005af81ae762b5710 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 10:14:50 2007 -0600 + + Move the MPC8560 ADS board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit acbca876fb3fec25cd9c55b0efc81ff618ff5262 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 10:13:47 2007 -0600 + + Move the MPC8568 MDS board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit a853d56c59b33415304531443633808736acfc6e +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 02:18:59 2007 -0600 + + Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx + + We already had defines for LAWAR_TRGT_IF_* that we should use + rather than creating new ones. Also, added some missing defines for + PCIE targets. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 04db400892da37b76a585e332a0c137954ad2015 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 02:10:09 2007 -0600 + + Stop using immap_t on 85xx + + In the future the offsets to various blocks may not be in same location. + Move to using CFG_MPC85xx_*_ADDR as the base of the registers + instead of getting it via &immap. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 2714223f8e04ab3e4133ff65872eef366d90bfea +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 01:23:09 2007 -0600 + + Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit c480861bf000156e6a3e932c258db59ff2212dd3 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 01:06:19 2007 -0600 + + Update MPC8568 MDS to use libfdt + + Updated the MPC8568 MDS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 1563f56e0c68f6920f956382d6d13bee3f01c0f7 +Author: Haiying Wang <Haiying.Wang@freescale.com> +Date: Wed Nov 14 15:52:06 2007 -0500 + + Add PCI Express support on MPC8568MDS + + Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit b90d25497625b90ffa3f2911a0895ca237556ff5 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 00:11:44 2007 -0600 + + Update MPC85xx CDS to use libfdt + + Updated the MPC85xx CDS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 0fd5ec66b10521a057ad73e69ab5f0f9eafba255 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Nov 28 22:54:27 2007 -0600 + + Update MPC8540 ADS to use libfdt + + Updated the MPC8540 ADS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 5ce715802f6c50dc78b3405b92f184b1e3710519 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Nov 28 22:40:31 2007 -0600 + + Update MPC8560 ADS to use libfdt + + Updated the MPC8560 ADS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit aafeefbdb8b029f5ca2a195598d0a501a606eea9 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Nov 28 00:36:33 2007 -0600 + + Stop using immap_t for cpm offset on 85xx + + In the future the offsets to various blocks may not be in same location. + Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers + instead of getting it via &immap->im_cpm. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit f59b55a5b8fcadaa99781ba48e7a38e956afa527 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Nov 27 23:25:02 2007 -0600 + + Stop using immap_t for guts offset on 85xx + + In the future the offsets to various blocks may not be in same location. + Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers + instead of getting it via &immap->im_gur. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 50c03c8cf494d91cdec39670d95337c743e16ec9 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Nov 27 22:42:34 2007 -0600 + + Update MPC8544 DS config + + * Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2 + * Removed some misc environment setup + * Moved to using fdtfile & fdtaddr as fdt env var names + * Enabled CONFIG_CMDLINE_EDITING + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit addce57e2e4c49e77ffb2020a84690713bb18b47 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Nov 26 17:12:24 2007 -0600 + + Update MPC8544DS to use libfdt + + Updated the MPC8544DS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit f852ce72f100cabd1f11c21c085a0ad8eca9fb65 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Nov 29 00:15:30 2007 -0600 + + Add libfdt based ft_cpu_setup for mpc85xx + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 9692c2734a47f23b44a0f68042a3e2ca8d1bfb39 +Author: Stefan Roese <sr@denx.de> +Date: Sat Dec 8 08:25:09 2007 +0100 + + CFI: Coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 81b20ccc2d795ae9a1199db5a50ad9c28d1e4d22 +Author: Michael Schwingen <michael@schwingen.org> +Date: Fri Dec 7 23:35:02 2007 +0100 + + CFI: support JEDEC flash roms in CFI-flash framework + + The following patch adds support for non-CFI flash ROMS, by hooking into the + CFI flash code and using most of its code, as recently discussed here in the + thread "Mixing CFI and non-CFI flashs". + + Signed-off-by: Michael Schwingen <michael@schwingen.org> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c01b17dd856fa120b2970f50d9598546a4927ec3 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Wed Nov 28 21:24:50 2007 -0500 + + Conditionally compile fdt_fixup_ethernet() + + Fix compiler warnings: On boards that don't have ethernets defined, + don't compile fdt_fixup_ethernet(). + +commit 246d4ae6bc282bc1841224e1c5fc49dc925e0bf7 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Nov 27 21:59:46 2007 -0600 + + Convert boards that set memory node to use fdt_fixup_memory() + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 151c8b09b35eebe8fd9139cb6c1d91c27b22f058 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Nov 26 17:06:15 2007 -0600 + + Added fdt_fixup_stdout that uses aliases to set linux,stdout-path + + We use a combination of the serialN alias and CONFIG_CONS_INDEX to + determine which serial alias we should set linux,stdout-path to. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 3c9272813fad84c691d0e4989bb18a3ffebdebfc +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Nov 26 14:57:45 2007 -0600 + + Add common memory fixup function + + Add the function fdt_fixup_memory() to fixup the /memory node of the fdt + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 9c9109e7fcf7ac2ca19c95b8ac54b8d1c773b157 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Nov 26 11:19:12 2007 -0600 + + Conditionally compile fdt_support.c + + Modify common/Makefile to conditionally compile fdt_support.c based + on CONFIG_OF_LIBFDT. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit d88e7ba0980773479e1a64badb293116071b7ef0 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Nov 26 10:41:40 2007 -0600 + + Fix build breakage due to libfdt import + + The IDS8247 got lost in the update and need an API update + do to rename of functions in libfdt. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 28f384b171bbf1fb2dafb1046e6d259a6b2f8714 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Fri Nov 23 19:43:20 2007 -0500 + + Add spaces around the = in the fdt print format. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 29592ecba3b932b9b152bcec6c0c0806412db4a3 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Fri Dec 7 01:25:38 2007 +0900 + + sh: Moved driver of the SuperH dependence + + The composition of the directory in the drivers/ changed. + I moved SuperH serial driver and marubun PCMCIA driver. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 41be969f4957115ed7b1fe8b890bfaee99d7a7a2 +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Dec 6 10:21:19 2007 +0100 + + Release v1.3.1 + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit cf5933ba1e97a1cd8f5f24070e820f21d976eaeb +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Dec 6 10:21:03 2007 +0100 + + ADS5121 Board: fix compile problem. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 8d4f040a3c15036a6ea25a9c39e7d89fefa8440d +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Dec 3 00:15:28 2007 +0100 + + Prepare for 1.3.1-rc1 + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 260eea5676ca46903a335686cc020b29c4ca46fe +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Thu Nov 29 01:21:54 2007 +0900 + + sh: Add SuperH boards maintainer to MAINTAINERS file + + Add MS7750SE and MS7722SE's board maintainer to MAINTAINERS file. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit aa9c4f1d22701a92347c1c81f34d12c8ad3a3747 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Thu Nov 29 00:13:04 2007 +0900 + + sh: Add ms7750se support in MAKEALL + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit c7144373427a178332bf9754131c8c34c52c200a +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Tue Nov 27 09:44:53 2007 +0100 + + sh: Add sh3 and sh4 support in MAKEALL + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 130080874a3d28450098481a262c5f7c855e908d +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Nov 25 02:51:17 2007 +0900 + + sh: Add document for SuperH. + + This document is a summary of information concerning SuperH of U-Boot. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 33ecdc2f9d64926e1a6067b28f3a0aefc3b6d23d +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Nov 25 02:39:31 2007 +0900 + + sh: Add marubun's pcmcia driver + + Marubun pcmcia is a chip for PCMCIA used with SuperH. + Of course, this can be used even by other architectures. + When use this driver, came to be able to use CompactFlash + and Ethernet. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit febd86b969b975289ed948f1ac0eb9722da41ced +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Nov 25 02:32:13 2007 +0900 + + sh: Update SuperH SCIF driver + + - Changed volatile unsigned to vu_. + - Changed Makefile for kconfig. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + commit a5f601fd1b1278deae5aa9fc27a232b0d1c1c788 Author: Wolfgang Denk <wd@denx.de> Date: Mon Nov 26 19:18:21 2007 +0100 @@ -1927,6 +2611,56 @@ Date: Mon Sep 24 00:08:37 2007 +0200 synchronizition with mainline +commit eda3e1e6619ad0bee94ae4b16c99d88e77e2af13 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Sep 23 02:42:38 2007 +0900 + + sh: Add support command of ide with sh + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit d91ea45d15cf8e0987456bd211ffbb650824b6f1 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Sep 23 02:38:42 2007 +0900 + + sh: Update Makefile + + Add support MS7722SE01 to Makefile. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 6c0bbdccd379f5c8702af9e0765294c2fb7472a6 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Sep 23 02:31:13 2007 +0900 + + sh: Add support Renesas sh7722 processor and Hitachi MS7722SE01 board + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 047375bfa4c3052fa50a748da7ff89e9dad3b364 +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Sep 23 02:19:24 2007 +0900 + + sh: Update MS7750SE01 platform + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 516ad760db3553766267ada01b7d5d727faa4bbd +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Sep 23 02:17:08 2007 +0900 + + sh: Remove comment out code from include/asm-sh/cpu_sh4.h + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit b02bad128669e567fce87d8df823b06a0144b8db +Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +Date: Sun Sep 23 02:12:30 2007 +0900 + + sh: Update core code of SuperH. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + commit 66dcad3a9a53e0766d90e0084123bd8529522fb0 Author: Wolfgang Denk <wd@denx.de> Date: Thu Sep 20 00:04:14 2007 +0200 @@ -8634,6 +9368,24 @@ Date: Tue May 15 07:55:42 2007 -0700 Fix to compile JSE against 20070514 git of u-boot +commit 69df3c4da0c93017cceb25a366e794570bd0ed98 +Author: Nobuhiro Iwamatsu <iwamatsu@rahute.(none)> +Date: Sun May 13 21:01:03 2007 +0900 + + sh: MS7750SE support. + + This adds support for the Hitachi MS7750SE. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + +commit 0b135cfc2e524dc249b75057b55dd4cc09842e27 +Author: Nobuhiro Iwamatsu <iwamatsu@rahute.(none)> +Date: Sun May 13 20:58:00 2007 +0900 + + sh: First support code of SuperH. + + Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + commit 61936667e86a250ae12fd2dc189d3588f0a59e0b Author: Stefan Roese <sr@denx.de> Date: Fri May 11 12:01:49 2007 +0200 @@ -117,7 +117,7 @@ N: Arun Dharankar E: ADharankar@ATTBI.Com D: threads / scheduler example code -N: Kári Davíđsson +N: K?ri Dav??sson E: kd@flaga.is D: FLAGA DM Support @@ -143,7 +143,7 @@ E: info@elste.org D: Port for the ModNET50 Board, NET+50 CPU Port W: http://www.imms.de -N: Daniel Engström +N: Daniel Engstr?m E: daniel@omicron.se D: x86 port, Support for sc520_cdp board @@ -334,7 +334,7 @@ N: Frank Morauf E: frank.morauf@salzbrenner.com D: Support for Embedded Planet RPX Super Board -N: David Müller +N: David M?ller E: d.mueller@elsoft.ch D: Support for Samsung ARM920T SMDK2410 eval board @@ -499,3 +499,8 @@ N: Alex Zuepke E: azu@sysgo.de D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM W: www.elinos.com + +N: Nobuhiro Iwamatsu +E: iwamatsu@nigauri.org +D: Support for SuperH, MS7750SE01 and MS7722SE01 boards. +W: http://www.nigauri.org/~iwamatsu/ diff --git a/MAINTAINERS b/MAINTAINERS index bf0ebb1758..fa0e9ea2d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -146,7 +146,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> CPCI4052 PPC405GP CPCI405AB PPC405GP CPCI405DT PPC405GP - CPCI440 PPC440GP CPCIISER4 PPC405GP DASA_SIM IOP480 (PPC401) DP405 PPC405EP @@ -159,6 +158,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> PCI405 PPC405GP PLU405 PPC405EP PMC405 PPC405GP + PMC440 PPC440EPx VOH405 PPC405EP VOM405 PPC405EP WUH405 PPC405EP @@ -204,6 +204,10 @@ Murray Jensen <Murray.Jensen@csiro.au> cogent_mpc8260 MPC8260 hymod MPC8260 +Larry Johnson <lrj@acm.org> + + korat PPC440EPx + Brad Kemp <Brad.Kemp@seranoa.com> ppmc8260 MPC8260 @@ -633,7 +637,22 @@ Hayden Fraser <Hayden.Fraser@freescale.com> Haavard Skinnemoen <hskinnemoen@atmel.com> - ATSTK1000 AT32AP7000 + ATSTK1000 AT32AP7xxx + ATSTK1002 AT32AP7000 + ATSTK1003 AT32AP7001 + ATSTK1004 AT32AP7002 + +######################################################################### +# SuperH Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Nobuhiro Iwmaatsu <iwamatsu@nigauri.org> + + MS7750SE SH7750 + MS7722SE SH7722 ######################################################################### # End of MAINTAINERS list # @@ -168,7 +168,6 @@ LIST_4xx=" \ CPCI4052 \ CPCI405AB \ CPCI405DT \ - CPCI440 \ CPCIISER4 \ CRAYL1 \ csb272 \ @@ -191,6 +190,7 @@ LIST_4xx=" \ katmai \ kilauea \ kilauea_nand \ + korat \ luan \ lwmon5 \ makalu \ @@ -208,6 +208,7 @@ LIST_4xx=" \ PIP405 \ PLU405 \ PMC405 \ + PMC440 \ PPChameleonEVB \ rainier \ sbc405 \ @@ -647,6 +648,8 @@ LIST_coldfire=" \ LIST_avr32=" \ atstk1002 \ + atstk1003 \ + atstk1004 \ " ######################################################################### @@ -660,6 +663,23 @@ LIST_blackfin=" \ bf561-ezkit \ " +######################################################################### +## SH Systems +######################################################################### + +LIST_sh4=" \ + ms7750se \ + ms7722se \ +" + +LIST_sh3="" + + +LIST_sh=" \ + ${LIST_sh3} \ + ${LIST_sh4} \ +" + #----------------------------------------------------------------------- #----- for now, just run PPC by default ----- @@ -694,7 +714,9 @@ do mips|mips_el| \ nios|nios2| \ ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ - x86|I486|TSEC) + x86|I486|TSEC| \ + sh|sh4|sh3 \ + ) for target in `eval echo '$LIST_'${arg}` do build_target ${target} @@ -152,6 +152,9 @@ endif ifeq ($(ARCH),avr32) CROSS_COMPILE = avr32-linux- endif +ifeq ($(ARCH),sh) +CROSS_COMPILE = sh4-linux- +endif endif endif @@ -1160,9 +1163,6 @@ CPCI405AB_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd @echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk -CPCI440_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci440 esd - CPCIISER4_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd @@ -1231,6 +1231,9 @@ haleakala_nand_config: unconfig @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk +korat_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx korat + luan_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc @@ -1283,6 +1286,9 @@ PLU405_config: unconfig PMC405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd +PMC440_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd + PPChameleonEVB_config \ PPChameleonEVB_BA_25_config \ PPChameleonEVB_ME_25_config \ @@ -1928,7 +1934,7 @@ TQM834x_config: unconfig ######################################################################### MPC8540ADS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale MPC8540EVAL_config \ MPC8540EVAL_33_config \ @@ -1952,7 +1958,7 @@ MPC8540EVAL_66_slave_config: unconfig @$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval MPC8560ADS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads freescale MPC8541CDS_legacy_config \ MPC8541CDS_config: unconfig @@ -1962,7 +1968,7 @@ MPC8541CDS_config: unconfig echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ echo "... legacy" ; \ fi - @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds + @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds freescale MPC8544DS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale @@ -1975,7 +1981,7 @@ MPC8548CDS_config: unconfig echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ echo "... legacy" ; \ fi - @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds + @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds freescale MPC8555CDS_legacy_config \ MPC8555CDS_config: unconfig @@ -1985,10 +1991,10 @@ MPC8555CDS_config: unconfig echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ echo "... legacy" ; \ fi - @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds + @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds freescale MPC8568MDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 @@ -2673,7 +2679,30 @@ bf561-ezkit_config: unconfig ######################################################################### atstk1002_config : unconfig - @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000 + @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x + +atstk1003_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x + +atstk1004_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x + +######################################################################### +######################################################################### +######################################################################### + +######################################################################### +## sh4 (Renesas SuperH) +######################################################################### +ms7750se_config: unconfig + @ >include/config.h + @echo "#define CONFIG_MS7750SE 1" >> include/config.h + @./mkconfig -a $(@:_config=) sh sh4 ms7750se + +ms7722se_config : unconfig + @ >include/config.h + @echo "#define CONFIG_MS7722SE 1" >> include/config.h + @./mkconfig -a $(@:_config=) sh sh4 ms7722se ######################################################################### ######################################################################### @@ -235,9 +235,7 @@ The following options need to be configured: - Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS. - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined) - Define exactly one of - CONFIG_ATSTK1002 - + Define exactly one, e.g. CONFIG_ATSTK1002 - CPU Module Type: (if CONFIG_COGENT is defined) Define exactly one of diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 39a3ef1695..25c9a22fea 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -25,6 +25,8 @@ #include <common.h> #include <ppc4xx.h> #include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/gpio.h> @@ -533,3 +535,24 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index c7da5216dc..ff6ae669ef 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -20,57 +20,9 @@ */ #include <ppc_asm.tmpl> +#include <asm-ppc/mmu.h> #include <config.h> -/* General */ -#define TLB_VALID 0x00000200 -#define _256M 0x10000000 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - /************************************************************************** * TLB TABLE * diff --git a/board/amcc/sequoia/sdram.h b/board/amcc/sequoia/sdram.h index 7f847aa2ad..6a7bf01efb 100644 --- a/board/amcc/sequoia/sdram.h +++ b/board/amcc/sequoia/sdram.h @@ -395,8 +395,8 @@ #define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) #define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) #define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) #define DDR0_27 0x1B #define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index f81f07146d..37b4f31b90 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -48,31 +48,31 @@ int board_early_init_f(void) * Setup the GPIO pins *-------------------------------------------------------------------*/ /* test-only: take GPIO init from pcs440ep ???? in config file */ - out32(GPIO0_OR, 0x00000000); - out32(GPIO0_TCR, 0x0000000f); - out32(GPIO0_OSRL, 0x50015400); - out32(GPIO0_OSRH, 0x550050aa); - out32(GPIO0_TSRL, 0x50015400); - out32(GPIO0_TSRH, 0x55005000); - out32(GPIO0_ISR1L, 0x50000000); - out32(GPIO0_ISR1H, 0x00000000); - out32(GPIO0_ISR2L, 0x00000000); - out32(GPIO0_ISR2H, 0x00000100); - out32(GPIO0_ISR3L, 0x00000000); - out32(GPIO0_ISR3H, 0x00000000); - - out32(GPIO1_OR, 0x00000000); - out32(GPIO1_TCR, 0xc2000000); - out32(GPIO1_OSRL, 0x5c280000); - out32(GPIO1_OSRH, 0x00000000); - out32(GPIO1_TSRL, 0x0c000000); - out32(GPIO1_TSRH, 0x00000000); - out32(GPIO1_ISR1L, 0x00005550); - out32(GPIO1_ISR1H, 0x00000000); - out32(GPIO1_ISR2L, 0x00050000); - out32(GPIO1_ISR2H, 0x00000000); - out32(GPIO1_ISR3L, 0x01400000); - out32(GPIO1_ISR3H, 0x00000000); + out_be32((u32 *) GPIO0_OR, 0x00000000); + out_be32((u32 *) GPIO0_TCR, 0x0000000f); + out_be32((u32 *) GPIO0_OSRL, 0x50015400); + out_be32((u32 *) GPIO0_OSRH, 0x550050aa); + out_be32((u32 *) GPIO0_TSRL, 0x50015400); + out_be32((u32 *) GPIO0_TSRH, 0x55005000); + out_be32((u32 *) GPIO0_ISR1L, 0x50000000); + out_be32((u32 *) GPIO0_ISR1H, 0x00000000); + out_be32((u32 *) GPIO0_ISR2L, 0x00000000); + out_be32((u32 *) GPIO0_ISR2H, 0x00000100); + out_be32((u32 *) GPIO0_ISR3L, 0x00000000); + out_be32((u32 *) GPIO0_ISR3H, 0x00000000); + + out_be32((u32 *) GPIO1_OR, 0x00000000); + out_be32((u32 *) GPIO1_TCR, 0xc2000000); + out_be32((u32 *) GPIO1_OSRL, 0x5c280000); + out_be32((u32 *) GPIO1_OSRH, 0x00000000); + out_be32((u32 *) GPIO1_TSRL, 0x0c000000); + out_be32((u32 *) GPIO1_TSRH, 0x00000000); + out_be32((u32 *) GPIO1_ISR1L, 0x00005550); + out_be32((u32 *) GPIO1_ISR1H, 0x00000000); + out_be32((u32 *) GPIO1_ISR2L, 0x00050000); + out_be32((u32 *) GPIO1_ISR2H, 0x00000000); + out_be32((u32 *) GPIO1_ISR3L, 0x01400000); + out_be32((u32 *) GPIO1_ISR3H, 0x00000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -102,16 +102,16 @@ int board_early_init_f(void) mtdcr(uic2sr, 0xffffffff); /* clear all */ /* 50MHz tmrclk */ - *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00); /* clear write protects */ - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; + out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00); /* enable Ethernet */ - *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00; + out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00); /* enable USB device */ - *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20; + out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20); /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 196171ce5a..4116838b28 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -24,6 +24,7 @@ * MA 02111-1307 USA */ +#include "asm/io.h" #include "lcd.h" @@ -45,11 +46,10 @@ void lcd_setup(int lcd, int config) */ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ udelay(10); /* wait 10us */ - if (config == 1) { + if (config == 1) out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ - } else { + else out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ - } udelay(10); /* wait 10us */ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ } else { @@ -58,11 +58,10 @@ void lcd_setup(int lcd, int config) */ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ udelay(10); /* wait 10us */ - if (config == 1) { + if (config == 1) out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ - } else { + else out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ - } udelay(10); /* wait 10us */ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ } @@ -104,12 +103,10 @@ void lcd_bmp(uchar *logo_bmp) printf("Error: malloc in gunzip failed!\n"); return; } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) { + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) return; - } - if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + if (len == CFG_VIDEO_LOGO_MAX_SIZE) printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); - } /* * Check for bmp mark 'BM' @@ -152,9 +149,8 @@ void lcd_bmp(uchar *logo_bmp) break; default: printf("LCD: Unknown bpp (%d) im image!\n", bpp); - if ((dst != NULL) && (dst != (uchar *)logo_bmp)) { + if ((dst != NULL) && (dst != (uchar *)logo_bmp)) free(dst); - } return; } printf(" (%d*%d, %dbpp)\n", width, height, bpp); @@ -212,9 +208,8 @@ void lcd_bmp(uchar *logo_bmp) } } - if ((dst != NULL) && (dst != (uchar *)logo_bmp)) { + if ((dst != NULL) && (dst != (uchar *)logo_bmp)) free(dst); - } } @@ -229,10 +224,10 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Detect epson */ - lcd_reg[0] = 0x00; - lcd_reg[1] = 0x00; + out_8(&lcd_reg[0], 0x00); + out_8(&lcd_reg[1], 0x00); - if (lcd_reg[0] == 0x1c) { + if (in_8(&lcd_reg[0]) == 0x1c) { /* * Big epson detected */ @@ -241,7 +236,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, palette_value = 0x1e4; lcd_depth = 16; puts("LCD: S1D13806"); - } else if (lcd_reg[1] == 0x1c) { + } else if (in_8(&lcd_reg[1]) == 0x1c) { /* * Big epson detected (with register swap bug) */ @@ -250,7 +245,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, palette_value = 0x1e5; lcd_depth = 16; puts("LCD: S1D13806S"); - } else if (lcd_reg[0] == 0x18) { + } else if (in_8(&lcd_reg[0]) == 0x18) { /* * Small epson detected (704) */ @@ -259,7 +254,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, palette_value = 0x17; lcd_depth = 8; puts("LCD: S1D13704"); - } else if (lcd_reg[0x10000] == 0x24) { + } else if (in_8(&lcd_reg[0x10000]) == 0x24) { /* * Small epson detected (705) */ @@ -277,7 +272,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Setup lcd controller regs */ - for (i = 0; i<reg_count; i++) { + for (i = 0; i < reg_count; i++) { s1dReg = regs[i].Index; if (reg_byte_swap) { if ((s1dReg & 0x0001) == 0) diff --git a/board/esd/cpci440/cpci440.c b/board/esd/cpci440/cpci440.c deleted file mode 100644 index caa6d5591f..0000000000 --- a/board/esd/cpci440/cpci440.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2002 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> -#include <asm/processor.h> - - -extern void lxt971_no_sleep(void); - - -long int fixed_sdram( void ); - -int board_early_init_f (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr( ebccfga, xbcfg ); - reg = mfdcr( ebccfgd ); - mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */ - - mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */ - mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */ - /* test-only: other regs still missing... */ - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr( uic0sr, 0xffffffff ); /* clear all */ - mtdcr( uic0er, 0x00000000 ); /* disable all */ - mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */ - mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */ - mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */ - mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */ - mtdcr( uic0sr, 0xffffffff ); /* clear all */ - - mtdcr( uic1sr, 0xffffffff ); /* clear all */ - mtdcr( uic1er, 0x00000000 ); /* disable all */ - mtdcr( uic1cr, 0x00000000 ); /* all non-critical */ - mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */ - mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */ - mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */ - mtdcr( uic1sr, 0xffffffff ); /* clear all */ - - return 0; -} - - -int checkboard (void) -{ - sys_info_t sysinfo; - get_sys_info(&sysinfo); - - printf("Board: esd CPCI-440\n"); - printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000); - printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000); - printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000); - printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000); - printf("\tEBC: %lu MHz\n", sysinfo.freqEBC/1000000); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return (0); -} - - -long int initdram (int board_type) -{ - long dram_size = 0; - - dram_size = fixed_sdram(); - return dram_size; -} - - -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 64 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram( void ) -{ - uint reg; - -#if 1 /* test-only */ - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */ - mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */ - mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */ - mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */ - mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/ - mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */ - udelay( 400 ); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */ - for(;;) - { - mfsdram( mem_mcsts, reg ); - if( reg & 0x80000000 ) - break; - } - - return( 64 * 1024 * 1024 ); /* 64 MB */ -#else - return( 32 * 1024 * 1024 ); /* 64 MB */ -#endif -} diff --git a/board/esd/cpci440/init.S b/board/esd/cpci440/init.S deleted file mode 100644 index 82f37fd996..0000000000 --- a/board/esd/cpci440/init.S +++ /dev/null @@ -1,94 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include <ppc_asm.tmpl> -#include <config.h> - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X ) - tlbtab_end diff --git a/board/esd/cpci440/strataflash.c b/board/esd/cpci440/strataflash.c deleted file mode 100644 index 2f055c20d5..0000000000 --- a/board/esd/cpci440/strataflash.c +++ /dev/null @@ -1,755 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index f026a7ac3b..57762b54ee 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -109,8 +109,8 @@ int misc_init_f (void) int misc_init_r (void) { - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); unsigned char *dst; ulong len = sizeof(fpgadata); int status; @@ -184,16 +184,28 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* + * Set NAND-FLASH GPIO signals to default + */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE); + + /* + * Setup EEPROM write protection + */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP); + + /* * Enable interrupts in exar duart mcr[3] */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; + out_8(duart0_mcr, 0x08); + out_8(duart1_mcr, 0x08); return (0); } @@ -259,3 +271,74 @@ void reset_phy(void) lxt971_no_sleep(); #endif } + + +#if defined(CFG_EEPROM_WREN) +/* Input: <dev_addr> I2C address of EEPROM device to enable. + * <state> -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if <state> was -1. + */ +int eeprom_write_enable (unsigned dev_addr, int state) +{ + if (CFG_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO0. */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO0. */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP)); + break; + } + } + return state; +} + +int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + if (state < 0) { + puts ("Query of write access state failed.\n"); + } else { + printf ("Write access for device 0x%0x is %sabled.\n", + CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + } + if (state < 0) { + puts ("Setup of write access state failed.\n"); + } + } + + return state; +} + +U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL); +#endif /* #if defined(CFG_EEPROM_WREN) */ diff --git a/board/esd/cpci440/Makefile b/board/esd/pmc440/Makefile index d13d31c974..4dd9c386cd 100644 --- a/board/esd/cpci440/Makefile +++ b/board/esd/pmc440/Makefile @@ -22,13 +22,12 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o strataflash.o ../common/misc.o +COBJS = $(BOARD).o cmd_pmc440.o sdram.o fpga.o \ + ../common/cmd_loadpci.o + SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) @@ -36,7 +35,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c new file mode 100644 index 0000000000..d588d8ca9b --- /dev/null +++ b/board/esd/pmc440/cmd_pmc440.c @@ -0,0 +1,558 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/processor.h> + +#include "pmc440.h" + +int is_monarch(void); +int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); +int eeprom_write_enable(unsigned dev_addr, int state); + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_BSP) + +static int got_fifoirq; +static int got_hcirq; + +int fpga_interrupt(u32 arg) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg; + int rc = -1; /* not for us */ + u32 status = FPGA_IN32(&fpga->status); + + /* check for interrupt from fifo module */ + if (status & STATUS_FIFO_ISF) { + /* disable this int source */ + FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE); + rc = 0; + got_fifoirq = 1; /* trigger backend */ + } + + if (status & STATUS_HOST_ISF) { + FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE); + rc = 0; + got_hcirq = 1; + } + + return rc; +} + + +int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + + got_hcirq = 0; + + FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE); + FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE); + + irq_install_handler(IRQ0_FPGA, + (interrupt_handler_t *)fpga_interrupt, + fpga); + + FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE); + + while (!got_hcirq) { + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + break; + } + } + if (got_hcirq) + printf("Got interrupt!\n"); + + FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE); + irq_free_handler(IRQ0_FPGA); + return 0; +} +U_BOOT_CMD( + waithci, 1, 1, do_waithci, + "waithci - Wait for host control interrupt\n", + NULL + ); + + +void dump_fifo(pmc440_fpga_t *fpga, int f, int *n) +{ + u32 ctrl; + + while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) { + printf("%5d %d %3d %08x", + (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL), + FPGA_IN32(&fpga->fifo[f].data)); + if (ctrl & FIFO_OVERFLOW) { + printf(" OVERFLOW\n"); + FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW); + } else + printf("\n"); + } +} + + +int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + int i; + int n = 0; + u32 ctrl, data, f; + char str[] = "\\|/-"; + int abort = 0; + int count = 0; + int count2 = 0; + + switch (argc) { + case 1: + /* print all fifos status information */ + printf("fifo level status\n"); + printf("______________________________\n"); + for (i=0; i<FIFO_COUNT; i++) { + ctrl = FPGA_IN32(&fpga->fifo[i].ctrl); + printf(" %d %3d %s%s%s %s\n", + i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL), + ctrl & FIFO_FULL ? "FULL " : "", + ctrl & FIFO_EMPTY ? "EMPTY " : "", + ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY", + ctrl & FIFO_OVERFLOW ? "OVERFLOW" : ""); + } + break; + + case 2: + /* completely read out fifo 'n' */ + if (!strcmp(argv[1],"read")) { + printf(" # fifo level data\n"); + printf("______________________________\n"); + + for (i=0; i<FIFO_COUNT; i++) + dump_fifo(fpga, i, &n); + + } else if (!strcmp(argv[1],"wait")) { + got_fifoirq = 0; + + irq_install_handler(IRQ0_FPGA, + (interrupt_handler_t *)fpga_interrupt, + fpga); + + printf(" # fifo level data\n"); + printf("______________________________\n"); + + /* enable all fifo interrupts */ + FPGA_OUT32(&fpga->hostctrl, + HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG); + for (i=0; i<FIFO_COUNT; i++) { + /* enable interrupts from all fifos */ + FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE); + } + + while (1) { + /* wait loop */ + while (!got_fifoirq) { + count++; + if (!(count % 100)) { + count2++; + putc(0x08); /* backspace */ + putc(str[count2 % 4]); + } + + /* Abort if ctrl-c was pressed */ + if ((abort = ctrlc())) { + puts("\nAbort\n"); + break; + } + udelay(1000); + } + if (abort) + break; + + /* simple fifo backend */ + if (got_fifoirq) { + for (i=0; i<FIFO_COUNT; i++) + dump_fifo(fpga, i, &n); + + got_fifoirq = 0; + /* unmask global fifo irq */ + FPGA_OUT32(&fpga->hostctrl, + HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG); + } + } + + /* disable all fifo interrupts */ + FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE); + for (i=0; i<FIFO_COUNT; i++) + FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE); + + irq_free_handler(IRQ0_FPGA); + + } else { + printf("Usage:\nfifo %s\n", cmdtp->help); + return 1; + } + break; + + case 4: + case 5: + if (!strcmp(argv[1],"write")) { + /* get fifo number or fifo address */ + f = simple_strtoul(argv[2], NULL, 16); + + /* data paramter */ + data = simple_strtoul(argv[3], NULL, 16); + + /* get optional count parameter */ + n = 1; + if (argc >= 5) + n = (int)simple_strtoul(argv[4], NULL, 10); + + if (f < FIFO_COUNT) { + printf("writing %d x %08x to fifo %d\n", + n, data, f); + for (i=0; i<n; i++) + FPGA_OUT32(&fpga->fifo[f].data, data); + } else { + printf("writing %d x %08x to fifo port at address %08x\n", + n, data, f); + for (i=0; i<n; i++) + out32(f, data); + } + } else { + printf("Usage:\nfifo %s\n", cmdtp->help); + return 1; + } + break; + + default: + printf("Usage:\nfifo %s\n", cmdtp->help); + return 1; + } + return 0; +} +U_BOOT_CMD( + fifo, 5, 1, do_fifo, + "fifo - Fifo module operations\n", + "wait\nfifo read\n" + "fifo write fifo(0..3) data [cnt=1]\n" + "fifo write address(>=4) data [cnt=1]\n" + " - without arguments: print all fifo's status\n" + " - with 'wait' argument: interrupt driven read from all fifos\n" + " - with 'read' argument: read current contents from all fifos\n" + " - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n" + ); + + +int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong sdsdp[5]; + ulong delay; + int count=16; + + if (argc < 2) { + printf("Usage:\nsbe %s\n", cmdtp->help); + return -1; + } + + if (argc > 1) { + if (!strcmp(argv[1], "400")) { + /* PLB=133MHz, PLB/PCI=4 */ + printf("Bootstrapping for 400MHz\n"); + sdsdp[0]=0x8678624e; + sdsdp[1]=0x0947a030; + sdsdp[2]=0x40082350; + sdsdp[3]=0x0d050000; + } else if (!strcmp(argv[1], "533")) { + /* PLB=133MHz, PLB/PCI=3 */ + printf("Bootstrapping for 533MHz\n"); + sdsdp[0]=0x87788252; + sdsdp[1]=0x095fa030; + sdsdp[2]=0x40082350; + sdsdp[3]=0x0d050000; + } else if (!strcmp(argv[1], "667")) { + /* PLB=133MHz, PLB/PCI=4 */ + printf("Bootstrapping for 667MHz\n"); + sdsdp[0]=0x8778a256; + sdsdp[1]=0x0947a030; + sdsdp[2]=0x40082350; + sdsdp[3]=0x0d050000; + } else if (!strcmp(argv[1], "test")) { + /* TODO: this will replace the 667 MHz config above. + * But it needs some more testing on a real 667 MHz CPU. + */ + printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n"); + sdsdp[0]=0x8778a256; + sdsdp[1]=0x095fa030; + sdsdp[2]=0x40082350; + sdsdp[3]=0x0d050000; + } else { + printf("Usage:\nsbe %s\n", cmdtp->help); + return -1; + } + } + + if (argc > 2) { + sdsdp[4] = 0; + if (argv[2][0]=='1') + sdsdp[4]=0x19750100; + else if (argv[2][0]=='0') + sdsdp[4]=0x19750000; + if (sdsdp[4]) + count += 4; + } + + if (argc > 3) { + delay = simple_strtoul(argv[3], NULL, 10); + if (delay > 20) + delay = 20; + sdsdp[4] |= delay; + } + + printf("Writing boot EEPROM ...\n"); + if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR, + 0, (uchar*)sdsdp, count) != 0) + printf("bootstrap_eeprom_write failed\n"); + else + printf("done (dump via 'i2c md 52 0.1 14')\n"); + + return 0; +} +U_BOOT_CMD( + sbe, 4, 0, do_setup_bootstrap_eeprom, + "sbe - setup bootstrap eeprom\n", + "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]" + ); + + +#if defined(CONFIG_PRAM) +#include <environment.h> +extern env_t *env_ptr; + +int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u32 memsize; + u32 pram, env_base; + char *v; + u32 param; + ulong *lptr; + + memsize = gd->bd->bi_memsize; + + v = getenv("pram"); + if (v) + pram = simple_strtoul(v, NULL, 10); + else { + printf("Error: pram undefined. Please define pram in KiB\n"); + return 1; + } + + param = memsize - (pram << 10); + printf("PARAM: @%08x\n", param); + + memset((void*)param, 0, (pram << 10)); + env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1)); + memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE); + + lptr = (ulong*)memsize; + *(--lptr) = CFG_ENV_SIZE; + *(--lptr) = memsize - env_base; + *(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08); + *(--lptr) = 0; + + /* make sure data can be accessed through PCI */ + flush_dcache_range(param, param + (pram << 10) - 1); + return 0; +} +U_BOOT_CMD( + painit, 1, 1, do_painit, + "painit - prepare PciAccess system\n", + NULL + ); +#endif /* CONFIG_PRAM */ + + +int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc > 1) { + if (argv[1][0] == '0') { + /* assert */ + printf("self-reset# asserted\n"); + out_be32((void*)GPIO0_TCR, + in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST); + } else { + /* deassert */ + printf("self-reset# deasserted\n"); + out_be32((void*)GPIO0_TCR, + in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST); + } + } else { + printf("self-reset# is %s\n", + in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ? + "active" : "inactive"); + } + + return 0; +} +U_BOOT_CMD( + selfreset, 2, 1, do_selfreset, + "selfreset- assert self-reset# signal\n", + NULL + ); + + +int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + + /* requiers bootet FPGA and PLD_IOEN_N active */ + if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) { + printf("Error: resetout requires a bootet FPGA\n"); + return -1; + } + + if (argc > 1) { + if (argv[1][0] == '0') { + /* assert */ + printf("PMC-RESETOUT# asserted\n"); + FPGA_OUT32(&fpga->hostctrl, + HOSTCTRL_PMCRSTOUT_GATE); + } else { + /* deassert */ + printf("PMC-RESETOUT# deasserted\n"); + FPGA_OUT32(&fpga->hostctrl, + HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG); + } + } else { + printf("PMC-RESETOUT# is %s\n", + FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ? + "inactive" : "active"); + } + + return 0; +} +U_BOOT_CMD( + resetout, 2, 1, do_resetout, + "resetout - assert PMC-RESETOUT# signal\n", + NULL + ); + + +int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (is_monarch()) { + printf("This command is only supported in non-monarch mode\n"); + return -1; + } + + if (argc > 1) { + if (argv[1][0] == '0') { + /* assert */ + printf("inta# asserted\n"); + out_be32((void*)GPIO1_TCR, + in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE); + } else { + /* deassert */ + printf("inta# deasserted\n"); + out_be32((void*)GPIO1_TCR, + in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE); + } + } else { + printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive"); + } + return 0; +} +U_BOOT_CMD( + inta, 2, 1, do_inta, + "inta - Assert/Deassert or query INTA# state in non-monarch mode\n", + NULL + ); + + +/* test-only */ +int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong pciaddr; + + if (argc > 1) { + pciaddr = simple_strtoul(argv[1], NULL, 16); + + pciaddr &= 0xf0000000; + + /* map PCI address at 0xc0000000 in PLB space */ + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */ + out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */ + } else { + printf("Usage:\npmm %s\n", cmdtp->help); + } + return 0; +} +U_BOOT_CMD( + pmm, 2, 1, do_pmm, + "pmm - Setup pmm[1] registers\n", + "<pciaddr> (pciaddr will be aligned to 256MB)\n" + ); + +#if defined(CFG_EEPROM_WREN) +int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1); + if (state < 0) { + puts("Query of write access state failed.\n"); + } else { + printf("Write access for device 0x%0x is %sabled.\n", + CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1); + } + if (state < 0) { + puts("Setup of write access state failed.\n"); + } + } + + return state; +} +U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL); +#endif /* #if defined(CFG_EEPROM_WREN) */ + +#endif /* CONFIG_CMD_BSP */ diff --git a/board/esd/cpci440/config.mk b/board/esd/pmc440/config.mk index 8e5f63fe48..e62b8d30e4 100644 --- a/board/esd/cpci440/config.mk +++ b/board/esd/pmc440/config.mk @@ -20,18 +20,14 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - # -# esd ADCIOP boards +# AMCC 440EPx Reference Platform (Sequoia) board # -#TEXT_BASE = 0xFFFE0000 +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x01fc0000 +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c new file mode 100644 index 0000000000..a35f42bd51 --- /dev/null +++ b/board/esd/pmc440/fpga.c @@ -0,0 +1,461 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <spartan2.h> +#include <spartan3.h> +#include <command.h> +#include "fpga.h" +#include "pmc440.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_FPGA) + +#define USE_SP_CODE + +#ifdef USE_SP_CODE +Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_init_fn, + NULL, /* err */ + fpga_done_fn, + fpga_clk_fn, + fpga_cs_fn, + fpga_wr_fn, + NULL, /* rdata */ + fpga_wdata_fn, + fpga_busy_fn, + fpga_abort_fn, + fpga_post_config_fn, +}; +#else +Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_clk_fn, + fpga_init_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_post_config_fn, +}; +#endif + +Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = { + ngcc_fpga_pre_config_fn, + ngcc_fpga_pgm_fn, + ngcc_fpga_clk_fn, + ngcc_fpga_init_fn, + ngcc_fpga_done_fn, + ngcc_fpga_wr_fn, + ngcc_fpga_post_config_fn +}; + +Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + XILINX_XC3S1200E_DESC( +#ifdef USE_SP_CODE + slave_parallel, +#else + slave_serial, +#endif + (void *)&pmc440_fpga_fns, + 0), + XILINX_XC2S200_DESC( + slave_serial, + (void *)&ngcc_fpga_fns, + 0) +}; + + +/* + * Set the active-low FPGA reset signal. + */ +void fpga_reset(int assert) +{ + debug("%s:%d: RESET ", __FUNCTION__, __LINE__); + if (assert) { + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA); + debug("asserted\n"); + } else { + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA); + debug("deasserted\n"); + } +} + + +/* + * Initialize the SelectMap interface. We assume that the mode and the + * initial state of all of the port pins have already been set! + */ +void fpga_serialslave_init(void) +{ + debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__, + __LINE__); + fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ +} + + +/* + * Set the FPGA's active-low SelectMap program line to the specified level + */ +int fpga_pgm_fn(int assert, int flush, int cookie) +{ + debug("%s:%d: FPGA PROGRAM ", + __FUNCTION__, __LINE__); + + if (assert) { + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG); + debug("asserted\n"); + } else { + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG); + debug("deasserted\n"); + } + return assert; +} + + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int fpga_init_fn(int cookie) +{ + if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT) + return 0; + else + return 1; +} + +#ifdef USE_SP_CODE +int fpga_abort_fn(int cookie) +{ + return 0; +} + + +int fpga_cs_fn(int assert_cs, int flush, int cookie) +{ + return assert_cs; +} + + +int fpga_busy_fn(int cookie) +{ + return 1; +} +#endif + + +/* + * Test the state of the active-high FPGA DONE pin + */ +int fpga_done_fn(int cookie) +{ + if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE) + return 1; + else + return 0; +} + + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +int fpga_pre_config_fn(int cookie) +{ + debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); + fpga_reset(TRUE); + + /* release init# */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT); + /* disable PLD IOs */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N); + return 0; +} + + +/* + * FPGA post configuration function. Blip the FPGA reset line and then see if + * the FPGA appears to be running. + */ +int fpga_post_config_fn(int cookie) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + int rc=0; + char *s; + + debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); + + /* enable PLD0..7 pins */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N); + + fpga_reset(TRUE); + udelay (100); + fpga_reset(FALSE); + udelay (100); + + FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK); + + /* NGCC only: enable ledlink */ + if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) + FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); + + return rc; +} + + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + if (assert_clk) + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK); + else + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK); + + return assert_clk; +} + + +int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + if (assert_write) + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA); + else + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA); + + return assert_write; +} + +#ifdef USE_SP_CODE +int fpga_wdata_fn(uchar data, int flush, int cookie) +{ + uchar val = data; + ulong or = in_be32((void*)GPIO1_OR); + int i = 7; + do { + /* Write data */ + if (val & 0x80) + or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA; + else + or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA); + + out_be32((void*)GPIO1_OR, or); + + /* Assert the clock */ + or |= GPIO1_FPGA_CLK; + out_be32((void*)GPIO1_OR, or); + val <<= 1; + i --; + } while (i > 0); + + /* Write last data bit (the 8th clock comes from the sp_load() code */ + if (val & 0x80) + or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA; + else + or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA); + + out_be32((void*)GPIO1_OR, or); + + return 0; +} +#endif + +#define NGCC_FPGA_PRG CLOCK_EN +#define NGCC_FPGA_DATA RESET_OUT +#define NGCC_FPGA_DONE CLOCK_IN +#define NGCC_FPGA_INIT IRIGB_R_IN +#define NGCC_FPGA_CLK CLOCK_OUT + +void ngcc_fpga_serialslave_init(void) +{ + debug("%s:%d: Initialize serial slave interface\n", + __FUNCTION__, __LINE__); + + /* make sure program pin is inactive */ + ngcc_fpga_pgm_fn (FALSE, FALSE, 0); +} + +/* + * Set the active-low FPGA reset signal. + */ +void ngcc_fpga_reset(int assert) +{ + debug("%s:%d: RESET ", __FUNCTION__, __LINE__); + + if (assert) { + FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N); + debug("asserted\n"); + } else { + FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N); + debug("deasserted\n"); + } +} + + +/* + * Set the FPGA's active-low SelectMap program line to the specified level + */ +int ngcc_fpga_pgm_fn(int assert, int flush, int cookie) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + + debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); + + if (assert) { + FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG); + debug("asserted\n"); + } else { + FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG); + debug("deasserted\n"); + } + + return assert; +} + + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int ngcc_fpga_init_fn(int cookie) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + + debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__); + if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) { + debug("high\n"); + return 0; + } else { + debug("low\n"); + return 1; + } +} + + +/* + * Test the state of the active-high FPGA DONE pin + */ +int ngcc_fpga_done_fn(int cookie) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + + debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__); + if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) { + debug("DONE high\n"); + return 1; + } else { + debug("low\n"); + return 0; + } +} + + +/* + * FPGA pre-configuration function. + */ +int ngcc_fpga_pre_config_fn(int cookie) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); + + ngcc_fpga_reset(TRUE); + FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00); + + ngcc_fpga_reset(TRUE); + return 0; +} + + +/* + * FPGA post configuration function. Blip the FPGA reset line and then see if + * the FPGA appears to be running. + */ +int ngcc_fpga_post_config_fn(int cookie) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + + debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__); + + udelay (100); + ngcc_fpga_reset(FALSE); + + FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); + + return 0; +} + + +int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + + if (assert_clk) + FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK); + else + FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK); + + return assert_clk; +} + + +int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie) +{ + pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; + + if (assert_write) + FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA); + else + FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA); + + return assert_write; +} + + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +int pmc440_init_fpga(void) +{ + char *s; + + debug("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", + __FUNCTION__, __LINE__, gd->reloc_off); + fpga_init(gd->reloc_off); + + fpga_serialslave_init (); + debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__); + fpga_add (fpga_xilinx, &fpga[0]); + + /* NGCC only */ + if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) { + ngcc_fpga_serialslave_init (); + debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__); + fpga_add (fpga_xilinx, &fpga[1]); + } + + return 0; +} +#endif /* CONFIG_FPGA */ diff --git a/board/esd/pmc440/fpga.h b/board/esd/pmc440/fpga.h new file mode 100644 index 0000000000..d61a3cfadd --- /dev/null +++ b/board/esd/pmc440/fpga.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +extern int pmc440_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_init_fn(int cookie); +extern int fpga_err_fn(int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_cs_fn(int assert_cs, int flush, int cookie); +extern int fpga_wr_fn(int assert_write, int flush, int cookie); +extern int fpga_wdata_fn (uchar data, int flush, int cookie); +extern int fpga_read_data_fn(unsigned char *data, int cookie); +extern int fpga_write_data_fn(unsigned char data, int flush, int cookie); +extern int fpga_busy_fn(int cookie); +extern int fpga_abort_fn(int cookie ); +extern int fpga_pre_config_fn(int cookie ); +extern int fpga_post_config_fn(int cookie ); + +extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int ngcc_fpga_init_fn(int cookie); +extern int ngcc_fpga_done_fn(int cookie); +extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie); +extern int ngcc_fpga_pre_config_fn(int cookie ); +extern int ngcc_fpga_post_config_fn(int cookie ); diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S new file mode 100644 index 0000000000..148af71bb5 --- /dev/null +++ b/board/esd/pmc440/init.S @@ -0,0 +1,122 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <asm-ppc/mmu.h> +#include <config.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ +#ifndef CONFIG_NAND_SPL + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) +#else + tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) +#endif + + /* TLB-entry for DDR SDRAM (Up to 2GB) */ +#ifdef CONFIG_4xx_DCACHE + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) +#else + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) +#endif + + /* TLB-entry for PCI Memory */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entries for EBC */ + /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral + * tlb entry. + * This dummy entry is only for convinience in order not to modify the + * amount of entries. Currently OS/9 relies on this :-) + */ + tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for NAND */ + tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for Internal Registers & OCM */ + tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /*TLB-entry PCI registers*/ + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for peripherals */ + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* TLB-entry PCI IO space */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* TODO: what about high IO space */ + tlbtab_end + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /* + * For NAND booting the first TLB has to be reconfigured to full size + * and with caching disabled after running from RAM! + */ +#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) +#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) + + .globl reconfig_tlb0 +reconfig_tlb0: + sync + isync + addi r4,r0,0x0000 /* TLB entry #0 */ + lis r5,TLB00@h + ori r5,r5,TLB00@l + tlbwe r5,r4,0x0000 /* Save it out */ + lis r5,TLB01@h + ori r5,r5,TLB01@l + tlbwe r5,r4,0x0001 /* Save it out */ + lis r5,TLB02@h + ori r5,r5,TLB02@l + tlbwe r5,r4,0x0002 /* Save it out */ + sync + isync + blr +#endif diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c new file mode 100644 index 0000000000..edf3a140b5 --- /dev/null +++ b/board/esd/pmc440/pmc440.c @@ -0,0 +1,898 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. + * Based on board/amcc/sequoia/sequoia.c + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <ppc440.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <command.h> +#include <i2c.h> +#ifdef CONFIG_RESET_PHY_R +#include <miiphy.h> +#endif +#include <serial.h> +#include "fpga.h" +#include "pmc440.h" + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +ulong flash_get_size(ulong base, int banknum); +int pci_is_66mhz(void); +int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); + + +struct serial_device *default_serial_console(void) +{ + uchar buf[4]; + ulong delay; + int i; + ulong val; + + /* + * Use default console on P4 when strapping jumper + * is installed (bootstrap option != 'H'). + */ + mfsdr(SDR_PINSTP, val); + if (((val & 0xf0000000) >> 29) != 7) + return &serial1_device; + + ulong scratchreg = in_be32((void*)GPIO0_ISR3L); + if (!(scratchreg & 0x80)) { + /* mark scratchreg valid */ + scratchreg = (scratchreg & 0xffffff00) | 0x80; + + i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4); + if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { + scratchreg |= buf[2]; + + /* bringup delay for console */ + for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) { + udelay(1000); + } + } else + scratchreg |= 0x01; + out_be32((void*)GPIO0_ISR3L, scratchreg); + } + + if (scratchreg & 0x01) + return &serial1_device; + else + return &serial0_device; +} + +int board_early_init_f(void) +{ + u32 sdr0_cust0; + u32 sdr0_pfc1, sdr0_pfc2; + u32 reg; + + /* general EBC configuration (disable EBC timeouts) */ + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, 0xf8400000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file + *-------------------------------------------------------------------*/ + out32(GPIO0_OR, 0x40000002); + out32(GPIO0_TCR, 0x4c90011f); + out32(GPIO0_OSRL, 0x28011400); + out32(GPIO0_OSRH, 0x55005000); + out32(GPIO0_TSRL, 0x08011400); + out32(GPIO0_TSRH, 0x55005000); + out32(GPIO0_ISR1L, 0x54000000); + out32(GPIO0_ISR1H, 0x00000000); + out32(GPIO0_ISR2L, 0x44000000); + out32(GPIO0_ISR2H, 0x00000100); + out32(GPIO0_ISR3L, 0x00000000); + out32(GPIO0_ISR3H, 0x00000000); + + out32(GPIO1_OR, 0x80002408); + out32(GPIO1_TCR, 0xd6003c08); + out32(GPIO1_OSRL, 0x0a5a0000); + out32(GPIO1_OSRH, 0x00000000); + out32(GPIO1_TSRL, 0x00000000); + out32(GPIO1_TSRH, 0x00000000); + out32(GPIO1_ISR1L, 0x00005555); + out32(GPIO1_ISR1H, 0x40000000); + out32(GPIO1_ISR2L, 0x04010000); + out32(GPIO1_ISR2H, 0x00000000); + out32(GPIO1_ISR3L, 0x01400000); + out32(GPIO1_ISR3H, 0x00000000); + + /* patch PLB:PCI divider for 66MHz PCI */ + mfcpr(clk_spcid, reg); + if (pci_is_66mhz() && (reg != 0x02000000)) { + mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ + + mfcpr(clk_icfg, reg); + reg |= CPR0_ICFG_RLI_MASK; + mtcpr(clk_icfg, reg); + + mtspr(dbcr0, 0x20000000); /* do chip reset */ + } + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffff7ef); + mtdcr(uic0tr, 0x00000000); + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffc7f5); + mtdcr(uic1tr, 0x00000000); + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0x27ffffff); + mtdcr(uic2tr, 0x00000000); + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + + /* select Ethernet pins */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; + mfsdr(SDR0_PFC2, sdr0_pfc2); + sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; + + /* enable 2nd IIC */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; + + mtsdr(SDR0_PFC2, sdr0_pfc2); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + /* setup NAND FLASH */ + mfsdr(SDR0_CUST0, sdr0_cust0); + sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NDFC_ARE_MASK | + (0x80000000 >> (28 + CFG_NAND_CS)); + mtsdr(SDR0_CUST0, sdr0_cust0); + + return 0; +} + +/*---------------------------------------------------------------------------+ + | misc_init_r. + +---------------------------------------------------------------------------*/ +int misc_init_r(void) +{ + uint pbcr; + int size_val = 0; + u32 reg; + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1; + char *act = getenv("usbact"); + + /* + * FLASH stuff... + */ + + /* Re-do sizing to get full correct info */ + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + mtdcr(ebccfga, pb2cr); +#else + mtdcr(ebccfga, pb0cr); +#endif + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + mtdcr(ebccfga, pb2cr); +#else + mtdcr(ebccfga, pb0cr); +#endif + mtdcr(ebccfgd, pbcr); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, 0); + +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + /* + * USB suff... + */ + if ((act == NULL || strcmp(act, "hostdev") == 0) && + !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){ + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* An 8-bit/60MHz interface is the only possible alternative + when connecting the Device to the PHY */ + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + + usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /*clear resets*/ + udelay(1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Host\n"); + + } else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + /*-------------------PATCH-------------------------------*/ + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + + udelay (1000); + mtsdr(SDR0_SRST1, 0x672c6000); + + udelay (1000); + mtsdr(SDR0_SRST0, 0x00000080); + + udelay (1000); + mtsdr(SDR0_SRST1, 0x60206000); + + *(unsigned int *)(0xe0000350) = 0x00000001; + + udelay (1000); + mtsdr(SDR0_SRST1, 0x60306000); + /*-------------------PATCH-------------------------------*/ + + /* SDR Setting */ + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_PFC1, sdr0_pfc1); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ + + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ + + usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + + sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ + + mtsdr(SDR0_USB2H0CR, usb2h0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + /*clear resets*/ + udelay(1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Device\n"); + } + + /* + * Clear PLB4A0_ACR[WRP] + * This fix will make the MAL burst disabling patch for the Linux + * EMAC driver obsolete. + */ + reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; + mtdcr(plb4_acr, reg); + +#ifdef CONFIG_FPGA + pmc440_init_fpga(); +#endif + + /* turn off POST LED */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N); + /* turn on RUN LED */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N); + return 0; +} + +int is_monarch(void) +{ + if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH) + return 0; + + return 1; +} + +int pci_is_66mhz(void) +{ + if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN) + return 1; + return 0; +} + +int board_revision(void) +{ + return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); +} + +int checkboard(void) +{ + puts("Board: esd GmbH - PMC440"); + + gd->board_type = board_revision(); + printf(", Rev 1.%ld, ", gd->board_type); + + if (!is_monarch()) { + puts("non-"); + } + + printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33"); + return (0); +} + + +#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) +/* + * Assign interrupts to PCI devices. Some OSs rely on this. + */ +void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB}; + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + int_line[PCI_DEV(dev) & 0x03]); +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + +#ifdef CONFIG_PCI_PNP + hose->fixup_irq = pmc440_pci_fixup_irq; +#endif + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440EPX PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, and enable region */ + + if (!is_monarch()) { + /* BAR1: top 64MB of RAM */ + out32r(PCIX0_PTM1MS, 0xfc000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0x0c000000); /* Local Addr. Reg */ + } else { + /* BAR1: complete 256MB RAM (TODO: make dynamic) */ + out32r(PCIX0_PTM1MS, 0xf0000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0x00000000); /* Local Addr. Reg */ + } + + /* BAR2: 16 MB FPGA registers */ + out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ + + if (is_monarch()) { + /* BAR2: map FPGA registers behind system memory at 1GB */ + pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008); + } + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + +#if 0 /* disabled for PMC405 backward compatibility */ + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); +#endif + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + + if (!is_monarch()) { + /* Program the board's subsystem id/classcode */ + pci_write_config_word(0, PCI_SUBSYSTEM_ID, + CFG_PCI_SUBSYS_ID_NONMONARCH); + pci_write_config_word(0, PCI_CLASS_SUB_CODE, + CFG_PCI_CLASSCODE_NONMONARCH); + + /* PCI configuration done: release ERREADY */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY); + out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); + } else { + /* Program the board's subsystem id/classcode */ + pci_write_config_word(0, PCI_SUBSYSTEM_ID, + CFG_PCI_SUBSYS_ID_MONARCH); + pci_write_config_word(0, PCI_CLASS_SUB_CODE, + CFG_PCI_CLASSCODE_MONARCH); + } +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + if (is_monarch()) { + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); + } +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + + +static void wait_for_pci_ready(void) +{ + int i; + char *s = getenv("pcidelay"); + if (s) { + int ms = simple_strtoul(s, NULL, 10); + printf("PCI: Waiting for %d ms\n", ms); + for (i=0; i<ms; i++) + udelay(1000); + } + + if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) { + printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); + while (1) { + if (ctrlc()) { + puts("abort\n"); + break; + } + if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) { + printf("done\n"); + break; + } + } + } +} + + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + char *s = getenv("pciscan"); + if (s == NULL) + if (is_monarch()) { + wait_for_pci_ready(); + return 1; + } else + return 0; + else if (!strcmp(s, "yes")) + return 1; + + return 0; +} +#endif /* defined(CONFIG_PCI) */ +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ + + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ + if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); + } + + if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); + } +} +#endif + +#if defined(CFG_EEPROM_WREN) +/* Input: <dev_addr> I2C address of EEPROM device to enable. + * <state> -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if <state> was -1. + */ +int eeprom_write_enable(unsigned dev_addr, int state) +{ + if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP)); + break; + } + } + return state; +} +#endif /* #if defined(CFG_EEPROM_WREN) */ + + +#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3 +int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +{ + unsigned end = offset + cnt; + unsigned blk_off; + int rcode = 0; + +#if defined(CFG_EEPROM_WREN) + eeprom_write_enable(dev_addr, 1); +#endif + /* Write data until done or would cross a write page boundary. + * We must write the address again when changing pages + * because the address counter only increments within a page. + */ + + while (offset < end) { + unsigned alen, len; + unsigned maxlen; + uchar addr[2]; + + blk_off = offset & 0xFF; /* block offset */ + + addr[0] = offset >> 8; /* block number */ + addr[1] = blk_off; /* block offset */ + alen = 2; + addr[0] |= dev_addr; /* insert device address */ + + len = end - offset; + +#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS) +#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) + + maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off); + if (maxlen > I2C_RXTX_LEN) + maxlen = I2C_RXTX_LEN; + + if (len > maxlen) + len = maxlen; + + if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) + rcode = 1; + + buffer += len; + offset += len; + +#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#endif + } +#if defined(CFG_EEPROM_WREN) + eeprom_write_enable(dev_addr, 0); +#endif + return rcode; +} + + +int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +{ + unsigned end = offset + cnt; + unsigned blk_off; + int rcode = 0; + + /* Read data until done or would cross a page boundary. + * We must write the address again when changing pages + * because the next page may be in a different device. + */ + while (offset < end) { + unsigned alen, len; + unsigned maxlen; + uchar addr[2]; + + blk_off = offset & 0xFF; /* block offset */ + + addr[0] = offset >> 8; /* block number */ + addr[1] = blk_off; /* block offset */ + alen = 2; + + addr[0] |= dev_addr; /* insert device address */ + + len = end - offset; + + maxlen = 0x100 - blk_off; + if (maxlen > I2C_RXTX_LEN) + maxlen = I2C_RXTX_LEN; + if (len > maxlen) + len = maxlen; + + if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) + rcode = 1; + buffer += len; + offset += len; + } + + return rcode; +} + + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) +int usb_board_init(void) +{ + char *act = getenv("usbact"); + int i; + + if ((act == NULL || strcmp(act, "hostdev") == 0) && + !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) + /* enable power on USB socket */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + + for (i=0; i<1000; i++) + udelay(1000); + + return 0; +} + +int usb_board_stop(void) +{ + /* disable power on USB socket */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N); + return 0; +} + +int usb_board_init_fail(void) +{ + usb_board_stop(); + return 0; +} +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h new file mode 100644 index 0000000000..7e70fd1cb7 --- /dev/null +++ b/board/esd/pmc440/pmc440.h @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PMC440_H__ +#define __PMC440_H__ + + +/*----------------------------------------------------------------------- + * GPIOs + */ +#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ +#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */ +#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */ +#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */ +#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */ +#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */ +#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */ + +#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */ +#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */ +#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ +#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ +#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ +#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */ + +/* FPGA programming pin configuration */ +#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ +#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ +#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ +#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */ +#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ +#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */ + +/*----------------------------------------------------------------------- + * FPGA interface + */ +#define FPGA_BA CFG_FPGA_BASE0 +#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v)) +#define FPGA_IN32(p) in_be32((void*)(p)) +#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v)) +#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v)) + +struct pmc440_fifo_s { + u32 data; + u32 ctrl; +}; + +/* fifo ctrl register */ +#define FIFO_IE (1 << 15) +#define FIFO_OVERFLOW (1 << 10) +#define FIFO_EMPTY (1 << 9) +#define FIFO_FULL (1 << 8) +#define FIFO_LEVEL_MASK 0x000000ff + +#define FIFO_COUNT 4 + +struct pmc440_fpga_s { + u32 ctrla; + u32 status; + u32 ctrlb; + u32 pad1[0x40 / sizeof(u32) - 3]; + u32 irig_time; /* offset: 0x0040 */ + u32 irig_tod; + u32 irig_cf; + u32 pad2; + u32 irig_rx_time; /* offset: 0x0050 */ + u32 pad3[3]; + u32 hostctrl; /* offset: 0x0060 */ + u32 pad4[0x20 / sizeof(u32) - 1]; + struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */ +}; + +typedef struct pmc440_fpga_s pmc440_fpga_t; + +/* ctrl register */ +#define CTRL_HOST_IE (1 << 8) + +/* outputs */ +#define RESET_EN (1 << 31) +#define CLOCK_EN (1 << 30) +#define RESET_OUT (1 << 19) +#define CLOCK_OUT (1 << 22) +#define RESET_OUT (1 << 19) +#define IRIGB_R_OUT (1 << 14) + + +/* status register */ +#define STATUS_VERSION_SHIFT 24 +#define STATUS_VERSION_MASK 0xff000000 +#define STATUS_HWREV_SHIFT 20 +#define STATUS_HWREV_MASK 0x00f00000 + +#define STATUS_CAN_ISF (1 << 11) +#define STATUS_CSTM_ISF (1 << 10) +#define STATUS_FIFO_ISF (1 << 9) +#define STATUS_HOST_ISF (1 << 8) + + +/* inputs */ +#define RESET_IN (1 << 0) +#define CLOCK_IN (1 << 1) +#define IRIGB_R_IN (1 << 5) + + +/* hostctrl register */ +#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) +#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) +#define HOSTCTRL_CSTM1IE_GATE (1 << 7) +#define HOSTCTRL_CSTM1IW_FLAG (1 << 6) +#define HOSTCTRL_CSTM0IE_GATE (1 << 5) +#define HOSTCTRL_CSTM0IW_FLAG (1 << 4) +#define HOSTCTRL_FIFOIE_GATE (1 << 3) +#define HOSTCTRL_FIFOIE_FLAG (1 << 2) +#define HOSTCTRL_HCINT_GATE (1 << 1) +#define HOSTCTRL_HCINT_FLAG (1 << 0) + +#define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000) +#define NGCC_CTRL_FPGARST_N (1 << 2) + +/*----------------------------------------------------------------------- + * FPGA to PPC interrupt + */ +#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */ +#define IRQ1_FPGA (32+30) /* UIC1 - custom module */ +#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */ +#define IRQ_ETH0 (64+ 4) /* UIC2 */ +#define IRQ_ETH1 ( 27) /* UIC0 */ +#define IRQ_RTC (64+ 0) /* UIC2 */ +#define IRQ_PCIA (64+ 1) /* UIC2 */ +#define IRQ_PCIB (32+18) /* UIC1 */ +#define IRQ_PCIC (32+19) /* UIC1 */ +#define IRQ_PCID (32+20) /* UIC1 */ + +#endif /* __PMC440_H__ */ diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c new file mode 100644 index 0000000000..78e2cb42a9 --- /dev/null +++ b/board/esd/pmc440/sdram.c @@ -0,0 +1,442 @@ +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debug output */ +#undef DEBUG + +#include <common.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <ppc440.h> + +#include "sdram.h" + +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ + defined(CONFIG_DDR_DATA_EYE) +/*-----------------------------------------------------------------------------+ + * wait_for_dlllock. + +----------------------------------------------------------------------------*/ +static int wait_for_dlllock(void) +{ + unsigned long val; + int wait = 0; + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_17); + val = DDR0_17_DLLLOCKREG_UNLOCKED; + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) + /* dlllockreg bit on */ + return 0; + else + wait++; + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + + return -1; +} +#endif + +#if defined(CONFIG_DDR_DATA_EYE) +/*-----------------------------------------------------------------------------+ + * wait_for_dram_init_complete. + +----------------------------------------------------------------------------*/ +int wait_for_dram_init_complete(void) +{ + unsigned long val; + int wait = 0; + + /* --------------------------------------------------------------+ + * Wait for 'DRAM initialization complete' bit in status register + * -------------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_00); + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) + /* 'DRAM initialization complete' bit */ + return 0; + else + wait++; + } + + debug("DRAM initialization complete bit in status register did not rise\n"); + + return -1; +} + +#define NUM_TRIES 64 +#define NUM_READS 10 + +/*-----------------------------------------------------------------------------+ + * denali_core_search_data_eye. + +----------------------------------------------------------------------------*/ +void denali_core_search_data_eye(unsigned long memory_size) +{ + int k, j; + u32 val; + u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; + u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; + u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; + u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; + volatile u32 *ram_pointer; + u32 test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; + + ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE); + + for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { + /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/ + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + + passing_cases = 0; + + for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) { + /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/ + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (wait_for_dlllock() != 0) { + printf("dlllock did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", + wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + ppcMsync(); + ppcMbar(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", + wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ + + /* write values */ + for (j=0; j<NUM_TRIES; j++) { + ram_pointer[j] = test[j]; + + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); + } + + /* read values back */ + for (j=0; j<NUM_TRIES; j++) { + for (k=0; k<NUM_READS; k++) { + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); + + if (ram_pointer[j] != test[j]) + break; + } + + /* read error */ + if (k != NUM_READS) + break; + } + + /* See if the dll_dqs_delay_X value passed.*/ + if (j < NUM_TRIES) { + /* Failed */ + passing_cases = 0; + /* break; */ + } else { + /* Passed */ + if (passing_cases == 0) + dll_dqs_delay_X_sw_val = dll_dqs_delay_X; + passing_cases++; + if (passing_cases >= max_passing_cases) { + max_passing_cases = passing_cases; + wr_dqs_shift_with_max_passing_cases = wr_dqs_shift; + dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val; + dll_dqs_delay_X_end_window = dll_dqs_delay_X; + } + } + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ + + } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ + + /* -----------------------------------------------------------+ + * Largest passing window is now detected. + * ----------------------------------------------------------*/ + + /* Compute dll_dqs_delay_X value */ + dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2; + wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; + + debug("DQS calibration - Window detected:\n"); + debug("max_passing_cases = %d\n", max_passing_cases); + debug("wr_dqs_shift = %d\n", wr_dqs_shift); + debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); + debug("dll_dqs_delay_X window = %d - %d\n", + dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_09=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_22=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_17=0x%08lx\n", val); + + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_18=0x%08lx\n", val); + + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_19=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (wait_for_dlllock() != 0) { + printf("dlllock did not occur !!!\n"); + hang(); + } + ppcMsync(); + ppcMbar(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ +} +#endif /* CONFIG_DDR_DATA_EYE */ + +#if defined(CONFIG_NAND_SPL) +/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big + * for the 4k NAND boot image so define bus_frequency to 133MHz here + * which is save for the refresh counter setup. + */ +#define get_bus_freq(val) 133000000 +#endif + +/************************************************************************* + * + * initdram -- 440EPx's DDR controller is a DENALI Core + * + ************************************************************************/ +long int initdram (int board_type) +{ +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_NAND_SPL) + ulong speed = get_bus_freq(0); +#else + ulong speed = 133333333; /* 133MHz is on the safe side */ +#endif + + mtsdram(DDR0_02, 0x00000000); + + mtsdram(DDR0_00, 0x0000190A); + mtsdram(DDR0_01, 0x01000000); + mtsdram(DDR0_03, 0x02030602); + mtsdram(DDR0_04, 0x0A020200); + mtsdram(DDR0_05, 0x02020308); + mtsdram(DDR0_06, 0x0102C812); + mtsdram(DDR0_07, 0x000D0100); + mtsdram(DDR0_08, 0x02430001); + mtsdram(DDR0_09, 0x00011D5F); + mtsdram(DDR0_10, 0x00000300); + mtsdram(DDR0_11, 0x0027C800); + mtsdram(DDR0_12, 0x00000003); + mtsdram(DDR0_14, 0x00000000); + mtsdram(DDR0_17, 0x19000000); + mtsdram(DDR0_18, 0x19191919); + mtsdram(DDR0_19, 0x19191919); + mtsdram(DDR0_20, 0x0B0B0B0B); + mtsdram(DDR0_21, 0x0B0B0B0B); + mtsdram(DDR0_22, 0x00267F0B); + mtsdram(DDR0_23, 0x00000000); + mtsdram(DDR0_24, 0x01010002); + if (speed > 133333334) + mtsdram(DDR0_26, 0x5B26050C); + else + mtsdram(DDR0_26, 0x5B260408); + mtsdram(DDR0_27, 0x0000682B); + mtsdram(DDR0_28, 0x00000000); + mtsdram(DDR0_31, 0x00000000); + mtsdram(DDR0_42, 0x01000006); + mtsdram(DDR0_43, 0x030A0200); + mtsdram(DDR0_44, 0x00000003); + mtsdram(DDR0_02, 0x00000001); + + wait_for_dlllock(); +#endif /* #ifndef CONFIG_NAND_U_BOOT */ + +#ifdef CONFIG_DDR_DATA_EYE + /* -----------------------------------------------------------+ + * Perform data eye search if requested. + * ----------------------------------------------------------*/ + denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20); +#endif + + return (CFG_MBYTES_SDRAM << 20); +} diff --git a/board/esd/pmc440/sdram.h b/board/esd/pmc440/sdram.h new file mode 100644 index 0000000000..7f847aa2ad --- /dev/null +++ b/board/esd/pmc440/sdram.h @@ -0,0 +1,505 @@ +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPD_SDRAM_DENALI_H_ +#define _SPD_SDRAM_DENALI_H_ + +#define ppcMsync sync +#define ppcMbar eieio + +/* General definitions */ +#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */ +#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */ +#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */ +#define SDRAM_NONE 0 /* No DIMM detected in Slot */ +#define MAXRANKS 2 /* 2 ranks maximum */ + +/* Supported PLB Frequencies */ +#define PLB_FREQ_133MHZ 133333333 +#define PLB_FREQ_152MHZ 152000000 +#define PLB_FREQ_160MHZ 160000000 +#define PLB_FREQ_166MHZ 166666666 + +/* Denali Core Registers */ +#define SDRAM_DCR_BASE 0x10 + +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +/*-----------------------------------------------------------------------------+ + | Values for ddrcfga register - indirect addressing of these regs + +-----------------------------------------------------------------------------*/ + +#define DDR0_00 0x00 +#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +/* Status */ +#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ +/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT0 0x00010000 +/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT1 0x00020000 +/* Bit2. Single correctable ECC event detected */ +#define DDR0_00_INT_STATUS_BIT2 0x00040000 +/* Bit3. Multiple correctable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT3 0x00080000 +/* Bit4. Single uncorrectable ECC event detected. */ +#define DDR0_00_INT_STATUS_BIT4 0x00100000 +/* Bit5. Multiple uncorrectable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT5 0x00200000 +/* Bit6. DRAM initialization complete. */ +#define DDR0_00_INT_STATUS_BIT6 0x00400000 +/* Bit7. Logical OR of all lower bits. */ +#define DDR0_00_INT_STATUS_BIT7 0x00800000 + +#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 +#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_00_DLL_START_POINT_MASK 0x0000007F +#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + + +#define DDR0_01 0x01 +#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 +#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 +#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ +#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_02 0x02 +#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ +#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) +#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) +#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ +#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ +#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_02_START_MASK 0x00000001 +#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) +#define DDR0_02_START_OFF 0x00000000 +#define DDR0_02_START_ON 0x00000001 + +#define DDR0_03 0x03 +#define DDR0_03_BSTLEN_MASK 0x07000000 +#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_03_CASLAT_MASK 0x00070000 +#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 +#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_03_INITAREF_MASK 0x0000000F +#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_04 0x04 +#define DDR0_04_TRC_MASK 0x1F000000 +#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_04_TRRD_MASK 0x00070000 +#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_04_TRTP_MASK 0x00000700 +#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) + +#define DDR0_05 0x05 +#define DDR0_05_TMRD_MASK 0x1F000000 +#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_05_TEMRS_MASK 0x00070000 +#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_05_TRP_MASK 0x00000F00 +#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_05_TRAS_MIN_MASK 0x000000FF +#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#define DDR0_06 0x06 +#define DDR0_06_WRITEINTERP_MASK 0x01000000 +#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_06_TWTR_MASK 0x00070000 +#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_06_TDLL_MASK 0x0000FF00 +#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_06_TRFC_MASK 0x0000007F +#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_07 0x07 +#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 +#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_07_TFAW_MASK 0x001F0000 +#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 +#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_07_AREFRESH_MASK 0x00000001 +#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_08 0x08 +#define DDR0_08_WRLAT_MASK 0x07000000 +#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_08_TCPD_MASK 0x00FF0000 +#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_08_DQS_N_EN_MASK 0x00000100 +#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 +#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_09 0x09 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_09_RTT_0_MASK 0x00030000 +#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 +#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F +#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_10 0x0A +#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ +#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_10_CS_MAP_MASK 0x00000300 +#define DDR0_10_CS_MAP_NO_MEM 0x00000000 +#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 +#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 +#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F +#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) + +#define DDR0_11 0x0B +#define DDR0_11_SREFRESH_MASK 0x01000000 +#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_11_TXSNR_MASK 0x00FF0000 +#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_11_TXSR_MASK 0x0000FF00 +#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) + +#define DDR0_12 0x0C +#define DDR0_12_TCKE_MASK 0x0000007 +#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) + +#define DDR0_13 0x0D + +#define DDR0_14 0x0E +#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 +#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_14_REDUC_MASK 0x00010000 +#define DDR0_14_REDUC_64BITS 0x00000000 +#define DDR0_14_REDUC_32BITS 0x00010000 +#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 +#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) + +#define DDR0_15 0x0F + +#define DDR0_16 0x10 + +#define DDR0_17 0x11 +#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 +#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ +#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) + +#define DDR0_18 0x12 +#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 +#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 +#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 +#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F +#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_19 0x13 +#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 +#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 +#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 +#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F +#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_20 0x14 +#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 +#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 +#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 +#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F +#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_21 0x15 +#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 +#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 +#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 +#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F +#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_22 0x16 +/* ECC */ +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ +#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) + +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 +#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F +#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + + +#define DDR0_23 0x17 +#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 +#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ +#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ +#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ +#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_24 0x18 +#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 +#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 +#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 +#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 +#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) +#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) + +#define DDR0_25 0x19 +#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ +#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ +#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_26 0x1A +#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 +#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_26_TREF_MASK 0x00003FFF +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_27 0x1B +#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 +#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_27_TINIT_MASK 0x0000FFFF +#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_28 0x1C +#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 +#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF +#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) + +#define DDR0_29 0x1D + +#define DDR0_30 0x1E + +#define DDR0_31 0x1F +#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF +#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_32 0x20 +#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_33 0x21 +#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_34 0x22 +#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_35 0x23 +#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_36 0x24 +#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_37 0x25 +#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_38 0x26 +#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_39 0x27 +#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_40 0x28 +#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_41 0x29 +#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_42 0x2A +#define DDR0_42_ADDR_PINS_MASK 0x07000000 +#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F +#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_43 0x2B +#define DDR0_43_TWR_MASK 0x07000000 +#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_43_APREBIT_MASK 0x000F0000 +#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 +#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 +#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_44 0x2C +#define DDR0_44_TRCD_MASK 0x000000FF +#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#endif /* _SPD_SDRAM_DENALI_H_ */ diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds new file mode 100644 index 0000000000..cf2e2b5581 --- /dev/null +++ b/board/esd/pmc440/u-boot-nand.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cpci440/u-boot.lds b/board/esd/pmc440/u-boot.lds index b1b4ad2a97..a423f98285 100644 --- a/board/esd/cpci440/u-boot.lds +++ b/board/esd/pmc440/u-boot.lds @@ -28,13 +28,11 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/ SECTIONS { .resetvec 0xFFFFFFFC : -/* .resetvec 0x01FFFFFC :*/ { *(.resetvec) } = 0xffff .bootpg 0xFFFFF000 : -/* .bootpg 0x01FFF000 :*/ { cpu/ppc4xx/start.o (.bootpg) } = 0xffff @@ -69,20 +67,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/esd/cpci440/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -95,7 +79,6 @@ SECTIONS *(.rodata) *(.rodata1) *(.rodata.str1.4) - *(.eh_frame) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } @@ -154,6 +137,9 @@ SECTIONS *(.bss) *(COMMON) } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + _end = . ; PROVIDE (end = .); } diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 2857a0bef5..87a584979b 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/processor.h> #include <command.h> #include <malloc.h> @@ -112,11 +113,11 @@ int misc_init_f (void) int misc_init_r (void) { - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - volatile unsigned short *lcd_contrast = + unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + unsigned short *lcd_contrast = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); - volatile unsigned short *lcd_backlight = + unsigned short *lcd_backlight = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); unsigned char *dst; ulong len = sizeof(fpgadata); @@ -180,25 +181,37 @@ int misc_init_r (void) /* * Reset FPGA via FPGA_INIT pin */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */ + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */ udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */ udelay(1000); /* wait 1ms */ /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* + * Set NAND-FLASH GPIO signals to default + */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE); + + /* + * Setup EEPROM write protection + */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP); + + /* * Enable interrupts in exar duart mcr[3] */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; + out_8(duart0_mcr, 0x08); + out_8(duart1_mcr, 0x08); /* * Init lcd interface and display logo @@ -240,17 +253,23 @@ int misc_init_r (void) /* * Set invert bit in small lcd controller */ - *(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01; + out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2), + in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01); /* * Set default contrast voltage on epson vga controller */ - *lcd_contrast = 0x4646; + out_be16(lcd_contrast, 0x4646); /* * Enable backlight */ - *lcd_backlight = 0xffff; + out_be16(lcd_backlight, 0xffff); + + /* + * Enable external I2C bus + */ + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON); return (0); } @@ -281,11 +300,6 @@ int checkboard (void) putc ('\n'); - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - return 0; } @@ -334,3 +348,86 @@ void ide_set_reset(int on) } } #endif /* CONFIG_IDE_RESET */ + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#ifdef CONFIG_LXT971_NO_SLEEP + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif +} +#endif + +#if defined(CFG_EEPROM_WREN) +/* Input: <dev_addr> I2C address of EEPROM device to enable. + * <state> -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if <state> was -1. + */ +int eeprom_write_enable (unsigned dev_addr, int state) +{ + if (CFG_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO0. */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO0. */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP)); + break; + } + } + return state; +} + +int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + if (state < 0) { + puts ("Query of write access state failed.\n"); + } else { + printf ("Write access for device 0x%0x is %sabled.\n", + CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + } + if (state < 0) { + puts ("Setup of write access state failed.\n"); + } + } + + return state; +} + +U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL); +#endif /* #if defined(CFG_EEPROM_WREN) */ diff --git a/board/cds/common/cadmus.c b/board/freescale/common/cadmus.c index 5f86de5af2..5f86de5af2 100644 --- a/board/cds/common/cadmus.c +++ b/board/freescale/common/cadmus.c diff --git a/board/cds/common/cadmus.h b/board/freescale/common/cadmus.h index 217ea64251..217ea64251 100644 --- a/board/cds/common/cadmus.h +++ b/board/freescale/common/cadmus.h diff --git a/board/cds/common/eeprom.c b/board/freescale/common/eeprom.c index 5034e0ca2e..5034e0ca2e 100644 --- a/board/cds/common/eeprom.c +++ b/board/freescale/common/eeprom.c diff --git a/board/cds/common/eeprom.h b/board/freescale/common/eeprom.h index 12a0789049..12a0789049 100644 --- a/board/cds/common/eeprom.h +++ b/board/freescale/common/eeprom.h diff --git a/board/cds/common/ft_board.c b/board/freescale/common/ft_board.c index 3eda1009ef..6f221aff26 100644 --- a/board/cds/common/ft_board.c +++ b/board/freescale/common/ft_board.c @@ -21,24 +21,29 @@ */ #include <common.h> - -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> +#include <libfdt.h> +#include <fdt_support.h> #include "cadmus.h" -extern void ft_cpu_setup(void *blob, bd_t *bd); - +#if defined(CONFIG_OF_BOARD_SETUP) static void cds_pci_fixup(void *blob) { - int len; - u32 *map; - int slot; - int i; + int node, tmp[2]; + const char *path; + int len, slot, i; + u32 *map = NULL; - map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len); - - if (!map) - map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len); + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + node = fdt_path_offset(blob, path); + if (node >= 0) { + map = fdt_getprop_w(blob, node, "interrupt-map", &len); + } + } + } if (map) { len /= sizeof(u32); @@ -50,33 +55,18 @@ static void cds_pci_fixup(void *blob) * changes depending on the slot the carrier card is in. */ map[3] = ((map[3] + slot - 2) % 4) + 1; - map+=7; } - } else { - printf("*** Warning - No PCI node found\n"); } } -#endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { - u32 *p; - int len; - + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } - cds_pci_fixup(blob); +#endif } #endif diff --git a/board/cds/common/via.c b/board/freescale/common/via.c index 4a63d77944..4a63d77944 100644 --- a/board/cds/common/via.c +++ b/board/freescale/common/via.c diff --git a/board/cds/common/via.h b/board/freescale/common/via.h index 77cfacc526..77cfacc526 100644 --- a/board/cds/common/via.h +++ b/board/freescale/common/via.h diff --git a/board/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile index 29136508f5..29136508f5 100644 --- a/board/mpc8540ads/Makefile +++ b/board/freescale/mpc8540ads/Makefile diff --git a/board/mpc8540ads/config.mk b/board/freescale/mpc8540ads/config.mk index 92f8931979..92f8931979 100644 --- a/board/mpc8540ads/config.mk +++ b/board/freescale/mpc8540ads/config.mk diff --git a/board/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S index 544fde94c4..544fde94c4 100644 --- a/board/mpc8540ads/init.S +++ b/board/freescale/mpc8540ads/init.S diff --git a/board/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 914e51a760..35f5eeaf03 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -30,11 +30,8 @@ #include <asm/processor.h> #include <asm/immap_85xx.h> #include <spd.h> - -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif - +#include <libfdt.h> +#include <fdt_support.h> #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -77,13 +74,12 @@ initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* @@ -125,9 +121,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -186,8 +181,7 @@ local_bus_init(void) void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; puts(" SDRAM: "); @@ -282,8 +276,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; @@ -331,22 +324,25 @@ pci_init_board(void) } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { - u32 *p; - int len; + int node, tmp[2]; + const char *path; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = hose.last_busno - hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif } } #endif diff --git a/board/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds index e7a88cfa44..a7c68b3648 100644 --- a/board/mpc8540ads/u-boot.lds +++ b/board/freescale/mpc8540ads/u-boot.lds @@ -35,7 +35,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/mpc8540ads/init.o (.bootpg) + board/freescale/mpc8540ads/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -65,7 +65,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/mpc8540ads/init.o (.text) + board/freescale/mpc8540ads/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/cds/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile index 7f53098850..7f53098850 100644 --- a/board/cds/mpc8541cds/Makefile +++ b/board/freescale/mpc8541cds/Makefile diff --git a/board/cds/mpc8541cds/config.mk b/board/freescale/mpc8541cds/config.mk index 17cc8bce9c..17cc8bce9c 100644 --- a/board/cds/mpc8541cds/config.mk +++ b/board/freescale/mpc8541cds/config.mk diff --git a/board/cds/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S index 978bda5e4d..978bda5e4d 100644 --- a/board/cds/mpc8541cds/init.S +++ b/board/freescale/mpc8541cds/init.S diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 558ba9903c..9ab98d4b68 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -28,6 +28,8 @@ #include <asm/immap_85xx.h> #include <ioports.h> #include <spd.h> +#include <libfdt.h> +#include <fdt_support.h> #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -203,8 +205,7 @@ int board_early_init_f (void) int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -250,7 +251,6 @@ long int initdram(int board_type) { long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); @@ -263,7 +263,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -293,9 +293,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -344,8 +343,7 @@ sdram_init(void) #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -506,3 +504,31 @@ pci_init_board(void) pci_mpc85xx_init(hose); #endif } + +#if defined(CONFIG_OF_BOARD_SETUP) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI1 + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = hose[0].last_busno - hose[0].first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_MPC85XX_PCI2 + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = hose[1].last_busno - hose[1].first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds index de0923a0d8..4360d677ec 100644 --- a/board/cds/mpc8555cds/u-boot.lds +++ b/board/freescale/mpc8541cds/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/cds/mpc8555cds/init.o (.bootpg) + board/freescale/mpc8541cds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +64,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/cds/mpc8555cds/init.o (.text) + board/freescale/mpc8541cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 68ccba746b..084d4b80d9 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -27,13 +27,6 @@ #include <config.h> #include <mpc85xx.h> -#define LAWAR_TRGT_PCI1 0x00000000 -#define LAWAR_TRGT_PCIE1 0x00200000 -#define LAWAR_TRGT_PCIE2 0x00100000 -#define LAWAR_TRGT_PCIE3 0x00300000 -#define LAWAR_TRGT_LBC 0x00400000 -#define LAWAR_TRGT_DDR 0x00f00000 - /* * TLB0 and TLB1 Entries * @@ -212,31 +205,31 @@ law_entry: .long (4f-3f)/8 3: .long 0 - .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN + .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) + .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) + .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) + .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) + .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) /* contains both PCIE3 MEM & IO space */ .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) 4: entry_end diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index b6c9e93d50..66cb536a4b 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -29,14 +29,11 @@ #include <asm/io.h> #include <spd.h> #include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> #include "../common/pixis.h" -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -extern void ft_cpu_setup(void *blob, bd_t *bd); -#endif - #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -52,10 +49,9 @@ int board_early_init_f (void) int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %x\n",&gur->porpllsr); @@ -149,8 +145,7 @@ int first_free_busno=0; void pci_init_board(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; @@ -508,51 +503,47 @@ get_board_sys_clk(ulong dummy) return val; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) + void ft_board_setup(void *blob, bd_t *bd) { - u32 *p; - int len; + int node, tmp[2]; + const char *path; ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { #ifdef CONFIG_PCI1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pci1_hose.last_busno - pci1_hose.first_busno; - debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } -#endif -#ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } #endif #ifdef CONFIG_PCIE2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; - debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE1 + path = fdt_getprop(blob, node, "pci2", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } #endif #ifdef CONFIG_PCIE3 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;; - debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci3", NULL); + if (path) { + tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } #endif + } } #endif diff --git a/board/cds/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile index 7f53098850..7f53098850 100644 --- a/board/cds/mpc8548cds/Makefile +++ b/board/freescale/mpc8548cds/Makefile diff --git a/board/cds/mpc8548cds/config.mk b/board/freescale/mpc8548cds/config.mk index b23bc8737d..b23bc8737d 100644 --- a/board/cds/mpc8548cds/config.mk +++ b/board/freescale/mpc8548cds/config.mk diff --git a/board/cds/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S index 72940b0350..a83a0952c3 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/freescale/mpc8548cds/init.S @@ -28,13 +28,6 @@ #include <config.h> #include <mpc85xx.h> -#define LAWAR_TRGT_PCI1 0x00000000 -#define LAWAR_TRGT_PCI2 0x00100000 -#define LAWAR_TRGT_PCIE 0x00200000 -#define LAWAR_TRGT_RIO 0x00c00000 -#define LAWAR_TRGT_LBC 0x00400000 -#define LAWAR_TRGT_DDR 0x00f00000 - /* * TLB0 and TLB1 Entries * @@ -232,39 +225,39 @@ law_entry: .long (4f-3f)/8 3: .long 0 - .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN + .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN #ifdef CFG_PCI1_MEM_PHYS .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) #endif #ifdef CFG_PCI2_MEM_PHYS .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) #endif #ifdef CFG_PCIE1_MEM_PHYS .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) + .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M) #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) + .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) #ifdef CFG_RIO_MEM_PHYS .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) + .long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) #endif 4: entry_end diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 36d7e1ed48..47e2dd86cb 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -29,14 +29,13 @@ #include <asm/immap_fsl_pci.h> #include <spd.h> #include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> #include "../common/cadmus.h" #include "../common/eeprom.h" #include "../common/via.h" -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -55,9 +54,8 @@ int board_early_init_f (void) int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -96,7 +94,6 @@ long int initdram(int board_type) { long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); @@ -109,7 +106,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -139,9 +136,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -177,8 +173,7 @@ sdram_init(void) #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -330,8 +325,7 @@ int first_free_busno=0; void pci_init_board(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; @@ -524,30 +518,30 @@ int last_stage_init(void) } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void ft_pci_setup(void *blob, bd_t *bd) { - u32 *p; - int len; - + int node, tmp[2]; + const char *path; + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { #ifdef CONFIG_PCI1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pci1_hose.last_busno - pci1_hose.first_busno; - debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } #endif - #ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } #endif + } } #endif diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds index b19c481a96..ee772d3ae2 100644 --- a/board/cds/mpc8548cds/u-boot.lds +++ b/board/freescale/mpc8548cds/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/cds/mpc8548cds/init.o (.bootpg) + board/freescale/mpc8548cds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +64,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/cds/mpc8548cds/init.o (.text) + board/freescale/mpc8548cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/cds/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile index 7f53098850..7f53098850 100644 --- a/board/cds/mpc8555cds/Makefile +++ b/board/freescale/mpc8555cds/Makefile diff --git a/board/cds/mpc8555cds/config.mk b/board/freescale/mpc8555cds/config.mk index 5dcaa774db..5dcaa774db 100644 --- a/board/cds/mpc8555cds/config.mk +++ b/board/freescale/mpc8555cds/config.mk diff --git a/board/cds/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S index 978bda5e4d..978bda5e4d 100644 --- a/board/cds/mpc8555cds/init.S +++ b/board/freescale/mpc8555cds/init.S diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 8f1642187c..74c220d4fd 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -26,6 +26,8 @@ #include <asm/immap_85xx.h> #include <ioports.h> #include <spd.h> +#include <libfdt.h> +#include <fdt_support.h> #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -201,8 +203,7 @@ int board_early_init_f (void) int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -248,7 +249,6 @@ long int initdram(int board_type) { long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); @@ -261,7 +261,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -291,9 +291,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -342,8 +341,7 @@ sdram_init(void) #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -506,3 +504,31 @@ pci_init_board(void) pci_mpc85xx_init(hose); #endif } + +#if defined(CONFIG_OF_BOARD_SETUP) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI1 + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = hose[0].last_busno - hose[0].first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_MPC85XX_PCI2 + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = hose[1].last_busno - hose[1].first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds index 7a5daefeb7..df21ea86e6 100644 --- a/board/cds/mpc8541cds/u-boot.lds +++ b/board/freescale/mpc8555cds/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/cds/mpc8541cds/init.o (.bootpg) + board/freescale/mpc8555cds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +64,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/cds/mpc8541cds/init.o (.text) + board/freescale/mpc8555cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile index 29136508f5..29136508f5 100644 --- a/board/mpc8560ads/Makefile +++ b/board/freescale/mpc8560ads/Makefile diff --git a/board/mpc8560ads/config.mk b/board/freescale/mpc8560ads/config.mk index 9aef2bb163..9aef2bb163 100644 --- a/board/mpc8560ads/config.mk +++ b/board/freescale/mpc8560ads/config.mk diff --git a/board/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S index 544fde94c4..544fde94c4 100644 --- a/board/mpc8560ads/init.S +++ b/board/freescale/mpc8560ads/init.S diff --git a/board/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index eef524b45e..bb7f11bcc8 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -32,10 +32,8 @@ #include <ioports.h> #include <spd.h> #include <miiphy.h> - -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif +#include <libfdt.h> +#include <fdt_support.h> #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -278,13 +276,12 @@ initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* @@ -326,9 +323,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -387,8 +383,7 @@ local_bus_init(void) void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; puts(" SDRAM: "); @@ -483,8 +478,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; @@ -548,35 +542,25 @@ pci_init_board(void) } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_soc_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len); - - if (p != NULL) - *p = cpu_to_be32(bd->bi_brgfreq); - - p = ft_get_prop(blob, - "/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed", - &len); - if (p != NULL) - *p = cpu_to_be32(bd->bi_baudrate); - - p = ft_get_prop(blob, - "/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed", - &len); - if (p != NULL) - *p = cpu_to_be32(bd->bi_baudrate); -} - +#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { + int node, tmp[2]; + const char *path; + ft_cpu_setup(blob, bd); - ft_soc_setup(blob, bd); + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = hose.last_busno - hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } } #endif diff --git a/board/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds index 726a153f98..c2cba617ea 100644 --- a/board/mpc8560ads/u-boot.lds +++ b/board/freescale/mpc8560ads/u-boot.lds @@ -35,7 +35,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/mpc8560ads/init.o (.bootpg) + board/freescale/mpc8560ads/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -65,7 +65,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/mpc8560ads/init.o (.text) + board/freescale/mpc8560ads/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/board/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile index a799aa4cc5..643fbc041d 100644 --- a/board/mpc8568mds/Makefile +++ b/board/freescale/mpc8568mds/Makefile @@ -29,9 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ - bcsr.o \ - ft_board.o +COBJS := $(BOARD).o bcsr.o SOBJS := init.o diff --git a/board/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c index aae0f98e03..aae0f98e03 100644 --- a/board/mpc8568mds/bcsr.c +++ b/board/freescale/mpc8568mds/bcsr.c diff --git a/board/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h index aefd9bf54d..aefd9bf54d 100644 --- a/board/mpc8568mds/bcsr.h +++ b/board/freescale/mpc8568mds/bcsr.h diff --git a/board/mpc8568mds/config.mk b/board/freescale/mpc8568mds/config.mk index 021522cafc..021522cafc 100644 --- a/board/mpc8568mds/config.mk +++ b/board/freescale/mpc8568mds/config.mk diff --git a/board/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S index 972a7d4299..e36036daf0 100644 --- a/board/mpc8568mds/init.S +++ b/board/freescale/mpc8568mds/init.S @@ -28,7 +28,6 @@ #include <config.h> #include <mpc85xx.h> - /* * TLB0 and TLB1 Entries * @@ -216,15 +215,14 @@ tlb1_entry: #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) -#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M)) - +#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) diff --git a/board/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 818ff138a9..460cb1b275 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -26,9 +26,12 @@ #include <pci.h> #include <asm/processor.h> #include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> #include <spd.h> #include <i2c.h> #include <ioports.h> +#include <libfdt.h> +#include <fdt_support.h> #include "bcsr.h" @@ -133,7 +136,6 @@ long int initdram(int board_type) { long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); @@ -146,7 +148,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -176,9 +178,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -211,8 +212,7 @@ sdram_init(void) #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint lsdmr_common; @@ -337,16 +337,19 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = { }; #endif -static struct pci_controller hose[] = { - { +static struct pci_controller pci1_hose = { #ifndef CONFIG_PCI_PNP config_table: pci_mpc8568mds_config_table, #endif - } }; - #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +int first_free_busno = 0; + /* * pib_init() -- Initialize the PCA9555 IO expander on the PIB board */ @@ -389,11 +392,164 @@ pib_init(void) asm("eieio"); } +#ifdef CONFIG_PCI void pci_init_board(void) { -#ifdef CONFIG_PCI + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + +#ifdef CONFIG_PCI1 +{ pib_init(); - pci_mpc85xx_init(hose); + + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + + uint pci_32 = 1; /* PORDEVSR[15] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + + uint pci_speed = 66666000; + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter" + ); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno = hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif + +#ifdef CONFIG_PCIE1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE connected to slot as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); + + first_free_busno=hose->last_busno+1; + + } else { + printf (" PCIE: disabled\n"); + } } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif +} +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + + ft_cpu_setup(blob, bd); + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI1 + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE1 + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif diff --git a/board/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds index 71099f6f13..4682041ad7 100644 --- a/board/mpc8568mds/u-boot.lds +++ b/board/freescale/mpc8568mds/u-boot.lds @@ -37,7 +37,7 @@ SECTIONS .bootpg 0xFFFFF000: { cpu/mpc85xx/start.o (.bootpg) - board/mpc8568mds/init.o (.bootpg) + board/freescale/mpc8568mds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -67,7 +67,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/mpc8568mds/init.o (.text) + board/freescale/mpc8568mds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/korat/Makefile b/board/korat/Makefile new file mode 100644 index 0000000000..fa19e6feaa --- /dev/null +++ b/board/korat/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2002-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/korat/config.mk b/board/korat/config.mk new file mode 100644 index 0000000000..39966e03eb --- /dev/null +++ b/board/korat/config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# Korat (PPC440EPx) board +# + +TEXT_BASE = 0xFFFA0000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/korat/init.S b/board/korat/init.S new file mode 100644 index 0000000000..bd0e8b4daa --- /dev/null +++ b/board/korat/init.S @@ -0,0 +1,80 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <asm-ppc/mmu.h> +#include <config.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + + /* + * TLB entries for SDRAM are not needed on this platform. They are + * generated dynamically in the SPD DDR2 detection routine. + */ + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) +#endif + + /* TLB-entry for PCI Memory */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for EBC */ + tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for Internal Registers & OCM */ + /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */ + tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /*TLB-entry PCI registers*/ + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for peripherals */ + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I) + + /* TLB-entry PCI IO Space - from sr@denx.de */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I) + + tlbtab_end diff --git a/board/korat/korat.c b/board/korat/korat.c new file mode 100644 index 0000000000..7cb9ee11f3 --- /dev/null +++ b/board/korat/korat.c @@ -0,0 +1,761 @@ +/* + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm-ppc/io.h> +#include <i2c.h> +#include <ppc440.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +ulong flash_get_size(ulong base, int banknum); + +int board_early_init_f(void) +{ + u32 sdr0_pfc1, sdr0_pfc2; + u32 gpio0_ir; + u32 reg; + int eth; + + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, 0xb8400000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + * + * Korat GPIO usage: + * + * Init. + * Pin Source I/O value Function + * ------ ------ --- ----- --------------------------------- + * GPIO00 Alt1 I/O x PerAddr07 + * GPIO01 Alt1 I/O x PerAddr06 + * GPIO02 Alt1 I/O x PerAddr05 + * GPIO03 GPIO x x GPIO03 to expansion bus connector + * GPIO04 GPIO x x GPIO04 to expansion bus connector + * GPIO05 GPIO x x GPIO05 to expansion bus connector + * GPIO06 Alt1 O x PerCS1 (2nd NOR flash) + * GPIO07 Alt1 O x PerCS2 (CPLD) + * GPIO08 Alt1 O x PerCS3 to expansion bus connector + * GPIO09 Alt1 O x PerCS4 to expansion bus connector + * GPIO10 Alt1 O x PerCS5 to expansion bus connector + * GPIO11 Alt1 I x PerErr + * GPIO12 GPIO O 0 ATMega !Reset + * GPIO13 GPIO O 1 SPI Atmega !SS + * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8) + * GPIO15 GPIO O 0 CPU Run LED !On + * GPIO16 Alt1 O x GMC1TxD0 + * GPIO17 Alt1 O x GMC1TxD1 + * GPIO18 Alt1 O x GMC1TxD2 + * GPIO19 Alt1 O x GMC1TxD3 + * GPIO20 Alt1 O x RejectPkt0 + * GPIO21 Alt1 O x RejectPkt1 + * GPIO22 GPIO I x PGOOD_DDR + * GPIO23 Alt1 O x SCPD0 + * GPIO24 Alt1 O x GMC0TxD2 + * GPIO25 Alt1 O x GMC0TxD3 + * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4) + * GPIO27 GPIO O 0 PHY #0 1000BASE-X + * GPIO28 GPIO O 0 PHY #1 1000BASE-X + * GPIO29 GPIO I x Test jumper !Present + * GPIO30 GPIO I x SFP module #0 !Present + * GPIO31 GPIO I x SFP module #1 !Present + * + * GPIO32 GPIO O 1 SFP module #0 Tx !Enable + * GPIO33 GPIO O 1 SFP module #1 Tx !Enable + * GPIO34 Alt2 I x !UART1_CTS + * GPIO35 Alt2 O x !UART1_RTS + * GPIO36 Alt1 I x !UART0_CTS + * GPIO37 Alt1 O x !UART0_RTS + * GPIO38 Alt2 O x UART1_Tx + * GPIO39 Alt2 I x UART1_Rx + * GPIO40 Alt1 I x IRQ0 (Ethernet 0) + * GPIO41 Alt1 I x IRQ1 (Ethernet 1) + * GPIO42 Alt1 I x IRQ2 (PCI interrupt) + * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD) + * GPIO44 xxxx x x (grounded through pulldown) + * GPIO45 GPIO O 0 PHY #0 Enable + * GPIO46 GPIO O 0 PHY #1 Enable + * GPIO47 GPIO I x Reset switch !Pressed + * GPIO48 GPIO I x Shutdown switch !Pressed + * GPIO49 xxxx x x (reserved for trace port) + * . . . . . + * . . . . . + * . . . . . + * GPIO63 xxxx x x (reserved for trace port) + *-------------------------------------------------------------------*/ + + out_be32((u32 *) GPIO0_OR, 0x00060000); + out_be32((u32 *) GPIO1_OR, 0xC0000000); + + out_be32((u32 *) GPIO0_OSRL, 0x54055400); + out_be32((u32 *) GPIO0_OSRH, 0x55015000); + out_be32((u32 *) GPIO1_OSRL, 0x02180000); + out_be32((u32 *) GPIO1_OSRH, 0x00000000); + + out_be32((u32 *) GPIO0_TSRL, 0x54055500); + out_be32((u32 *) GPIO0_TSRH, 0x00015000); + out_be32((u32 *) GPIO1_TSRL, 0x00000000); + out_be32((u32 *) GPIO1_TSRH, 0x00000000); + + out_be32((u32 *) GPIO0_TCR, 0x000FF0D8); + out_be32((u32 *) GPIO1_TCR, 0xD6060000); + + out_be32((u32 *) GPIO0_ISR1L, 0x54000100); + out_be32((u32 *) GPIO0_ISR1H, 0x00500000); + out_be32((u32 *) GPIO1_ISR1L, 0x00405500); + out_be32((u32 *) GPIO1_ISR1H, 0x00000000); + + out_be32((u32 *) GPIO0_ISR2L, 0x00000000); + out_be32((u32 *) GPIO0_ISR2H, 0x00000000); + out_be32((u32 *) GPIO1_ISR2L, 0x04010000); + out_be32((u32 *) GPIO1_ISR2H, 0x00000000); + + out_be32((u32 *) GPIO0_ISR3L, 0x00000000); + out_be32((u32 *) GPIO0_ISR3H, 0x00000000); + out_be32((u32 *) GPIO1_ISR3L, 0x00000000); + out_be32((u32 *) GPIO1_ISR3H, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ + mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + + /* take sim card reader and CF controller out of reset */ + out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80); + + /* Configure the two Ethernet PHYs. For each PHY, configure for fiber + * if the SFP module is present, and for copper if it is not present. + */ + gpio0_ir = in_be32((u32 *) GPIO0_IR); + for (eth = 0; eth < 2; ++eth) { + if (gpio0_ir & (0x00000001 << (1 - eth))) { + /* SFP module not present: configure PHY for copper. */ + /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ + out_8((u8 *) CFG_CPLD_BASE + 0x06, + in_8((u8 *) CFG_CPLD_BASE + 0x06) | + 0x06 << (4 * eth)); + } else { + /* SFP module present: configure PHY for fiber and + enable output */ + out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) | + (0x00000001 << (4 - eth))); + out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) & + ~(0x00000001 << (31 - eth))); + } + } + /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ + out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000); + + /* select Ethernet pins */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | + SDR0_PFC1_SELECT_CONFIG_4; + mfsdr(SDR0_PFC2, sdr0_pfc2); + sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | + SDR0_PFC2_SELECT_CONFIG_4; + mtsdr(SDR0_PFC2, sdr0_pfc2); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + /* PCI arbiter enabled */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); + + return 0; +} + +static int man_data_read(unsigned int addr) +{ + /* + * Read an octet of data from address "addr" in the manufacturer's + * information serial EEPROM, or -1 on error. + */ + u8 data[2]; + + if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) || + 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) { + debug("man_data_read(0x%02X) failed\n", addr); + return -1; + } + debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]); + return data[0]; +} + +static unsigned int man_data_field_addr(unsigned int const field) +{ + /* + * The manufacturer's information serial EEPROM contains a sequence of + * zero-delimited fields. Return the starting address of field "field", + * or 0 on error. + */ + unsigned addr, i; + + if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1)) + /* Only format "A" is currently supported */ + return 0; + + for (addr = 2, i = 1; i < field && addr < 256; ++addr) { + if ('\0' == man_data_read(addr)) + ++i; + } + return (addr < 256) ? addr : 0; +} + +static char *man_data_read_field(char s[], unsigned const field, + unsigned const length) +{ + /* + * Place the null-terminated contents of field "field" of length + * "length" from the manufacturer's information serial EEPROM into + * string "s[length + 1]" and return a pointer to s, or return 0 on + * error. In either case the original contents of s[] is not preserved. + */ + unsigned addr, i; + + addr = man_data_field_addr(field); + if (0 == addr || addr + length >= 255) + return 0; + + for (i = 0; i < length; ++i) { + int const c = man_data_read(addr++); + + if (c <= 0) + return 0; + + s[i] = (char)c; + } + if (0 != man_data_read(addr)) + return 0; + + s[i] = '\0'; + return s; +} + +static void set_serial_number(void) +{ + /* + * If the environmental variable "serial#" is not set, try to set it + * from the manufacturer's information serial EEPROM. + */ + char s[MAN_SERIAL_NO_LENGTH + 1]; + + if (0 == getenv("serial#") && + 0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD, + MAN_SERIAL_NO_LENGTH)) + setenv("serial#", s); +} + +static void set_mac_addresses(void) +{ + /* + * If the environmental variables "ethaddr" and/or "eth1addr" are not + * set, try to set them from the manufacturer's information serial + * EEPROM. + */ + char s[MAN_MAC_ADDR_LENGTH + 1]; + + if (0 != getenv("ethaddr") && 0 != getenv("eth1addr")) + return; + + if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD, + MAN_MAC_ADDR_LENGTH)) + return; + + if (0 == getenv("ethaddr")) + setenv("ethaddr", s); + + if (0 == getenv("eth1addr")) { + ++s[MAN_MAC_ADDR_LENGTH - 1]; + setenv("eth1addr", s); + } +} + +/*---------------------------------------------------------------------------+ + | misc_init_r. + +---------------------------------------------------------------------------*/ +int misc_init_r(void) +{ + uint pbcr; + int size_val = 0; + u32 reg; + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1; + char *act = getenv("usbact"); + + /* + * FLASH stuff... + */ + + /* Re-do sizing to get full correct info */ + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, pbcr); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, 0); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + /* + * USB suff... + */ + if (act == NULL || strcmp(act, "hostdev") == 0) { + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */ + + /* An 8-bit/60MHz interface is the only possible alternative + when connecting the Device to the PHY */ + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */ + + /* To enable the USB 2.0 Device function through the UTMI interface */ + usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */ + + sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */ + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /*clear resets */ + udelay(1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Host(int phy) Device(ext phy)\n"); + + } else if (strcmp(act, "dev") == 0) { + /*-------------------PATCH-------------------------------*/ + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */ + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + + udelay(1000); + mtsdr(SDR0_SRST1, 0x672c6000); + + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000080); + + udelay(1000); + mtsdr(SDR0_SRST1, 0x60206000); + + *(unsigned int *)(0xe0000350) = 0x00000001; + + udelay(1000); + mtsdr(SDR0_SRST1, 0x60306000); + /*-------------------PATCH-------------------------------*/ + + /* SDR Setting */ + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_PFC1, sdr0_pfc1); + + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0 */ + + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0 */ + + usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0 */ + + sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1 */ + + mtsdr(SDR0_USB2H0CR, usb2h0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + /*clear resets */ + udelay(1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Device(int phy)\n"); + } + + mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ + reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); + mtsdr(SDR0_SRST1, reg); + + /* + * Clear PLB4A0_ACR[WRP] + * This fix will make the MAL burst disabling patch for the Linux + * EMAC driver obsolete. + */ + reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; + mtdcr(plb4_acr, reg); + + set_serial_number(); + set_mac_addresses(); + return 0; +} + +int checkboard(void) +{ + char const *const s = getenv("serial#"); + u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0); + u32 const gpio0_or = in_be32((u32 *) GPIO0_OR); + + printf("Board: Korat, Rev. %X", rev); + if (s != NULL) + printf(", serial# %s", s); + + printf(", Ethernet PHY 0: "); + if (gpio0_or & 0x00000010) + printf("fiber"); + else + printf("copper"); + + printf(", PHY 1: "); + if (gpio0_or & 0x00000008) + printf("fiber"); + else + printf("copper"); + + printf(".\n"); + return (0); +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + /* TODO: find correct size of SDRAM */ + for (k = 0; k < CFG_MBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) + printf("%3d MB\r", k / 1024); + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif /* defined(CFG_DRAM_TEST) */ + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440EPX PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers for on-board NEC uPD720101 USB controller + *--------------------------------------------------------------------------*/ + pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Korat is always configured as host. */ + return (1); +} +#endif + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif diff --git a/board/korat/u-boot.lds b/board/korat/u-boot.lds new file mode 100644 index 0000000000..a423f98285 --- /dev/null +++ b/board/korat/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/lwmon5/sdram.h b/board/lwmon5/sdram.h index 7f847aa2ad..6a7bf01efb 100644 --- a/board/lwmon5/sdram.h +++ b/board/lwmon5/sdram.h @@ -395,8 +395,8 @@ #define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) #define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) #define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) #define DDR0_27 0x1B #define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 3b3c8ed26d..64dfe0930c 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -35,8 +35,7 @@ long int fixed_sdram (void); int board_pre_init (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -68,14 +67,13 @@ long int initdram (int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) @@ -138,8 +136,7 @@ long int initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -222,8 +219,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile new file mode 100644 index 0000000000..6dec0136c2 --- /dev/null +++ b/board/ms7722se/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/ms7722se/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := ms7722se.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ms7722se/config.mk b/board/ms7722se/config.mk new file mode 100644 index 0000000000..4797d6f8f6 --- /dev/null +++ b/board/ms7722se/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/ms7722se/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S new file mode 100644 index 0000000000..2024e27ffe --- /dev/null +++ b/board/ms7722se/lowlevel_init.S @@ -0,0 +1,294 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/ms7722se/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 ! Address of Cache Control Register + mov.l CCR_D, r0 ! Instruction Cache Invalidate + mov.l r0, @r1 + + mov.l MMUCR_A, r1 ! Address of MMU Control Register + mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit + mov.l r0, @r1 + + mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 + mov.l MSTPCR0_D, r0 ! + mov.l r0, @r1 + + mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 + mov.l MSTPCR2_D, r0 ! + mov.l r0, @r1 + + mov.l SBSCR_A, r1 ! + mov.w SBSCR_D, r0 ! + mov.w r0, @r1 + + mov.l PSCR_A, r1 ! + mov.w PSCR_D, r0 ! + mov.w r0, @r1 + +! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) +! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max +! mov.w r0, @r1 + + mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) + mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) + mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms + mov.w r0, @r1 + + mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register + mov.l FRQCR_D, r0 ! + mov.l r0, @r1 + + mov.l CCR_A, r1 ! Address of Cache Control Register + mov.l CCR_D_2, r0 ! ?? + mov.l r0, @r1 + +bsc_init: + + mov.l PSELA_A, r1 + mov.w PSELA_D, r0 + mov.w r0, @r1 + + mov.l DRVCR_A, r1 + mov.w DRVCR_D, r0 + mov.w r0, @r1 + + mov.l PCCR_A, r1 + mov.w PCCR_D, r0 + mov.w r0, @r1 + + mov.l PECR_A, r1 + mov.w PECR_D, r0 + mov.w r0, @r1 + + mov.l PJCR_A, r1 + mov.w PJCR_D, r0 + mov.w r0, @r1 + + mov.l PXCR_A, r1 + mov.w PXCR_D, r0 + mov.w r0, @r1 + + mov.l CMNCR_A, r1 ! CMNCR address -> R1 + mov.l CMNCR_D, r0 ! CMNCR data -> R0 + mov.l r0, @r1 ! CMNCR set + + mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 + mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 + mov.l r0, @r1 ! CS0BCR set + + mov.l CS2BCR_A, r1 ! CS2BCR address -> R1 + mov.l CS2BCR_D, r0 ! CS2BCR data -> R0 + mov.l r0, @r1 ! CS2BCR set + + mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 + mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 + mov.l r0, @r1 ! CS4BCR set + + mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 + mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 + mov.l r0, @r1 ! CS5ABCR set + + mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 + mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 + mov.l r0, @r1 ! CS5BBCR set + + mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 + mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 + mov.l r0, @r1 ! CS6ABCR set + + mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 + mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 + mov.l r0, @r1 ! CS0WCR set + + mov.l CS2WCR_A, r1 ! CS2WCR address -> R1 + mov.l CS2WCR_D, r0 ! CS2WCR data -> R0 + mov.l r0, @r1 ! CS2WCR set + + mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 + mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 + mov.l r0, @r1 ! CS4WCR set + + mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 + mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 + mov.l r0, @r1 ! CS5AWCR set + + mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 + mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 + mov.l r0, @r1 ! CS5BWCR set + + mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 + mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 + mov.l r0, @r1 ! CS6AWCR set + + ! SDRAM initialization + mov.l SDCR_A, r1 ! SB_SDCR address -> R1 + mov.l SDCR_D, r0 ! SB_SDCR data -> R0 + mov.l r0, @r1 ! SB_SDCR set + + mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 + mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 + mov.l r0, @r1 ! SB_SDWCR set + + mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 + mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 + mov.l r0, @r1 ! SB_SDPCR set + + mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 + mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 + mov.l r0, @r1 ! SB_RTCOR set + + mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 + mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 + mov.l r0, @r1 ! SB_RTCSR set + + mov.l SDMR3_A, r1 ! SDMR3 address -> R1 + mov #0x00, r0 ! SDMR3 data -> R0 + mov.b r0, @r1 ! SDMR3 set + + ! BL bit off (init = ON) (?!?) + + stc sr, r0 ! BL bit off(init=ON) + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + mov #0, r0 + + .align 2 + +CCR_A: .long CCR +MMUCR_A: .long MMUCR +MSTPCR0_A: .long MSTPCR0 +MSTPCR2_A: .long MSTPCR2 +SBSCR_A: .long SBSCR +PSCR_A: .long PSCR +RWTCSR_A: .long RWTCSR +RWTCNT_A: .long RWTCNT +FRQCR_A: .long FRQCR + +CCR_D: .long 0x00000800 +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff +FRQCR_D: .long 0x07022538 + +PSELA_A: .long 0xa405014E +PSELA_D: .word 0x0A10 + .align 2 + +DRVCR_A: .long 0xa405018A +DRVCR_D: .word 0x0554 + .align 2 + +PCCR_A: .long 0xa4050104 +PCCR_D: .word 0x8800 + .align 2 + +PECR_A: .long 0xa4050108 +PECR_D: .word 0x0000 + .align 2 + +PJCR_A: .long 0xa4050110 +PJCR_D: .word 0x1000 + .align 2 + +PXCR_A: .long 0xa4050148 +PXCR_D: .word 0x0AAA + .align 2 + +CMNCR_A: .long CMNCR +CMNCR_D: .long 0x00000013 +CS0BCR_A: .long CS0BCR ! Flash bank 1 +CS0BCR_D: .long 0x24920400 +CS2BCR_A: .long CS2BCR ! SRAM +CS2BCR_D: .long 0x24920400 +CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot +CS4BCR_D: .long 0x24920400 +CS5ABCR_A: .long CS5ABCR ! Ext slot +CS5ABCR_D: .long 0x24920400 +CS5BBCR_A: .long CS5BBCR ! USB controller +CS5BBCR_D: .long 0x24920400 +CS6ABCR_A: .long CS6ABCR ! Ethernet +CS6ABCR_D: .long 0x24920400 + +CS0WCR_A: .long CS0WCR +CS0WCR_D: .long 0x00000300 +CS2WCR_A: .long CS2WCR +CS2WCR_D: .long 0x00000300 +CS4WCR_A: .long CS4WCR +CS4WCR_D: .long 0x00000300 +CS5AWCR_A: .long CS5AWCR +CS5AWCR_D: .long 0x00000300 +CS5BWCR_A: .long CS5BWCR +CS5BWCR_D: .long 0x00000300 +CS6AWCR_A: .long CS6AWCR +CS6AWCR_D: .long 0x00000300 + +SDCR_A: .long SBSC_SDCR +SDCR_D: .long 0x00020809 +SDWCR_A: .long SBSC_SDWCR +SDWCR_D: .long 0x00164d0d +SDPCR_A: .long SBSC_SDPCR +SDPCR_D: .long 0x00000087 +RTCOR_A: .long SBSC_RTCOR +RTCOR_D: .long 0xA55A0034 +RTCSR_A: .long SBSC_RTCSR +RTCSR_D: .long 0xA55A0010 +SDMR3_A: .long 0xFE500180 + + .align 1 + +SBSCR_D: .word 0x0040 +PSCR_D: .word 0x0000 +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA507 +RWTCNT_D: .word 0x5A00 + +SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c new file mode 100644 index 0000000000..0d3d55cf5c --- /dev/null +++ b/board/ms7722se/ms7722se.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/ms7722se/ms7722se.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> + +#define LED_BASE 0xB0800000 + +int checkboard(void) +{ + puts("BOARD: Hitachi UL MS7722SE\n"); + return 0; +} + +int board_init(void) +{ + /* Setup PTXMD[1:0] for /CS6A */ + outw(inw(PXCR) & ~0xf000, PXCR); + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state (unsigned short value) +{ + *((volatile unsigned short *) LED_BASE) = (value & 0xFF); +} diff --git a/board/ms7722se/u-boot.lds b/board/ms7722se/u-boot.lds new file mode 100644 index 0000000000..692bc62918 --- /dev/null +++ b/board/ms7722se/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile new file mode 100644 index 0000000000..f81d56cb44 --- /dev/null +++ b/board/ms7750se/Makefile @@ -0,0 +1,43 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := ms7750se.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +################################################################# + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +################################################################# diff --git a/board/ms7750se/config.mk b/board/ms7750se/config.mk new file mode 100644 index 0000000000..1eed5802e1 --- /dev/null +++ b/board/ms7750se/config.mk @@ -0,0 +1,23 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# +TEXT_BASE = 0x8FFC0000 diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S new file mode 100644 index 0000000000..d3e3cd5e8d --- /dev/null +++ b/board/ms7750se/lowlevel_init.S @@ -0,0 +1,179 @@ +/* + modified from SH-IPL+g + Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. + + Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R + + Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org> + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA +*/ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> + +#ifdef CONFIG_CPU_SH7751 +#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ +#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ +#ifdef CONFIG_MARUBUN_PCCARD +#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#else /* CONFIG_MARUBUN_PCCARD */ +#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#endif /* CONFIG_MARUBUN_PCCARD */ +#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ +#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ +#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */ +#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ +#else /* CONFIG_CPU_SH7751 */ +#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ +#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ +#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:15 A0B:7 */ +#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ +#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ +#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */ +#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ +#endif /* CONFIG_CPU_SH7751 */ + + .global lowlevel_init + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 ! CCR Address + mov.l CCR_D_DISABLE, r0 ! CCR Data + mov.l r0, @r1 + +init_bsc: + mov.l FRQCR_A,r1 /* FRQCR Address */ + mov.l FRQCR_D,r0 /* FRQCR Data */ + mov.w r0,@r1 + + mov.l BCR1_A,r1 /* BCR1 Address */ + mov.l BCR1_D,r0 /* BCR1 Data */ + mov.l r0,@r1 + + mov.l BCR2_A,r1 /* BCR2 Address */ + mov.l BCR2_D,r0 /* BCR2 Data */ + mov.w r0,@r1 + + mov.l WCR1_A,r1 /* WCR1 Address */ + mov.l WCR1_D,r0 /* WCR1 Data */ + mov.l r0,@r1 + + mov.l WCR2_A,r1 /* WCR2 Address */ + mov.l WCR2_D,r0 /* WCR2 Data */ + mov.l r0,@r1 + + mov.l WCR3_A,r1 /* WCR3 Address */ + mov.l WCR3_D,r0 /* WCR3 Data */ + mov.l r0,@r1 + + mov.l MCR_A,r1 /* MCR Address */ + mov.l MCR_D1,r0 /* MCR Data1 */ + mov.l r0,@r1 + + mov.l SDMR3_A,r1 /* Set SDRAM mode */ + mov #0,r0 + mov.b r0,@r1 + + ! Do you need PCMCIA setting? + ! If so, please add the lines here... + + mov.l RTCNT_A,r1 /* RTCNT Address */ + mov.l RTCNT_D,r0 /* RTCNT Data */ + mov.w r0,@r1 + + mov.l RTCOR_A,r1 /* RTCOR Address */ + mov.l RTCOR_D,r0 /* RTCOR Data */ + mov.w r0,@r1 + + mov.l RTCSR_A,r1 /* RTCSR Address */ + mov.l RTCSR_D,r0 /* RTCSR Data */ + mov.w r0,@r1 + + mov.l RFCR_A,r1 /* RFCR Address */ + mov.l RFCR_D,r0 /* RFCR Data */ + mov.w r0,@r1 /* Clear reflesh counter */ + /* Wait DRAM refresh 30 times */ + mov #30,r3 +1: + mov.w @r1,r0 + extu.w r0,r2 + cmp/hi r3,r2 + bf 1b + + mov.l MCR_A,r1 /* MCR Address */ + mov.l MCR_D2,r0 /* MCR Data2 */ + mov.l r0,@r1 + + mov.l SDMR3_A,r1 /* Set SDRAM mode */ + mov #0,r0 + mov.b r0,@r1 + + rts + nop + + .align 2 + +CCR_A: .long CCR +CCR_D_DISABLE: .long 0x0808 +FRQCR_A: .long FRQCR +FRQCR_D: +#ifdef CONFIG_CPU_TYPE_R + .long 0x00000e1a /* 12:3:3 */ +#else /* CONFIG_CPU_TYPE_R */ +#ifdef CONFIG_GOOD_SESH4 + .long 0x00000e13 /* 6:2:1 */ +#else + .long 0x00000e23 /* 6:1:1 */ +#endif +#endif /* CONFIG_CPU_TYPE_R */ + +BCR1_A: .long BCR1 +BCR1_D: .long 0x00000008 /* Area 3 SDRAM */ +BCR2_A: .long BCR2 +BCR2_D: .long BCR2_D_VALUE /* Bus width settings */ +WCR1_A: .long WCR1 +WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ +WCR2_A: .long WCR2 +WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ +WCR3_A: .long WCR3 +WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ +RTCSR_A: .long RTCSR +RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ +RTCNT_A: .long RTCNT +RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCOR_A: .long RTCOR +RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ +SDMR3_A: .long SDMR3_ADDRESS +MCR_A: .long MCR +MCR_D1: .long MCR_D1_VALUE +MCR_D2: .long MCR_D2_VALUE +RFCR_A: .long RFCR +RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ diff --git a/board/mpc8568mds/ft_board.c b/board/ms7750se/ms7750se.c index 36815ccfbb..d2d824c5a7 100644 --- a/board/mpc8568mds/ft_board.c +++ b/board/ms7750se/ms7750se.c @@ -1,5 +1,6 @@ /* - * Copyright 2004-2007 Freescale Semiconductor. + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * See file CREDITS for list of people who contributed to this * project. @@ -11,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -21,25 +22,30 @@ */ #include <common.h> +#include <asm/processor.h> -#include <ft_build.h> +int checkboard(void) +{ + puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; -extern void ft_cpu_setup(void *blob, bd_t *bd); + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int board_late_init(void) { - u32 *p; - int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } + return 0; } -#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */ diff --git a/board/ms7750se/u-boot.lds b/board/ms7750se/u-boot.lds new file mode 100644 index 0000000000..692bc62918 --- /dev/null +++ b/board/ms7750se/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 6ead1d0630..999d8b5259 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -45,8 +45,7 @@ long int fixed_sdram(void); int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -79,13 +78,12 @@ initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); int i,x; x = 10; @@ -133,9 +131,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -229,8 +226,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index a10075451e..bfde6959b4 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -232,13 +232,12 @@ initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); int i,x; x = 10; @@ -287,9 +286,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -382,8 +380,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index e8b9929e77..47df884ce5 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -195,8 +195,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xfffffffdf; /* disable master abort */ #endif @@ -264,16 +263,15 @@ long int initdram (int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; #if 0 #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #endif /* 0 */ #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; @@ -336,8 +334,7 @@ long int initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -424,8 +421,7 @@ long int fixed_sdram (void) #define CFG_DDR_CONTROL 0xc2000000 #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = 0x00000007; ddr->cs1_bnds = 0x0010001f; diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index a58c043b62..3649acf07d 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -203,8 +203,7 @@ int board_early_init_f(void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xfffffffdf; /* disable master abort */ #endif @@ -283,11 +282,10 @@ initdram (int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 9bacb98d86..e2b38a6205 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -252,8 +252,7 @@ int board_early_init_f(void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -302,8 +301,7 @@ initdram (int board_type) #if defined(CONFIG_DDR_DLL) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c index 9c1f087687..2053adefb4 100644 --- a/board/tqm85xx/sdram.c +++ b/board/tqm85xx/sdram.c @@ -57,8 +57,7 @@ int cas_latency(void); long int sdram_setup(int casl) { int i; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr; + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); unsigned long cfg_ddr_timing1; unsigned long cfg_ddr_mode; @@ -150,8 +149,7 @@ long int initdram (int board_type) * This DLL-Override only used on TQM8540 and TQM8560 */ { - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); int i,x; x = 10; diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index 256c076c7d..5d5cb1b75c 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -262,8 +262,7 @@ int checkboard (void) int misc_init_r (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); /* * Adjust flash start and offset to detected values @@ -324,9 +323,8 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c index db0a7e5eb8..4342ebc841 100644 --- a/board/tqm8xx/flash.c +++ b/board/tqm8xx/flash.c @@ -33,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; +#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */ + #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ && !defined(CONFIG_TQM885D) # ifndef CFG_OR_TIMING_FLASH_AT_50MHZ @@ -828,3 +830,5 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /*----------------------------------------------------------------------- */ + +#endif /* !defined(CFG_FLASH_CFI_DRIVER) */ diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index cebdcc0764..fcd941e0d2 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -37,6 +37,7 @@ static long int dram_size (long int, long int *, long int); #define _NOT_USED_ 0xFFFFFFFF +/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */ const uint sdram_table[] = { /* @@ -63,14 +64,14 @@ const uint sdram_table[] = /* * Single Write. (Offset 18 in UPMA RAM) */ - 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44, + 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Write. (Offset 20 in UPMA RAM) */ 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, + 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* @@ -83,7 +84,7 @@ const uint sdram_table[] = /* * Exception. (Offset 3c in UPMA RAM) */ - 0x7FFFFC07, /* last */ + 0xFFFFFC07, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, }; @@ -183,7 +184,7 @@ long int initdram (int board_type) #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && (board_type != 'M') && - (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */ + (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ memctl->memc_or3 = CFG_OR3_PRELIM; memctl->memc_br3 = CFG_BR3_PRELIM; } @@ -259,7 +260,7 @@ long int initdram (int board_type) #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && (board_type != 'M') && - (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */ + (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ /* * Check Bank 1 Memory Size * use current column settings diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index d8163494e8..9546729294 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -260,6 +260,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (hdr->ih_arch != IH_CPU_NIOS2) #elif defined(__PPC__) if (hdr->ih_arch != IH_CPU_PPC) +#elif defined(__sh__) + if (hdr->ih_arch != IH_CPU_SH) #else # error Unknown CPU type #endif diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 821dcff9bf..c38be4f1a7 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -886,7 +886,7 @@ input_swap_data(int dev, ulong *sect_buf, int words) #endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH) static void output_data(int dev, ulong *sect_buf, int words) { @@ -938,7 +938,7 @@ output_data(int dev, ulong *sect_buf, int words) } #endif /* __PPC__ */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH) static void input_data(int dev, ulong *sect_buf, int words) { diff --git a/cpu/at32ap/at32ap7000/Makefile b/cpu/at32ap/at32ap700x/Makefile index d276712118..d276712118 100644 --- a/cpu/at32ap/at32ap7000/Makefile +++ b/cpu/at32ap/at32ap700x/Makefile diff --git a/cpu/at32ap/at32ap7000/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 52f5372a60..859124a91f 100644 --- a/cpu/at32ap/at32ap7000/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -21,6 +21,7 @@ */ #include <common.h> +#include <asm/arch/chip-features.h> #include <asm/arch/gpio.h> /* @@ -52,6 +53,7 @@ void gpio_enable_ebi(void) #endif } +#ifdef AT32AP700x_CHIP_HAS_USART void gpio_enable_usart0(void) { gpio_select_periph_B(GPIO_PIN_PA8, 0); @@ -72,10 +74,12 @@ void gpio_enable_usart2(void) void gpio_enable_usart3(void) { + gpio_select_periph_B(GPIO_PIN_PB17, 0); gpio_select_periph_B(GPIO_PIN_PB18, 0); - gpio_select_periph_B(GPIO_PIN_PB19, 0); } +#endif +#ifdef AT32AP700x_CHIP_HAS_MACB void gpio_enable_macb0(void) { gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ @@ -125,7 +129,9 @@ void gpio_enable_macb1(void) gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */ #endif } +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI void gpio_enable_mmci(void) { gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */ @@ -135,3 +141,4 @@ void gpio_enable_mmci(void) gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */ gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ } +#endif diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c index cf48be10ba..f59dfb5995 100644 --- a/cpu/at32ap/atmel_mci.c +++ b/cpu/at32ap/atmel_mci.c @@ -198,11 +198,11 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, /* Put the device into Transfer state */ ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); - if (ret) goto fail; + if (ret) goto out; /* Set block length */ ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); - if (ret) goto fail; + if (ret) goto out; pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); @@ -211,7 +211,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, start * mmc_blkdev.blksz, resp, (R1 | NCR | TRCMD_START | TRDIR_READ | TRTYP_BLOCK)); - if (ret) goto fail; + if (ret) goto out; ret = -EIO; wordcount = 0; @@ -219,7 +219,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, do { status = mmci_readl(SR); if (status & (ERROR_FLAGS | MMCI_BIT(OVRE))) - goto fail; + goto read_error; } while (!(status & MMCI_BIT(RXRDY))); if (status & MMCI_BIT(RXRDY)) { @@ -244,9 +244,10 @@ out: mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); return i; -fail: +read_error: mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); - printf("mmc: bread failed, card status = %08x\n", card_status); + printf("mmc: bread failed, status = %08x, card status = %08x\n", + status, card_status); goto out; } diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 32091fa4e1..d179d701bd 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -29,8 +29,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o resetvec.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o + pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \ + $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c index 3504d50cae..b0ecd25507 100644 --- a/cpu/mpc85xx/commproc.c +++ b/cpu/mpc85xx/commproc.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; void m8560_cpm_reset(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile ulong count; gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); @@ -50,11 +50,11 @@ m8560_cpm_reset(void) /* * Reset CPM */ - immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST; + cpm->im_cpm_cp.cpcr = CPM_CR_RST; count = 0; do { /* Spin until command processed */ __asm__ __volatile__ ("eieio"); - } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); + } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); } /* Allocate some memory from the dual ported ram. @@ -64,7 +64,7 @@ m8560_cpm_reset(void) uint m8560_cpm_dpalloc(uint size, uint align) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; uint retloc; uint align_mask, off; uint savebase; @@ -86,7 +86,7 @@ m8560_cpm_dpalloc(uint size, uint align) retloc = gd->dp_alloc_base; gd->dp_alloc_base += size; - memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size); + memset((void *)&(cpm->im_dprambase[retloc]), 0, size); return(retloc); } @@ -120,16 +120,16 @@ m8560_cpm_hostalloc(uint size, uint align) void m8560_cpm_setbrg(uint brg, uint rate) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile uint *bp; /* This is good enough to get SMCs running..... */ if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); } else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); brg -= 4; } bp += brg; @@ -142,16 +142,16 @@ m8560_cpm_setbrg(uint brg, uint rate) void m8560_cpm_fastbrg(uint brg, uint rate, int div16) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile uint *bp; /* This is good enough to get SMCs running..... */ if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); } else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); brg -= 4; } bp += brg; @@ -167,14 +167,14 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16) void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile uint *bp; if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); } else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); brg -= 4; } bp += brg; diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bbc54448da..ac8b018b0a 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -30,11 +30,6 @@ #include <command.h> #include <asm/cache.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif - - int checkcpu (void) { sys_info_t sysinfo; @@ -44,6 +39,8 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; + u32 ddr_ratio; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); svr = get_svr(); ver = SVR_VER(svr); @@ -107,14 +104,25 @@ int checkcpu (void) puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000); - printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); + + ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + switch (ddr_ratio) { + case 0x0: + printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000); + break; + case 0x7: + printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000); + break; + default: + printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000); + break; + } #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } @@ -214,8 +222,7 @@ reset_85xx_watchdog(void) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; + volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; @@ -225,8 +232,7 @@ void dma_init(void) { } uint dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; + volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); volatile uint status = dma->sr0; /* While the channel is busy, spin */ @@ -245,8 +251,7 @@ uint dma_check(void) { } int dma_xfer(void *dest, uint count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; + volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); dma->dar0 = (uint) dest; dma->sar0 = (uint) src; @@ -258,94 +263,3 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif - - -#ifdef CONFIG_OF_FLAT_TREE -void -ft_cpu_setup(void *blob, bd_t *bd) -{ - u32 *p; - ulong clock; - int len; - - clock = bd->bi_busfreq; - p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - -#if defined(CONFIG_HAS_ETH0) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enetaddr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enetaddr, 6); -#endif - -#if defined(CONFIG_HAS_ETH1) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet1addr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet1addr, 6); -#endif - -#if defined(CONFIG_HAS_ETH2) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet2addr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet2addr, 6); - -#ifdef CONFIG_UEC_ETH - p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet2addr, 6); - - p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet2addr, 6); - -#endif -#endif - -#if defined(CONFIG_HAS_ETH3) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet3addr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet3addr, 6); - -#ifdef CONFIG_UEC_ETH - p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet3addr, 6); - - p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet3addr, 6); - -#endif -#endif - -} -#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 79ad20c91a..fdb9ecbd50 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -59,7 +59,7 @@ static void config_qe_ioports(void) #endif #ifdef CONFIG_CPM2 -static void config_8560_ioports (volatile immap_t * immr) +void config_8560_ioports (volatile ccsr_cpm_t * cpm) { int portnum; @@ -99,7 +99,7 @@ static void config_8560_ioports (volatile immap_t * immr) } if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (immr, portnum); + volatile ioport_t *iop = ioport_addr (cpm, portnum); uint tpmsk = ~pmsk; /* @@ -131,8 +131,7 @@ static void config_8560_ioports (volatile immap_t * immr) void cpu_init_f (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); /* Pointer is writable since we allocated a register for it */ @@ -143,7 +142,7 @@ void cpu_init_f (void) #ifdef CONFIG_CPM2 - config_8560_ioports(immap); + config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); #endif /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary @@ -222,18 +221,15 @@ void cpu_init_f (void) int cpu_init_r(void) { -#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE) - volatile immap_t *immap = (immap_t *)CFG_IMMR; -#endif #ifdef CONFIG_CLEAR_LAW0 - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); /* clear alternate boot location LAW (used for sdram, or ddr bank) */ ecm->lawar0 = 0; #endif #if defined(CONFIG_L2_CACHE) - volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; + volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint svr, ver; uint l2srbar; diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index 5b23a80e1c..bd62aab9f3 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -230,8 +230,8 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { struct ether_fcc_info_s * info = dev->priv; int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp); + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); fcc_enet_t *pram_ptr; unsigned long mem_addr; @@ -242,35 +242,35 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (1-2): ioports have been set up already */ /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */ - immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | + cpm->im_cpm_mux.cmxuar = 0; /* ATM */ + cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | info->cmxfcr_value; /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 1){ - immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 2){ - immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } /* 28.9 - (6): FDSR: Ethernet Syn */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555; + cpm->im_cpm_fcc1.fdsr = 0xD555; } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555; + cpm->im_cpm_fcc2.fdsr = 0xD555; } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555; + cpm->im_cpm_fcc3.fdsr = 0xD555; } /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ @@ -296,7 +296,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; /* 28.9 - (7): initialize parameter ram */ - pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]); + pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); /* clear whole structure to make sure all reserved fields are zero */ memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); @@ -385,14 +385,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (8)(9): clear out events in FCCE */ /* 28.9 - (9): FCCM: mask all events */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc1.fccm = 0; + cpm->im_cpm_fcc1.fcce = ~0x0; + cpm->im_cpm_fcc1.fccm = 0; } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc2.fccm = 0; + cpm->im_cpm_fcc2.fcce = ~0x0; + cpm->im_cpm_fcc2.fccm = 0; } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc3.fccm = 0; + cpm->im_cpm_fcc3.fcce = ~0x0; + cpm->im_cpm_fcc3.fccm = 0; } /* 28.9 - (10-12): we don't use ethernet interrupts */ @@ -413,11 +413,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (14): enable tx/rx in gfmr */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } return 1; @@ -426,15 +426,15 @@ static int fec_init(struct eth_device* dev, bd_t *bis) static void fec_halt(struct eth_device* dev) { struct ether_fcc_info_s * info = dev->priv; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; /* write GFMR: disable tx/rx */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } else if(info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } else if(info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c new file mode 100644 index 0000000000..737a6c485a --- /dev/null +++ b/cpu/mpc85xx/fdt.c @@ -0,0 +1,64 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +void ft_cpu_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + fdt_fixup_ethernet(blob, bd); +#endif + + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", bd->bi_busfreq / 8, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); +#ifdef CONFIG_QE + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); +#endif + +#ifdef CFG_NS16550 + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", bd->bi_busfreq, 1); +#endif + +#ifdef CONFIG_CPM2 + do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", + "current-speed", bd->bi_baudrate, 1); + + do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", + "clock-frequency", bd->bi_brgfreq, 1); +#endif + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index bf737d6228..18e5377b32 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -80,19 +80,17 @@ int disable_interrupts (void) int interrupt_init (void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); - immr->im_pic.gcr = MPC85xx_PICGCR_RST; - while (immr->im_pic.gcr & MPC85xx_PICGCR_RST); - immr->im_pic.gcr = MPC85xx_PICGCR_M; + pic->gcr = MPC85xx_PICGCR_RST; + while (pic->gcr & MPC85xx_PICGCR_RST); + pic->gcr = MPC85xx_PICGCR_M; decrementer_count = get_tbclk() / CFG_HZ; mtspr(SPRN_TCR, TCR_PIE); set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); #ifdef CONFIG_INTERRUPTS - volatile ccsr_pic_t *pic = &immr->im_pic; - pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index db09e45fbc..a5060cdec4 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,10 +29,6 @@ #include <asm/cpm_85xx.h> #include <pci.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#endif - #if defined(CONFIG_PCI) static struct pci_controller *pci_hose; @@ -43,12 +39,11 @@ pci_mpc85xx_init(struct pci_controller *board_hose) u16 reg16; u32 dev; - volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; - volatile ccsr_pcix_t *pcix = &immap->im_pcix; + volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR); #ifdef CONFIG_MPC85XX_PCI2 - volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; + volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR); #endif - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); struct pci_controller * hose; pci_hose = board_hose; @@ -216,27 +211,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = pci_hose_scan(hose); #endif } - -#ifdef CONFIG_OF_FLAT_TREE -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; - } - -#ifdef CONFIG_MPC85XX_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; - } -#endif -} -#endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c index 8878bc5319..98075bbe54 100644 --- a/cpu/mpc85xx/qe_io.c +++ b/cpu/mpc85xx/qe_io.c @@ -34,9 +34,9 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) - &(im->im_gur.qe_par_io); + &(gur->qe_par_io); /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c index 4e925f8bea..7ee3cc8234 100644 --- a/cpu/mpc85xx/serial_scc.c +++ b/cpu/mpc85xx/serial_scc.c @@ -88,17 +88,17 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile ccsr_cpm_scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; - volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp); + volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); uint dpaddr; /* initialize pointers to SCC */ - sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]); - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); /* Disable transmitter/receiver. */ @@ -107,8 +107,8 @@ int serial_init (void) /* put the SCC channel into NMSI (non multiplexd serial interface) * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). */ - im->im_cpm.im_cpm_mux.cmxscr = \ - (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; + cpm->im_cpm_mux.cmxscr = \ + (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; /* Set up the baud rate generator. */ @@ -123,7 +123,7 @@ int serial_init (void) /* Set the physical address of the host memory buffers in * the buffer descriptors. */ - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]); + rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]); rbdf->cbd_bufaddr = (uint) (rbdf+2); rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; tbdf = rbdf + 1; @@ -201,14 +201,13 @@ serial_putc(const char c) { volatile scc_uart_t *up; volatile cbd_t *tbdf; - volatile immap_t *im; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; if (c == '\n') serial_putc ('\r'); - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]); /* Wait for last character to go. */ @@ -235,12 +234,11 @@ serial_getc(void) { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile immap_t *im; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; unsigned char c; - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); /* Wait for character to show up. */ @@ -260,11 +258,10 @@ serial_tstc() { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile immap_t *im; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); } diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 5dc223a53e..553f736a56 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -53,8 +53,8 @@ picos_to_clk(int picos) { int clks; - clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); - if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks = picos / (2000000000 / (get_ddr_freq(0) / 1000)); + if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) { clks++; } @@ -171,8 +171,7 @@ unsigned int determine_refresh_rate(unsigned int spd_refresh) long int spd_sdram(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr; + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; @@ -309,7 +308,7 @@ spd_sdram(void) if ((SVR_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrioovcr = (0x80000000 /* Enable */ | 0x10000000);/* VSEL to 1.8V */ } @@ -422,7 +421,7 @@ spd_sdram(void) * Adjust the CAS Latency to allow for bus speeds that * are slower than the DDR module. */ - busfreq = get_bus_freq(0) / 1000000; /* MHz */ + busfreq = get_ddr_freq(0) / 1000000; /* MHz */ effective_data_rate = max_data_rate; if (busfreq < 90) { @@ -1023,8 +1022,7 @@ spd_sdram(void) static unsigned int setup_laws_and_tlbs(unsigned int memsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); unsigned int tlb_size; unsigned int law_size; unsigned int ram_tlb_index; @@ -1130,8 +1128,7 @@ ddr_enable_ecc(unsigned int dram_size) { uint *p = 0; uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 12359a2d64..27de37afa8 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -35,8 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint plat_ratio,e500_ratio,half_freqSystemBus; plat_ratio = (gur->porpllsr) & 0x0000003e; @@ -49,6 +48,15 @@ void get_sys_info (sys_info_t * sysInfo) * overflow for processor speeds above 2GHz */ half_freqSystemBus = sysInfo->freqSystemBus/2; sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; + sysInfo->freqDDRBus = sysInfo->freqSystemBus; + +#ifdef CONFIG_DDR_CLK_FREQ + { + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + if (ddr_ratio != 0x7) + sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; + } +#endif } @@ -56,12 +64,12 @@ int get_clocks (void) { sys_info_t sys_info; #if defined(CONFIG_CPM2) - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; uint sccr, dfbrg; /* set VCO = 4 * BRG */ - immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc; - sccr = immap->im_cpm.im_cpm_intctl.sccr; + cpm->im_cpm_intctl.sccr &= 0xfffffffc; + sccr = cpm->im_cpm_intctl.sccr; dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; #endif get_sys_info (&sys_info); @@ -94,3 +102,19 @@ ulong get_bus_freq (ulong dummy) return val; } + +/******************************************** + * get_ddr_freq + * return ddr bus freq in Hz + *********************************************/ +ulong get_ddr_freq (ulong dummy) +{ + ulong val; + + sys_info_t sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqDDRBus; + + return val; +} diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index efc80c7aee..2381fb0654 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -288,8 +288,8 @@ UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_pic_t *pic = &immap->im_pic; + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + uint vect; #if defined(CONFIG_CMD_KGDB) diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 101d5f9cb3..11b089330b 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -259,11 +259,8 @@ int get_clocks_866 (void) */ sccr_reg = immr->im_clkrst.car_sccr; sccr_reg &= ~SCCR_EBDF11; -#if defined(CONFIG_TQM885D) - if (gd->cpu_clk <= 80000000) { -#else + if (gd->cpu_clk <= 66000000) { -#endif sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ gd->bus_clk = gd->cpu_clk; } else { diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index c20dc730ef..bfe0864d11 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -849,7 +849,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #ifdef CONFIG_4xx_DCACHE - flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE - 1); + flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); bd_uncached = bis->bi_memsize; program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, TLB_WORD2_I_ENABLE); @@ -1064,7 +1064,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); - flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len - 1); + flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); /*-----------------------------------------------------------------------+ * set TX Buffer busy, and send it @@ -1566,7 +1566,7 @@ static int ppc_4xx_eth_rx (struct eth_device *dev) /* NetReceive(NetRxPackets[i], length); */ invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, (u32)hw_p->rx[user_index].data_ptr + - length - 4 - 1); + length - 4); NetReceive (NetRxPackets[user_index], length - 4); /* Free Recv Buffer */ hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 9155e9a98d..178c5c6742 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -43,6 +43,8 @@ COBJS += bedbug_405.o COBJS += commproc.o COBJS += cpu.o COBJS += cpu_init.o +COBJS += denali_data_eye.o +COBJS += denali_spd_ddr2.o COBJS += fdt.o COBJS += gpio.o COBJS += i2c.o diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 01ab523c51..2e0dd6f062 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -136,11 +136,16 @@ cpu_init_f (void) out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ #endif -#if defined (CONFIG_450EP) +#if defined (CONFIG_405EP) /* * Set EMAC noise filter bits */ mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + + /* + * Enable the internal PCI arbiter + */ + mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ #endif /* CONFIG_405EP */ diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c new file mode 100644 index 0000000000..6c949a0fe1 --- /dev/null +++ b/cpu/ppc4xx/denali_data_eye.c @@ -0,0 +1,396 @@ +/* + * cpu/ppc4xx/denali_data_eye.c + * Extracted from board/amcc/sequoia/sdram.c by Larry Johnson <lrj@acm.org>. + * + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include <common.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <ppc4xx.h> + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +/*-----------------------------------------------------------------------------+ + * denali_wait_for_dlllock. + +----------------------------------------------------------------------------*/ +int denali_wait_for_dlllock(void) +{ + u32 val; + int wait; + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + for (wait = 0; wait != 0xffff; ++wait) { + mfsdram(DDR0_17, val); + if (DDR0_17_DLLLOCKREG_DECODE(val)) { + /* dlllockreg bit on */ + return 0; + } + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + return -1; +} + +#if defined(CONFIG_DDR_DATA_EYE) +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +/*-----------------------------------------------------------------------------+ + * wait_for_dram_init_complete. + +----------------------------------------------------------------------------*/ +static int wait_for_dram_init_complete(void) +{ + unsigned long val; + int wait = 0; + + /* --------------------------------------------------------------+ + * Wait for 'DRAM initialization complete' bit in status register + * -------------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_00); + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) + /* 'DRAM initialization complete' bit */ + return 0; + else + wait++; + } + debug("DRAM initialization complete bit in status register did not " + "rise\n"); + return -1; +} + +#define NUM_TRIES 64 +#define NUM_READS 10 + +/*-----------------------------------------------------------------------------+ + * denali_core_search_data_eye. + +----------------------------------------------------------------------------*/ +/* + * Avoid conflict with implementations of denali_core_search_data_eye in board- + * specific code. + */ +void denali_core_search_data_eye(void) + __attribute__ ((weak, alias("__denali_core_search_data_eye"))); + +void __denali_core_search_data_eye(void) +{ + int k, j; + u32 val; + u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; + u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; + u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; + u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; + volatile u32 *ram_pointer; + u32 test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 + }; + + ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE); + + for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { + /* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */ + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | + DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + + passing_cases = 0; + + for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; + dll_dqs_delay_X++) { + /* for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; + dll_dqs_delay_X++) { */ + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* clear any ECC errors */ + mtdcr(ddrcfga, DDR0_00); + mtdcr(ddrcfgd, + mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (denali_wait_for_dlllock() != 0) { + printf("dll lock did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = " + "%d\n", wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + sync(); + eieio(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur!!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = " + "%d\n", wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ + + /* write values */ + for (j = 0; j < NUM_TRIES; j++) { + ram_pointer[j] = test[j]; + + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r"(&ram_pointer[j])); + } + + /* read values back */ + for (j = 0; j < NUM_TRIES; j++) { + for (k = 0; k < NUM_READS; k++) { + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r"(&ram_pointer + [j])); + + if (ram_pointer[j] != test[j]) + break; + } + + /* read error */ + if (k != NUM_READS) + break; + } + + /* See if the dll_dqs_delay_X value passed. */ + mtdcr(ddrcfga, DDR0_00); + if (j < NUM_TRIES + || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & + 0x3F)) { + /* Failed */ + passing_cases = 0; + /* break; */ + } else { + /* Passed */ + if (passing_cases == 0) + dll_dqs_delay_X_sw_val = + dll_dqs_delay_X; + passing_cases++; + if (passing_cases >= max_passing_cases) { + max_passing_cases = passing_cases; + wr_dqs_shift_with_max_passing_cases = + wr_dqs_shift; + dll_dqs_delay_X_start_window = + dll_dqs_delay_X_sw_val; + dll_dqs_delay_X_end_window = + dll_dqs_delay_X; + } + } + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ + } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ + + /* -----------------------------------------------------------+ + * Largest passing window is now detected. + * ----------------------------------------------------------*/ + + /* Compute dll_dqs_delay_X value */ + dll_dqs_delay_X = (dll_dqs_delay_X_end_window + + dll_dqs_delay_X_start_window) / 2; + wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; + + debug("DQS calibration - Window detected:\n"); + debug("max_passing_cases = %d\n", max_passing_cases); + debug("wr_dqs_shift = %d\n", wr_dqs_shift); + debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); + debug("dll_dqs_delay_X window = %d - %d\n", + dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_09=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_22=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_17=0x%08lx\n", val); + + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_18=0x%08lx\n", val); + + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_19=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (denali_wait_for_dlllock() != 0) { + printf("dll lock did not occur !!!\n"); + hang(); + } + sync(); + eieio(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ +} +#endif /* defined(CONFIG_DDR_DATA_EYE) */ +#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c new file mode 100644 index 0000000000..825bc2139c --- /dev/null +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -0,0 +1,1254 @@ +/* + * cpu/ppc4xx/denali_spd_ddr2.c + * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core + * DDR2 controller, specifically the 440EPx/GRx. + * + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org. + * + * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... + * + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * COPYRIGHT AMCC CORPORATION 2004 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include <common.h> +#include <command.h> +#include <ppc4xx.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/mmu.h> + +#if defined(CONFIG_SPD_EEPROM) && \ + (defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) + +/*-----------------------------------------------------------------------------+ + * Defines + *-----------------------------------------------------------------------------*/ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define MAXDIMMS 2 +#define MAXRANKS 2 + +#define ONE_BILLION 1000000000 + +#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) + +#define DLL_DQS_DELAY 0x19 +#define DLL_DQS_BYPASS 0x0B +#define DQS_OUT_SHIFT 0x7F + +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory + * region. Right now the cache should still be disabled in U-Boot because of the + * EMAC driver, that need it's buffer descriptor to be located in non cached + * memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * everything correctly. + */ +#if defined(CFG_ENABLE_SDRAM_CACHE) +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#endif + +/*-----------------------------------------------------------------------------+ + * Prototypes + *-----------------------------------------------------------------------------*/ +extern int denali_wait_for_dlllock(void); +extern void denali_core_search_data_eye(void); +extern void dcbz_area(u32 start_address, u32 num_bytes); +extern void dflush(void); + +/* + * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed + */ +void __spd_ddr_init_hang(void) +{ + hang(); +} +void spd_ddr_init_hang(void) + __attribute__ ((weak, alias("__spd_ddr_init_hang"))); + +#if defined(DEBUG) +static void print_mcsr(void) +{ + printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR)); +} + +static void denali_sdram_register_dump(void) +{ + unsigned int sdram_data; + + printf("\n Register Dump:\n"); + mfsdram(DDR0_00, sdram_data); + printf(" DDR0_00 = 0x%08X", sdram_data); + mfsdram(DDR0_01, sdram_data); + printf(" DDR0_01 = 0x%08X\n", sdram_data); + mfsdram(DDR0_02, sdram_data); + printf(" DDR0_02 = 0x%08X", sdram_data); + mfsdram(DDR0_03, sdram_data); + printf(" DDR0_03 = 0x%08X\n", sdram_data); + mfsdram(DDR0_04, sdram_data); + printf(" DDR0_04 = 0x%08X", sdram_data); + mfsdram(DDR0_05, sdram_data); + printf(" DDR0_05 = 0x%08X\n", sdram_data); + mfsdram(DDR0_06, sdram_data); + printf(" DDR0_06 = 0x%08X", sdram_data); + mfsdram(DDR0_07, sdram_data); + printf(" DDR0_07 = 0x%08X\n", sdram_data); + mfsdram(DDR0_08, sdram_data); + printf(" DDR0_08 = 0x%08X", sdram_data); + mfsdram(DDR0_09, sdram_data); + printf(" DDR0_09 = 0x%08X\n", sdram_data); + mfsdram(DDR0_10, sdram_data); + printf(" DDR0_10 = 0x%08X", sdram_data); + mfsdram(DDR0_11, sdram_data); + printf(" DDR0_11 = 0x%08X\n", sdram_data); + mfsdram(DDR0_12, sdram_data); + printf(" DDR0_12 = 0x%08X", sdram_data); + mfsdram(DDR0_14, sdram_data); + printf(" DDR0_14 = 0x%08X\n", sdram_data); + mfsdram(DDR0_17, sdram_data); + printf(" DDR0_17 = 0x%08X", sdram_data); + mfsdram(DDR0_18, sdram_data); + printf(" DDR0_18 = 0x%08X\n", sdram_data); + mfsdram(DDR0_19, sdram_data); + printf(" DDR0_19 = 0x%08X", sdram_data); + mfsdram(DDR0_20, sdram_data); + printf(" DDR0_20 = 0x%08X\n", sdram_data); + mfsdram(DDR0_21, sdram_data); + printf(" DDR0_21 = 0x%08X", sdram_data); + mfsdram(DDR0_22, sdram_data); + printf(" DDR0_22 = 0x%08X\n", sdram_data); + mfsdram(DDR0_23, sdram_data); + printf(" DDR0_23 = 0x%08X", sdram_data); + mfsdram(DDR0_24, sdram_data); + printf(" DDR0_24 = 0x%08X\n", sdram_data); + mfsdram(DDR0_25, sdram_data); + printf(" DDR0_25 = 0x%08X", sdram_data); + mfsdram(DDR0_26, sdram_data); + printf(" DDR0_26 = 0x%08X\n", sdram_data); + mfsdram(DDR0_27, sdram_data); + printf(" DDR0_27 = 0x%08X", sdram_data); + mfsdram(DDR0_28, sdram_data); + printf(" DDR0_28 = 0x%08X\n", sdram_data); + mfsdram(DDR0_31, sdram_data); + printf(" DDR0_31 = 0x%08X", sdram_data); + mfsdram(DDR0_32, sdram_data); + printf(" DDR0_32 = 0x%08X\n", sdram_data); + mfsdram(DDR0_33, sdram_data); + printf(" DDR0_33 = 0x%08X", sdram_data); + mfsdram(DDR0_34, sdram_data); + printf(" DDR0_34 = 0x%08X\n", sdram_data); + mfsdram(DDR0_35, sdram_data); + printf(" DDR0_35 = 0x%08X", sdram_data); + mfsdram(DDR0_36, sdram_data); + printf(" DDR0_36 = 0x%08X\n", sdram_data); + mfsdram(DDR0_37, sdram_data); + printf(" DDR0_37 = 0x%08X", sdram_data); + mfsdram(DDR0_38, sdram_data); + printf(" DDR0_38 = 0x%08X\n", sdram_data); + mfsdram(DDR0_39, sdram_data); + printf(" DDR0_39 = 0x%08X", sdram_data); + mfsdram(DDR0_40, sdram_data); + printf(" DDR0_40 = 0x%08X\n", sdram_data); + mfsdram(DDR0_41, sdram_data); + printf(" DDR0_41 = 0x%08X", sdram_data); + mfsdram(DDR0_42, sdram_data); + printf(" DDR0_42 = 0x%08X\n", sdram_data); + mfsdram(DDR0_43, sdram_data); + printf(" DDR0_43 = 0x%08X", sdram_data); + mfsdram(DDR0_44, sdram_data); + printf(" DDR0_44 = 0x%08X\n", sdram_data); +} +#else +static inline void denali_sdram_register_dump(void) +{ +} + +inline static void print_mcsr(void) +{ +} +#endif /* defined(DEBUG) */ + +static int is_ecc_enabled(void) +{ + u32 val; + + mfsdram(DDR0_22, val); + return 0x3 == DDR0_22_CTRL_RAW_DECODE(val); +} + +static unsigned char spd_read(u8 chip, unsigned int addr) +{ + u8 data[2]; + + if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) { + debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr); + return 0; + } + debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n", + chip, addr, data[0]); + return data[0]; +} + +static unsigned long get_tcyc(unsigned char reg) +{ + /* + * Byte 9, et al: Cycle time for CAS Latency=X, is split into two + * nibbles: the higher order nibble (bits 4-7) designates the cycle time + * to a granularity of 1ns; the value presented by the lower order + * nibble (bits 0-3) has a granularity of .1ns and is added to the value + * designated by the higher nibble. In addition, four lines of the lower + * order nibble are assigned to support +.25, +.33, +.66, and +.75. + */ + + unsigned char subfield_b = reg & 0x0F; + + switch (subfield_b & 0x0F) { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + case 0x8: + case 0x9: + return 1000 * (reg >> 4) + 100 * subfield_b; + case 0xA: + return 1000 * (reg >> 4) + 250; + case 0xB: + return 1000 * (reg >> 4) + 333; + case 0xC: + return 1000 * (reg >> 4) + 667; + case 0xD: + return 1000 * (reg >> 4) + 750; + } + return 0; +} + +/*------------------------------------------------------------------ + * Find the installed DIMMs, make sure that the are DDR2, and fill + * in the dimm_ranks array. Then dimm_ranks[dimm_num] > 0 iff the + * DIMM and dimm_num is present. + * Note: Because there are only two chip-select lines, it is assumed + * that a board with a single socket can support two ranks on that + * socket, while a board with two sockets can support only one rank + * on each socket. + *-----------------------------------------------------------------*/ +static void get_spd_info(unsigned long dimm_ranks[], + unsigned long *ranks, + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_found = FALSE; + unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1; + unsigned char num_of_bytes; + unsigned char total_size; + + *ranks = 0; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + num_of_bytes = 0; + total_size = 0; + + num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); + total_size = spd_read(iic0_dimm_addr[dimm_num], 1); + if ((num_of_bytes != 0) && (total_size != 0)) { + unsigned char const dimm_type = + spd_read(iic0_dimm_addr[dimm_num], 2); + + unsigned long ranks_on_dimm = + (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1; + + if (8 != dimm_type) { + switch (dimm_type) { + case 1: + printf("ERROR: Standard Fast Page Mode " + "DRAM DIMM"); + break; + case 2: + printf("ERROR: EDO DIMM"); + break; + case 3: + printf("ERROR: Pipelined Nibble DIMM"); + break; + case 4: + printf("ERROR: SDRAM DIMM"); + break; + case 5: + printf("ERROR: Multiplexed ROM DIMM"); + break; + case 6: + printf("ERROR: SGRAM DIMM"); + break; + case 7: + printf("ERROR: DDR1 DIMM"); + break; + default: + printf("ERROR: Unknown DIMM (type %d)", + (unsigned int)dimm_type); + break; + } + printf(" detected in slot %lu.\n", dimm_num); + printf("Only DDR2 SDRAM DIMMs are supported." + "\n"); + printf("Replace the module with a DDR2 DIMM." + "\n\n"); + spd_ddr_init_hang(); + } + dimm_found = TRUE; + debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM" + "\n", dimm_num, ranks_on_dimm); + if (ranks_on_dimm > max_ranks_per_dimm) { + printf("WARNING: DRAM DIMM in slot %lu has %lu " + "ranks.\n"); + if (1 == max_ranks_per_dimm) { + printf("Only one rank will be used.\n"); + } else { + printf + ("Only two ranks will be used.\n"); + } + ranks_on_dimm = max_ranks_per_dimm; + } + dimm_ranks[dimm_num] = ranks_on_dimm; + *ranks += ranks_on_dimm; + } else { + dimm_ranks[dimm_num] = 0; + debug("DIMM slot %lu: Not populated\n", dimm_num); + } + } + if (dimm_found == FALSE) { + printf("ERROR: No memory installed.\n"); + printf("Install at least one DDR2 DIMM.\n\n"); + spd_ddr_init_hang(); + } + debug("Total number of ranks = %d\n", *ranks); +} + +/*------------------------------------------------------------------ + * For the memory DIMMs installed, this routine verifies that + * frequency previously calculated is supported. + *-----------------------------------------------------------------*/ +static void check_frequency(unsigned long *dimm_ranks, + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long cycle_time; + unsigned long calc_cycle_time; + + /* + * calc_cycle_time is calculated from DDR frequency set by board/chip + * and is expressed in picoseconds to match the way DIMM cycle time is + * calculated below. + */ + calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq); + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + cycle_time = + get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9)); + debug("cycle_time=%d ps\n", cycle_time); + + if (cycle_time > (calc_cycle_time + 10)) { + /* + * the provided sdram cycle_time is too small + * for the available DIMM cycle_time. The + * additionnal 10ps is here to accept a small + * incertainty. + */ + printf + ("ERROR: DRAM DIMM detected with cycle_time %d ps in " + "slot %d \n while calculated cycle time is %d ps.\n", + (unsigned int)cycle_time, + (unsigned int)dimm_num, + (unsigned int)calc_cycle_time); + printf + ("Replace the DIMM, or change DDR frequency via " + "strapping bits.\n\n"); + spd_ddr_init_hang(); + } + } + } +} + +/*------------------------------------------------------------------ + * This routine gets size information for the installed memory + * DIMMs. + *-----------------------------------------------------------------*/ +static void get_dimm_size(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long *const rows, + unsigned long *const banks, + unsigned long *const cols, unsigned long *const width) +{ + unsigned long dimm_num; + + *rows = 0; + *banks = 0; + *cols = 0; + *width = 0; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + unsigned long t; + + /* Rows */ + t = spd_read(iic0_dimm_addr[dimm_num], 3); + if (0 == *rows) { + *rows = t; + } else if (t != *rows) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of rows.\n\n"); + spd_ddr_init_hang(); + } + /* Banks */ + t = spd_read(iic0_dimm_addr[dimm_num], 17); + if (0 == *banks) { + *banks = t; + } else if (t != *banks) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of banks.\n\n"); + spd_ddr_init_hang(); + } + /* Columns */ + t = spd_read(iic0_dimm_addr[dimm_num], 4); + if (0 == *cols) { + *cols = t; + } else if (t != *cols) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of columns.\n\n"); + spd_ddr_init_hang(); + } + /* Data width */ + t = spd_read(iic0_dimm_addr[dimm_num], 6); + if (0 == *width) { + *width = t; + } else if (t != *width) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same data width.\n\n"); + spd_ddr_init_hang(); + } + } + } + debug("Number of rows = %d\n", *rows); + debug("Number of columns = %d\n", *cols); + debug("Number of banks = %d\n", *banks); + debug("Data width = %d\n", *width); + if (*rows > 14) { + printf("ERROR: DRAM DIMM modules have %lu address rows.\n", + *rows); + printf("Only modules with 14 or fewer rows are supported.\n\n"); + spd_ddr_init_hang(); + } + if (4 != *banks && 8 != *banks) { + printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks); + printf("Only modules with 4 or 8 banks are supported.\n\n"); + spd_ddr_init_hang(); + } + if (*cols > 12) { + printf("ERROR: DRAM DIMM modules have %lu address columns.\n", + *cols); + printf("Only modules with 12 or fewer columns are " + "supported.\n\n"); + spd_ddr_init_hang(); + } + if (32 != *width && 40 != *width && 64 != *width && 72 != *width) { + printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n", + *width); + printf("Only modules with widths of 32, 40, 64, and 72 bits " + "are supported.\n\n"); + spd_ddr_init_hang(); + } +} + +/*------------------------------------------------------------------ + * Only 1.8V modules are supported. This routine verifies this. + *-----------------------------------------------------------------*/ +static void check_voltage_type(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long voltage_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); + if (0x05 != voltage_type) { /* 1.8V for DDR2 */ + printf("ERROR: Slot %lu provides 1.8V for DDR2 " + "DIMMs.\n", dimm_num); + switch (voltage_type) { + case 0x00: + printf("This DIMM is 5.0 Volt/TTL.\n"); + break; + case 0x01: + printf("This DIMM is LVTTL.\n"); + break; + case 0x02: + printf("This DIMM is 1.5 Volt.\n"); + break; + case 0x03: + printf("This DIMM is 3.3 Volt/TTL.\n"); + break; + case 0x04: + printf("This DIMM is 2.5 Volt.\n"); + break; + default: + printf("This DIMM is an unknown " + "voltage.\n"); + break; + } + printf("Replace it with a 1.8V DDR2 DIMM.\n\n"); + spd_ddr_init_hang(); + } + } + } +} + +static void program_ddr0_03(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq, + unsigned long rows, unsigned long *cas_latency) +{ + unsigned long dimm_num; + unsigned long cas_index; + unsigned long cycle_2_0_clk; + unsigned long cycle_3_0_clk; + unsigned long cycle_4_0_clk; + unsigned long cycle_5_0_clk; + unsigned long max_2_0_tcyc_ps = 100; + unsigned long max_3_0_tcyc_ps = 100; + unsigned long max_4_0_tcyc_ps = 100; + unsigned long max_5_0_tcyc_ps = 100; + unsigned char cas_available = 0x3C; /* value for DDR2 */ + u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2); + unsigned int const tcyc_addr[3] = { 9, 23, 25 }; + + /*------------------------------------------------------------------ + * Get the board configuration info. + *-----------------------------------------------------------------*/ + debug("sdram_freq = %d\n", sdram_freq); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned char const cas_bit = + spd_read(iic0_dimm_addr[dimm_num], 18); + unsigned char cas_mask; + + cas_available &= cas_bit; + for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) { + if (cas_bit & cas_mask) + break; + } + debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n", + cas_bit, cas_mask); + + for (cas_index = 0; cas_index < 3; + cas_mask >>= 1, cas_index++) { + unsigned long cycle_time_ps; + + if (!(cas_available & cas_mask)) { + continue; + } + cycle_time_ps = + get_tcyc(spd_read(iic0_dimm_addr[dimm_num], + tcyc_addr[cas_index])); + + debug("cas_index = %d: cycle_time_ps = %d\n", + cas_index, cycle_time_ps); + /* + * DDR2 devices use the following bitmask for CAS latency: + * Bit 7 6 5 4 3 2 1 0 + * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD + */ + switch (cas_mask) { + case 0x20: + max_5_0_tcyc_ps = + max(max_5_0_tcyc_ps, cycle_time_ps); + break; + case 0x10: + max_4_0_tcyc_ps = + max(max_4_0_tcyc_ps, cycle_time_ps); + break; + case 0x08: + max_3_0_tcyc_ps = + max(max_3_0_tcyc_ps, cycle_time_ps); + break; + case 0x04: + max_2_0_tcyc_ps = + max(max_2_0_tcyc_ps, cycle_time_ps); + break; + } + } + } + } + debug("cas_available (bit map) = 0x%02X\n", cas_available); + + /*------------------------------------------------------------------ + * Set the SDRAM mode, SDRAM_MMODE + *-----------------------------------------------------------------*/ + + /* add 10 here because of rounding problems */ + cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10; + cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10; + cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10; + cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10; + debug("cycle_2_0_clk = %d\n", cycle_2_0_clk); + debug("cycle_3_0_clk = %d\n", cycle_3_0_clk); + debug("cycle_4_0_clk = %d\n", cycle_4_0_clk); + debug("cycle_5_0_clk = %d\n", cycle_5_0_clk); + + if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) { + *cas_latency = 2; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) | + DDR0_03_CASLAT_LIN_ENCODE(0x4); + } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) { + *cas_latency = 3; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) | + DDR0_03_CASLAT_LIN_ENCODE(0x6); + } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) { + *cas_latency = 4; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) | + DDR0_03_CASLAT_LIN_ENCODE(0x8); + } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) { + *cas_latency = 5; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) | + DDR0_03_CASLAT_LIN_ENCODE(0xA); + } else { + printf("ERROR: Cannot find a supported CAS latency with the " + "installed DIMMs.\n"); + printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, " + "and 5.0 are supported.\n"); + printf("Make sure the PLB speed is within the supported range " + "of the DIMMs.\n"); + printf("sdram_freq=%d cycle2=%d cycle3=%d cycle4=%d " + "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk, + cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); + spd_ddr_init_hang(); + } + debug("CAS latency = %d\n", *cas_latency); + mtsdram(DDR0_03, ddr0_03); +} + +static void program_ddr0_04(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rc_ps = 0; + unsigned long t_rrd_ps = 0; + unsigned long t_rtp_ps = 0; + unsigned long t_rc_clk; + unsigned long t_rrd_clk; + unsigned long t_rtp_clk; + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tRC */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41); + switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) { + case 0x1: + ps += 250; + break; + case 0x2: + ps += 333; + break; + case 0x3: + ps += 500; + break; + case 0x4: + ps += 667; + break; + case 0x5: + ps += 750; + break; + } + t_rc_ps = max(t_rc_ps, ps); + /* tRRD */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28); + t_rrd_ps = max(t_rrd_ps, ps); + /* tRTP */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38); + t_rtp_ps = max(t_rtp_ps, ps); + } + } + debug("t_rc_ps = %d\n", t_rc_ps); + t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000; + debug("t_rrd_ps = %d\n", t_rrd_ps); + t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000; + debug("t_rtp_ps = %d\n", t_rtp_ps); + t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) | + DDR0_04_TRRD_ENCODE(t_rrd_clk) | + DDR0_04_TRTP_ENCODE(t_rtp_clk)); +} + +static void program_ddr0_05(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rp_ps = 0; + unsigned long t_ras_ps = 0; + unsigned long t_rp_clk; + unsigned long t_ras_clk; + u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tRP */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27); + t_rp_ps = max(t_rp_ps, ps); + /* tRAS */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30); + t_ras_ps = max(t_ras_ps, ps); + } + } + debug("t_rp_ps = %d\n", t_rp_ps); + t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000; + debug("t_ras_ps = %d\n", t_ras_ps); + t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) | + DDR0_05_TRAS_MIN_ENCODE(t_ras_clk)); +} + +static void program_ddr0_06(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned char spd_40; + unsigned long t_wtr_ps = 0; + unsigned long t_rfc_ps = 0; + unsigned long t_wtr_clk; + unsigned long t_rfc_clk; + u32 ddr0_06 = + DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tWTR */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37); + t_wtr_ps = max(t_wtr_ps, ps); + /* tRFC */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42); + spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40); + ps += 256000 * (spd_40 & 0x01); + switch ((spd_40 & 0x0E) >> 1) { + case 0x1: + ps += 250; + break; + case 0x2: + ps += 333; + break; + case 0x3: + ps += 500; + break; + case 0x4: + ps += 667; + break; + case 0x5: + ps += 750; + break; + } + t_rfc_ps = max(t_rfc_ps, ps); + } + } + debug("t_wtr_ps = %d\n", t_wtr_ps); + t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000; + debug("t_rfc_ps = %d\n", t_rfc_ps); + t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) | + DDR0_06_TRFC_ENCODE(t_rfc_clk)); +} + +static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks) +{ + unsigned long csmap; + + if (2 == ranks) { + /* Both chip selects in use */ + csmap = 0x03; + } else { + /* One chip select in use */ + csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2; + } + mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) | + DDR0_10_CS_MAP_ENCODE(csmap) | + DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0)); +} + +static void program_ddr0_11(unsigned long sdram_freq) +{ + unsigned long const t_xsnr_ps = 200000; /* 200 ns */ + unsigned long t_xsnr_clk; + + debug("t_xsnr_ps = %d\n", t_xsnr_ps); + t_xsnr_clk = + (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) | + DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200)); +} + +static void program_ddr0_22(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, unsigned long width) +{ +#if defined(CONFIG_DDR_ECC) + unsigned long dimm_num; + unsigned long ecc_available = width >= 64; + u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | + DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS); + + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + /* Check for ECC */ + if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) & + 0x02)) { + ecc_available = FALSE; + } + } + } + if (ecc_available) { + debug("ECC found on all DIMMs present\n"); + mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3)); + } else { + debug("ECC not found on some or all DIMMs present\n"); + mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0)); + } +#else + mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) | + DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | + DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS)); +#endif /* defined(CONFIG_DDR_ECC) */ +} + +static void program_ddr0_24(unsigned long ranks) +{ + u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */ + DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0); + + if (2 == ranks) { + /* Both chip selects in use */ + ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) | + DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2); + } else { + /* One chip select in use */ + /* One of the two fields added to ddr0_24 is a "don't care" */ + ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) | + DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1); + } + mtsdram(DDR0_24, ddr0_24); +} + +static void program_ddr0_26(unsigned long sdram_freq) +{ + unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */ + /* TODO: check definition of tRAS_MAX */ + unsigned long const t_ras_max_ps = 9 * t_ref_ps; + unsigned long t_ras_max_clk; + unsigned long t_ref_clk; + + /* Round down t_ras_max_clk and t_ref_clk */ + debug("t_ras_max_ps = %d\n", t_ras_max_ps); + t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000; + debug("t_ref_ps = %d\n", t_ref_ps); + t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000; + mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) | + DDR0_26_TREF_ENCODE(t_ref_clk)); +} + +static void program_ddr0_27(unsigned long sdram_freq) +{ + unsigned long const t_init_ps = 200000000; /* 200 us. init */ + unsigned long t_init_clk; + + debug("t_init_ps = %d\n", t_init_ps); + t_init_clk = + (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) | + DDR0_27_TINIT_ENCODE(t_init_clk)); +} + +static void program_ddr0_43(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq, + unsigned long cols, unsigned long banks) +{ + unsigned long dimm_num; + unsigned long t_wr_ps = 0; + unsigned long t_wr_clk; + u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) | + DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) | + DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36); + t_wr_ps = max(t_wr_ps, ps); + } + } + debug("t_wr_ps = %d\n", t_wr_ps); + t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk)); +} + +static void program_ddr0_44(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rcd_ps = 0; + unsigned long t_rcd_clk; + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29); + t_rcd_ps = max(t_rcd_ps, ps); + } + } + debug("t_rcd_ps = %d\n", t_rcd_ps); + t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk)); +} + +/*-----------------------------------------------------------------------------+ + * initdram. Initializes the 440EPx/GPx DDR SDRAM controller. + * Note: This routine runs from flash with a stack set up in the chip's + * sram space. It is important that the routine does not require .sbss, .bss or + * .data sections. It also cannot call routines that require these sections. + *-----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures SDRAM memory banks for DDR operation. + * Auto Memory Configuration option reads the DDR SDRAM EEPROMs + * via the IIC bus and then configures the DDR SDRAM memory + * banks appropriately. If Auto Memory Configuration is + * not used, it is assumed that no DIMM is plugged + *-----------------------------------------------------------------------------*/ +long int initdram(int board_type) +{ + unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; + unsigned long dimm_ranks[MAXDIMMS]; + unsigned long ranks; + unsigned long rows; + unsigned long banks; + unsigned long cols; + unsigned long width; + unsigned long const sdram_freq = get_bus_freq(0); + unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */ + unsigned long cas_latency = 0; /* to quiet initialization warning */ + unsigned long dram_size; + + debug("\nEntering initdram()\n"); + + /*------------------------------------------------------------------ + * Stop the DDR-SDRAM controller. + *-----------------------------------------------------------------*/ + mtsdram(DDR0_02, DDR0_02_START_ENCODE(0)); + + /* + * Make sure I2C controller is initialized + * before continuing. + */ + /* switch to correct I2C bus */ + I2C_SET_BUS(CFG_SPD_BUS_NUM); + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /*------------------------------------------------------------------ + * Clear out the serial presence detect buffers. + * Perform IIC reads from the dimm. Fill in the spds. + * Check to see if the dimm slots are populated + *-----------------------------------------------------------------*/ + get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Check the frequency supported for the dimms plugged. + *-----------------------------------------------------------------*/ + check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + /*------------------------------------------------------------------ + * Check and get size information. + *-----------------------------------------------------------------*/ + get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks, + &cols, &width); + + /*------------------------------------------------------------------ + * Check the voltage type for the dimms plugged. + *-----------------------------------------------------------------*/ + check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Program registers for SDRAM controller. + *-----------------------------------------------------------------*/ + mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | + DDR0_00_DLL_START_POINT_DECODE(0x0A)); + + mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) | + DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) | + DDR0_01_INT_MASK_ENCODE(0xFF)); + + program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, + rows, &cas_latency); + + program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + /*------------------------------------------------------------------ + * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia + * board SDRAM, but may be overly concervate. + *-----------------------------------------------------------------*/ + mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | + DDR0_07_TFAW_ENCODE(13) | + DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | + DDR0_07_AREFRESH_ENCODE(0)); + + mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) | + DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) | + DDR0_08_DDRII_ENCODE(1)); + + mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) | + DDR0_09_RTT_0_ENCODE(0x1) | + DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) | + DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20)); + + program_ddr0_10(dimm_ranks, ranks); + + program_ddr0_11(sdram_freq); + + mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3)); + + mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) | + DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) | + DDR0_14_REG_DIMM_ENABLE_ENCODE(0)); + + mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS)); + + mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS)); + + program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width); + + mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) | + DDR0_23_FWC_ENCODE(0)); + + program_ddr0_24(ranks); + + program_ddr0_26(sdram_freq); + + program_ddr0_27(sdram_freq); + + mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) | + DDR0_28_EMRS2_DATA_ENCODE(0x0000)); + + mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); + + mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | + DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); + + program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, + cols, banks); + + program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + denali_sdram_register_dump(); + + dram_size = (width >= 64) ? 8 : 4; + dram_size *= 1 << cols; + dram_size *= banks; + dram_size *= 1 << rows; + dram_size *= ranks; + debug("dram_size = %lu\n", dram_size); + + /* Start the SDRAM controler */ + mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); + denali_wait_for_dlllock(); + +#if defined(CONFIG_DDR_DATA_EYE) + /* -----------------------------------------------------------+ + * Perform data eye search if requested. + * ----------------------------------------------------------*/ + program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE); + denali_core_search_data_eye(); + denali_sdram_register_dump(); + remove_tlb(CFG_SDRAM_BASE, dram_size); +#endif + +#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) + program_tlb(0, CFG_SDRAM_BASE, dram_size, 0); + sync(); + eieio(); + /* Zero the memory */ + debug("Zeroing SDRAM..."); + dcbz_area(CFG_SDRAM_BASE, dram_size); + dflush(); + debug("Completed\n"); + sync(); + eieio(); + remove_tlb(CFG_SDRAM_BASE, dram_size); + +#if defined(CONFIG_DDR_ECC) + /* + * If ECC is enabled, clear and enable interrupts + */ + if (is_ecc_enabled()) { + u32 val; + + sync(); + eieio(); + /* Clear error status */ + mfsdram(DDR0_00, val); + mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + /* Set 'int_mask' parameter to functionnal value */ + mfsdram(DDR0_01, val); + mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) | + DDR0_01_INT_MASK_ALL_OFF); +#if defined(CONFIG_DDR_DATA_EYE) + /* + * Running denali_core_search_data_eye() when ECC is enabled + * causes non-ECC machine checks. This clears them. + */ + print_mcsr(); + mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); + print_mcsr(); +#endif + sync(); + eieio(); + } +#endif /* defined(CONFIG_DDR_ECC) */ +#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ + + program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); + return dram_size; +} + +void board_add_ram_info(int use_default) +{ + u32 val; + + printf(" (ECC"); + if (!is_ecc_enabled()) { + printf(" not"); + } + printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000); + + mfsdram(DDR0_03, val); + printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1); +} +#endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index 3ef30004fb..afcb974068 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -21,11 +21,6 @@ * MA 02111-1307 USA */ -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - #include <common.h> #include <watchdog.h> #include <command.h> @@ -39,42 +34,16 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * The aliases needed for this generic etherne MAC address - * fixup function are not in place yet. So don't use this - * approach for now. This will be enabled later. - */ -#undef USES_FDT_ALIASES - -#ifndef USES_FDT_ALIASES -static void do_fixup_macaddr(void *fdt, int offset, const void *val, int i) -{ - int rc; - - debug("Updating node EMAC%d\n", i); - - rc = fdt_setprop(fdt, offset, "mac-address", val, 6); - if (rc) - printf("Unable to update property %s, err=%s\n", - "mac-address", fdt_strerror(rc)); - rc = fdt_setprop(fdt, offset, "local-mac-address", val, 6); - if (rc) - printf("Unable to update property %s, err=%s\n", - "local-mac-address", fdt_strerror(rc)); -} -#endif /* USES_FDT_ALIASES */ - void ft_cpu_setup(void *blob, bd_t *bd) { - char *cpu_path = "/cpus/" OF_CPU; sys_info_t sys_info; - int offset; - int i; get_sys_info(&sys_info); - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", bd->bi_intfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", + bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", + bd->bi_intfreq, 1); do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", @@ -86,47 +55,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1); -#ifdef USES_FDT_ALIASES /* - * The aliases needed for this generic etherne MAC address - * fixup function are not in place yet. So don't use this - * approach for now. This will be enabled later. + * Fixup all ethernet nodes + * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob, bd); -#else - offset = -1; - for (i = 0; i < 4; i++) { - /* - * FIXME: This will cause problems with emac3 compatible - * devices, like on 405GP. But hopefully when we deal - * with those devices, the aliases stuff will be in - * place. - */ - offset = fdt_node_offset_by_compatible(blob, offset, "ibm,emac4"); - if (offset < 0) - break; - - switch (i) { - case 0: - do_fixup_macaddr(blob, offset, bd->bi_enetaddr, 0); - break; -#ifdef CONFIG_HAS_ETH1 - case 1: - do_fixup_macaddr(blob, offset, bd->bi_enet1addr, 1); - break; -#endif -#ifdef CONFIG_HAS_ETH2 - case 2: - do_fixup_macaddr(blob, offset, bd->bi_enet2addr, 2); - break; -#endif -#ifdef CONFIG_HAS_ETH3 - case 3: - do_fixup_macaddr(blob, offset, bd->bi_enet3addr, 3); - break; -#endif - } - } -#endif /* USES_FDT_ALIASES */ } #endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 98ba0a7b35..4216f0bd41 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -27,19 +27,6 @@ | | Author: Mark Wisner | - | Change Activity- - | - | Date Description of Change BY - | --------- --------------------- --- - | 05-May-99 Created MKW - | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to - | better match OPB speed. Also modified delay times. JWB - | 29-Jul-99 Added Full duplex support MKW - | 24-Aug-99 Removed printf from dp83843_duplex() JWB - | 19-Jul-00 Ported to esd cpci405 sr - | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS - | <travis.sawyer@sandburst.com> - | +-----------------------------------------------------------------------------*/ #include <common.h> @@ -61,7 +48,6 @@ void miiphy_dump (char *devname, unsigned char addr) unsigned long i; unsigned short data; - for (i = 0; i < 0x1A; i++) { if (miiphy_read (devname, addr, i, &data)) { printf ("read error for reg %lx\n", i); @@ -76,15 +62,86 @@ void miiphy_dump (char *devname, unsigned char addr) } /* end for loop */ } /* end dump */ - /***********************************************************/ /* (Re)start autonegotiation */ /***********************************************************/ int phy_setup_aneg (char *devname, unsigned char addr) { - unsigned short ctl, adv; + u16 bmcr; + +#if defined(CONFIG_PHY_DYNAMIC_ANEG) + /* + * Set up advertisement based on capablilities reported by the PHY. + * This should work for both copper and fiber. + */ + u16 bmsr; +#if defined(CONFIG_PHY_GIGE) + u16 exsr = 0x0000; +#endif + + miiphy_read (devname, addr, PHY_BMSR, &bmsr); + +#if defined(CONFIG_PHY_GIGE) + if (bmsr & PHY_BMSR_EXT_STAT) + miiphy_read (devname, addr, PHY_EXSR, &exsr); + + if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) { + /* 1000BASE-X */ + u16 anar = 0x0000; + + if (exsr & PHY_EXSR_1000XF) + anar |= PHY_X_ANLPAR_FD; + + if (exsr & PHY_EXSR_1000XH) + anar |= PHY_X_ANLPAR_HD; + + miiphy_write (devname, addr, PHY_ANAR, anar); + } else +#endif + { + u16 anar, btcr; + + miiphy_read (devname, addr, PHY_ANAR, &anar); + anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | + PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10); + + miiphy_read (devname, addr, PHY_1000BTCR, &btcr); + btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); + + if (bmsr & PHY_BMSR_100T4) + anar |= PHY_ANLPAR_T4; + + if (bmsr & PHY_BMSR_100TXF) + anar |= PHY_ANLPAR_TXFD; + + if (bmsr & PHY_BMSR_100TXH) + anar |= PHY_ANLPAR_TX; + + if (bmsr & PHY_BMSR_10TF) + anar |= PHY_ANLPAR_10FD; + + if (bmsr & PHY_BMSR_10TH) + anar |= PHY_ANLPAR_10; + + miiphy_write (devname, addr, PHY_ANAR, anar); + +#if defined(CONFIG_PHY_GIGE) + if (exsr & PHY_EXSR_1000TF) + btcr |= PHY_1000BTCR_1000FD; + + if (exsr & PHY_EXSR_1000TH) + btcr |= PHY_1000BTCR_1000HD; + + miiphy_write (devname, addr, PHY_1000BTCR, btcr); +#endif + } + +#else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ + /* + * Set up standard advertisement + */ + u16 adv; - /* Setup standard advertise */ miiphy_read (devname, addr, PHY_ANAR, &adv); adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | @@ -95,15 +152,16 @@ int phy_setup_aneg (char *devname, unsigned char addr) adv |= (0x0300); miiphy_write (devname, addr, PHY_1000BTCR, adv); +#endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ + /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &ctl); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, ctl); + miiphy_read (devname, addr, PHY_BMCR, &bmcr); + bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write (devname, addr, PHY_BMCR, bmcr); return 0; } - /***********************************************************/ /* read a phy reg and return the value with a rc */ /***********************************************************/ @@ -116,19 +174,23 @@ unsigned int miiphy_getemac_offset (void) /* Need to find out which mdi port we're using */ zmii = in_be32((void *)ZMII_FER); - if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { + if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) /* using port 0 */ eoffset = 0; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) { + + else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) /* using port 1 */ eoffset = 0x100; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) { + + else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) /* using port 2 */ eoffset = 0x400; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) { + + else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) /* using port 3 */ eoffset = 0x600; - } else { + + else { /* None of the mdi ports are enabled! */ /* enable port 0 */ zmii |= ZMII_FER_MDI << ZMII_FER_V (0); @@ -156,21 +218,20 @@ unsigned int miiphy_getemac_offset (void) #endif } - -int emac4xx_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) { unsigned long sta_reg; /* STA scratch area */ unsigned long i; unsigned long emac_reg; - emac_reg = miiphy_getemac_offset (); /* see if it is ready for 1000 nsec */ i = 0; /* see if it is ready for sec */ - while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == + EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) { #ifdef ET_DEBUG @@ -187,10 +248,10 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) -#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; #else - sta_reg |= EMAC_STACR_READ; + sta_reg |= EMAC_STACR_READ; #endif #else sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; @@ -211,37 +272,34 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG - printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ + printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif i = 0; while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); - if (i > 5) { + if (i > 5) return -1; - } + i++; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif } - if ((sta_reg & EMAC_STACR_PHYE) != 0) { + if ((sta_reg & EMAC_STACR_PHYE) != 0) return -1; - } - *value = *(short *) (&sta_reg); + *value = *(short *)(&sta_reg); return 0; - } /* phy_read */ - /***********************************************************/ /* write a phy reg and return the value with a rc */ /***********************************************************/ -int emac4xx_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, + unsigned short value) { unsigned long sta_reg; /* STA scratch area */ unsigned long i; @@ -251,9 +309,11 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, /* see if it is ready for 1000 nsec */ i = 0; - while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == + EMAC_STACR_OC_MASK) { if (i > 5) return -1; + udelay (7); i++; } @@ -263,10 +323,10 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) -#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; #else - sta_reg |= EMAC_STACR_WRITE; + sta_reg |= EMAC_STACR_WRITE; #endif #else sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; @@ -278,8 +338,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, !defined(CONFIG_405EX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif - sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ - sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ + sta_reg = sta_reg | ((unsigned long)addr << 5); /* Phy address */ + sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ memcpy (&sta_reg, &value, 2); /* put in data */ out_be32((void *)EMAC_STACR + emac_reg, sta_reg); @@ -288,12 +348,13 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, i = 0; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG - printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ + printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) return -1; + i++; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG @@ -303,6 +364,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, if ((sta_reg & EMAC_STACR_PHYE) != 0) return -1; + return 0; -} /* phy_write */ +} /* phy_write */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index f5a135f1a0..52601ed700 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1356,7 +1356,11 @@ relocate_code: dccci 0,0 /* Invalidate data cache, now no longer our stack */ sync isync - addi r1,r0,0x0000 /* TLB entry #0 */ +#ifdef CFG_TLB_FOR_BOOT_FLASH + addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */ +#else + addi r1,r0,0x0000 /* Default TLB entry is #0 */ +#endif tlbre r0,r1,0x0002 /* Read contents */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ tlbwe r0,r1,0x0002 /* Save it out */ @@ -1490,16 +1494,25 @@ clear_bss: lwz r4,GOT(_end) cmplw 0, r3, r4 - beq 6f + beq 7f li r0, 0 -5: + + andi. r5, r4, 3 + beq 6f + sub r4, r4, r5 + mtctr r5 + mr r5, r4 +5: stb r0, 0(r5) + addi r5, r5, 1 + bdnz 5b +6: stw r0, 0(r3) addi r3, r3, 4 cmplw 0, r3, r4 - bne 5b -6: + bne 6b +7: mr r3, r9 /* Init Data pointer */ mr r4, r10 /* Destination Address */ bl board_init_r diff --git a/cpu/sh4/Makefile b/cpu/sh4/Makefile new file mode 100644 index 0000000000..1bb8bd7729 --- /dev/null +++ b/cpu/sh4/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +OBJS = cpu.o interrupts.o watchdog.o time.o cache.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/sh4/cache.c b/cpu/sh4/cache.c new file mode 100644 index 0000000000..4e744d7145 --- /dev/null +++ b/cpu/sh4/cache.c @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> + +/* + * Jump to P2 area. + * When handling TLB or caches, we need to do it from P2 area. + */ +#define jump_to_P2() \ + do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "or %1, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy) \ + : "r" (0x20000000)); \ + } while (0) + +/* + * Back to P1 area. + */ +#define back_to_P1() \ + do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "nop;nop;nop;nop;nop;nop;nop\n\t" \ + "mov.l 1f, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy)); \ + } while (0) + +#define CACHE_VALID 1 +#define CACHE_UPDATED 2 + +static inline void cache_wback_all(void) +{ + unsigned long addr, data, i, j; + + jump_to_P2(); + for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){ + for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { + addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT) + | (i << CACHE_OC_ENTRY_SHIFT); + data = inl(addr); + if (data & CACHE_UPDATED) { + data &= ~CACHE_UPDATED; + outl(data, addr); + } + } + } + back_to_P1(); +} + + +#define CACHE_ENABLE 0 +#define CACHE_DISABLE 1 + +int cache_control(unsigned int cmd) +{ + unsigned long ccr; + + jump_to_P2(); + ccr = inl(CCR); + + if (ccr & CCR_CACHE_ENABLE) + cache_wback_all(); + + if (cmd == CACHE_DISABLE) + outl(CCR_CACHE_STOP, CCR); + else + outl(CCR_CACHE_INIT, CCR); + back_to_P1(); + + return 0; +} diff --git a/cpu/sh4/config.mk b/cpu/sh4/config.mk new file mode 100644 index 0000000000..b3feb2a515 --- /dev/null +++ b/cpu/sh4/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +PLATFORM_CPPFLAGS += -m4-nofpu +PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c new file mode 100644 index 0000000000..0ebf95180c --- /dev/null +++ b/cpu/sh4/cpu.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> + +int checkcpu(void) +{ + puts("CPU: SH4\n"); + return 0; +} + +int cpu_init (void) +{ + return 0; +} + +int cleanup_before_linux (void) +{ + disable_interrupts(); + return 0; +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts(); + reset_cpu (0); + return 0; +} + +void flush_cache (unsigned long addr, unsigned long size) +{ + +} + +void icache_enable (void) +{ + cache_control(0); +} + +void icache_disable (void) +{ + cache_control(1); +} + +int icache_status (void) +{ + return 0; +} + +void dcache_enable (void) +{ +} + +void dcache_disable (void) +{ +} + +int dcache_status (void) +{ + return 0; +} diff --git a/cpu/sh4/interrupts.c b/cpu/sh4/interrupts.c new file mode 100644 index 0000000000..6988ecc7c2 --- /dev/null +++ b/cpu/sh4/interrupts.c @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +int interrupt_init (void) +{ + return 0; +} + +void enable_interrupts (void) +{ + +} + +int disable_interrupts (void){ + return 0; +} diff --git a/cpu/sh4/start.S b/cpu/sh4/start.S new file mode 100644 index 0000000000..a68ebb8c93 --- /dev/null +++ b/cpu/sh4/start.S @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + + .text + .align 2 + + .global _start +_start: + mov.l ._lowlevel_init, r0 +100: bsrf r0 + nop + + bsr 1f + nop +1: sts pr, r5 + mov.l ._reloc_dst, r4 + add #(_start-1b), r5 + mov.l ._reloc_dst_end, r6 + +2: mov.l @r5+, r1 + mov.l r1, @r4 + add #4, r4 + cmp/hs r6, r4 + bf 2b + + mov.l ._bss_start, r4 + mov.l ._bss_end, r5 + mov #0, r1 + +3: mov.l r1, @r4 /* bss clear */ + add #4, r4 + cmp/hs r5, r4 + bf 3b + + mov.l ._gd_init, r13 /* global data */ + mov.l ._stack_init, r15 /* stack */ + + mov.l ._sh_generic_init, r0 + jsr @r0 + nop + +loop: + bra loop + + .align 2 + +._lowlevel_init: .long (lowlevel_init - (100b + 4)) +._reloc_dst: .long reloc_dst +._reloc_dst_end: .long reloc_dst_end +._bss_start: .long bss_start +._bss_end: .long bss_end +._gd_init: .long (_start - CFG_GBL_DATA_SIZE) +._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16) +._sh_generic_init: .long sh_generic_init diff --git a/cpu/sh4/time.c b/cpu/sh4/time.c new file mode 100644 index 0000000000..5f8a3a0802 --- /dev/null +++ b/cpu/sh4/time.c @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2007 + * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#define TMU_MAX_COUNTER (~0UL) + +static void tmu_timer_start (unsigned int timer) +{ + if (timer > 2) + return; + + *((volatile unsigned char *) TSTR) |= (1 << timer); +} + +static void tmu_timer_stop (unsigned int timer) +{ + u8 val = *((volatile u8 *)TSTR); + if (timer > 2) + return; + *((volatile unsigned char *)TSTR) = val &~(1 << timer); +} + +int timer_init (void) +{ + /* Divide clock by 4 */ + *(volatile u16 *)TCR0 = 0; + + tmu_timer_stop(0); + tmu_timer_start(0); + return 0; +} + +/* + In theory we should return a true 64bit value (ie something that doesn't + overflow). However, we don't. Therefore if TMU runs at fastest rate of + 6.75 MHz this value will wrap after u-boot has been running for approx + 10 minutes. +*/ +unsigned long long get_ticks (void) +{ + return (0 - *((volatile u32 *) TCNT0)); +} + +unsigned long get_timer (unsigned long base) +{ + return ((0 - *((volatile u32 *) TCNT0)) - base); +} + +void set_timer (unsigned long t) +{ + *((volatile unsigned int *) TCNT0) = (0 - t); +} + +void reset_timer (void) +{ + tmu_timer_stop(0); + set_timer (0); + tmu_timer_start(0); +} + +void udelay (unsigned long usec) +{ + unsigned int start = get_timer (0); + unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000)); + + while (get_timer (0) < end) + continue; +} + +unsigned long get_tbclk (void) +{ + return CFG_HZ; +} diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c new file mode 100644 index 0000000000..346e21714f --- /dev/null +++ b/cpu/sh4/watchdog.c @@ -0,0 +1,50 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#define WDT_BASE WTCNT + +static unsigned char cnt_read (void){ + return *((volatile unsigned char *)(WDT_BASE + 0x00)); +} + +static unsigned char csr_read (void){ + return *((volatile unsigned char *)(WDT_BASE + 0x04)); +} + +static void cnt_write (unsigned char value){ + while (csr_read() & (1 << 5)) { + /* delay */ + } + *((volatile unsigned short *)(WDT_BASE + 0x00)) + = ((unsigned short) value) | 0x5A00; +} + +static void csr_write (unsigned char value){ + *((volatile unsigned short *)(WDT_BASE + 0x04)) + = ((unsigned short) value) | 0xA500; +} + + +int watchdog_init (void){ return 0; } + +void reset_cpu (unsigned long ignored) +{ + while(1); +} diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia new file mode 100644 index 0000000000..3ed5cd33c4 --- /dev/null +++ b/doc/README.marubun-pcmcia @@ -0,0 +1,65 @@ + +U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver + Last update 21/11/2007 by Nobuhiro Iwamatsu + +======================================================================================== + +0. What's this? + This driver supports MARUBUN MR-SHPC-01. + url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html + (Sorry Japanese only.) + + This chip is used with SuperH well, and adopted by the + reference board. + ex. * MS7750SE01 + * MS7722SE01 + * other + + This chip doesn't support CardBus. + +1. base source code + The code is based on sources from the Linux kernel + ( arch/sh/kernel/cf-enabler.c ). + +2. How to use + The options you have to specify in the config file are (with the + value for my board as an example): + + * CONFIG_MARUBUN_PCCARD + If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD. + ex. #define CONFIG_MARUBUN_PCCARD + + * CONFIG_PCMCIA_SLOT_A + Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A . + ex. #define CONFIG_PCMCIA_SLOT_A 1 + + * CFG_MARUBUN_MRSHPC + This is MR-SHPC-01 PCMCIA controler base address. + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_MRSHPC 0xb03fffe0 + ( for MS7722SE01 environment ) + + * CFG_MARUBUN_MW1 + This is MR-SHPC-01 memory window base address. + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_MW1 0xb0400000 + ( for MS7722SE01 environment ) + + * CFG_MARUBUN_MW1 + This is MR-SHPC-01 attribute window base address. + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_MW2 0xb0500000 + ( for MS7722SE01 environment ) + + * CFG_MARUBUN_MW1 + This is MR-SHPC-01 I/O window base address. + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_IO 0xb0600000 + ( for MS7722SE01 environment ) + +3. Other + * Check Compact Flash only. + * Maybe, NE2000 compatible NIC is sure to move. + +Copyright (c) 2007 + Nobuhiro Iwamatsu <iwamatsu@nigaur.org> diff --git a/doc/README.sh b/doc/README.sh new file mode 100644 index 0000000000..075d360e90 --- /dev/null +++ b/doc/README.sh @@ -0,0 +1,61 @@ + +U-Boot for Renesas SuperH + Last update 08/10/2007 by Nobuhiro Iwamatsu + +================================================================================ +0. What's this? + This file contains status information for the port of U-Boot to the + Renesas SuperH series of CPUs. + +================================================================================ +1. Overview + SuperH has an original boot loader. However, source code is dirty, and + maintenance is not done. + To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu + started the porting to u-boot in 2007. + +================================================================================ +2. Supported CPUs + + 2.1. Renesas SH7750/SH7750R + 2.2. Renesas SH7722 + +================================================================================ +3. Supported Boards + + 3.1. Hitachi UL MS7750SE01/MS7750RSE01 + Board specific code is in board/ms7750se + To use this board, type "make ms7750se_config". + + 3.2. Hitachi UL MS7722SE01 + Board specific code is in board/ms7722se + To use this board, type "make ms7722se_config". + + ** README ** + In SuperH, S-record and binary of made u-boot work on the memory. + When u-boot is written in the flash, it is necessary to change the + address by using 'objcopy'. + ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec + +================================================================================ +4. Compiler + You can use the following of u-boot to compile. + - SuperH Linux Open site + http://www.superh-linux.org/ + - KPIT GNU tools + http://www.kpitgnutools.com/ + +================================================================================ +5. Future + I plan to support the following CPUs and boards. + 5.1. CPUs + - SH7710/SH7712 (SH3) + - SH7780(SH4) + - SH7785(SH4) + + 5.2. Boards + - Many boards ;-) + +================================================================================ +Copyright (c) 2007 + Nobuhiro Iwamatsu <iwamatsu@nigaur.org> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index cebb2ba635..32e3f44a91 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -34,6 +34,7 @@ COBJS-y += adm1021.o COBJS-y += ds1621.o COBJS-y += ds1722.o COBJS-y += ds1775.o +COBJS-y += lm73.o COBJS-y += lm75.o COBJS-y += lm81.o diff --git a/drivers/hwmon/lm73.c b/drivers/hwmon/lm73.c new file mode 100644 index 0000000000..f9ae01297b --- /dev/null +++ b/drivers/hwmon/lm73.c @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org + * + * based on dtt/lm75.c which is ... + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * National Semiconductor LM73 Temperature Sensor + */ + +#include <common.h> + +#ifdef CONFIG_DTT_LM73 +#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ + (CFG_EEPROM_PAGE_WRITE_BITS < 1) +# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM73" +#endif + +#include <i2c.h> +#include <dtt.h> + +/* + * Device code + */ +#define DTT_I2C_DEV_CODE 0x48 /* National Semi's LM73 device */ + +int dtt_read(int sensor, int reg) +{ + int dlen; + uchar data[2]; + + /* + * Validate 'reg' param and get register size. + */ + switch (reg) { + case DTT_CONFIG: + case DTT_CONTROL: + dlen = 1; + break; + case DTT_READ_TEMP: + case DTT_TEMP_HIGH: + case DTT_TEMP_LOW: + case DTT_ID: + dlen = 2; + break; + default: + return -1; + } + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate LM73 addr */ + /* + * Now try to read the register. + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return -1; + /* + * Handle 2 byte result. + */ + if (2 == dlen) + return ((int)((short)data[1] + (((short)data[0]) << 8))); + + return (int)data[0]; +} /* dtt_read() */ + +int dtt_write(int sensor, int reg, int val) +{ + int dlen; + uchar data[2]; + + /* + * Validate 'reg' param and handle register size + */ + switch (reg) { + case DTT_CONFIG: + case DTT_CONTROL: + dlen = 1; + data[0] = (char)(val & 0xff); + break; + case DTT_TEMP_HIGH: + case DTT_TEMP_LOW: + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + break; + default: + return -1; + } + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate LM73 addr */ + /* + * Write value to register. + */ + return i2c_write(sensor, reg, 1, data, dlen) != 0; +} /* dtt_write() */ + +static int _dtt_init(int sensor) +{ + int val; + + /* + * Validate the Identification register + */ + if (0x0190 != dtt_read(sensor, DTT_ID)) + return 1; + /* + * Setup THIGH (upper-limit) and TLOW (lower-limit) registers + */ + val = CFG_DTT_MAX_TEMP << 7; + if (dtt_write(sensor, DTT_TEMP_HIGH, val)) + return 1; + + val = CFG_DTT_MIN_TEMP << 7; + if (dtt_write(sensor, DTT_TEMP_LOW, val)) + return 1; + /* + * Setup configuraton register + */ + /* config = alert active low, disabled, and reset */ + val = 0x64; + if (dtt_write(sensor, DTT_CONFIG, val)) + return 1; + /* + * Setup control/status register + */ + /* control = temp resolution 0.25C */ + val = 0x00; + if (dtt_write(sensor, DTT_CONTROL, val)) + return 1; + + dtt_read(sensor, DTT_CONTROL); /* clear temperature flags */ + return 0; +} /* _dtt_init() */ + +int dtt_init(void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("%s%d FAILED INIT\n", header, i + 1); + else + printf("%s%d is %i C\n", header, i + 1, + dtt_get_temp(sensors[i])); + } + return 0; +} /* dtt_init() */ + +int dtt_get_temp(int sensor) +{ + return (dtt_read(sensor, DTT_READ_TEMP) + 0x0040) >> 7; +} /* dtt_get_temp() */ + +#endif /* CONFIG_DTT_LM73 */ diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 95c5e02af9..952e919843 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -29,6 +29,7 @@ COBJS-y += at45.o COBJS-y += cfi_flash.o COBJS-y += dataflash.o COBJS-y += mw_eeprom.o +COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 5579a1efc1..f370e4fbd3 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -42,9 +42,12 @@ #ifdef CFG_FLASH_CFI_DRIVER /* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. + * This file implements a Common Flash Interface (CFI) driver for + * U-Boot. + * + * The width of the port and the width of the chips are determined at + * initialization. These widths are used to calculate the address for + * access CFI data structures. * * References * JEDEC Standard JESD68 - Common Flash Interface (CFI) @@ -55,7 +58,7 @@ * AMD/Spansion Application Note: Migration from Single-byte to Three-byte * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * - * define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between + * Define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between * reading and writing ... (yes there is such a Hardware). */ @@ -98,10 +101,6 @@ #define AMD_STATUS_TOGGLE 0x40 #define AMD_STATUS_ERROR 0x20 -#define AMD_ADDR_ERASE_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) -#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) -#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA) - #define FLASH_OFFSET_MANUFACTURER_ID 0x00 #define FLASH_OFFSET_DEVICE_ID 0x01 #define FLASH_OFFSET_DEVICE_ID2 0x0E @@ -110,7 +109,8 @@ #define FLASH_OFFSET_CFI_ALT 0x555 #define FLASH_OFFSET_CFI_RESP 0x10 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 -#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 /* extended query table primary addr */ +/* extended query table primary address */ +#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 #define FLASH_OFFSET_WTOUT 0x1F #define FLASH_OFFSET_WBTOUT 0x20 #define FLASH_OFFSET_ETOUT 0x21 @@ -149,16 +149,9 @@ typedef union { unsigned long long ll; } cfiword_t; -typedef union { - volatile unsigned char *cp; - volatile unsigned short *wp; - volatile unsigned long *lp; - volatile unsigned long long *llp; -} cfiptr_t; - #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ -static uint flash_offset_cfi[2]={FLASH_OFFSET_CFI,FLASH_OFFSET_CFI_ALT}; +static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; /* use CFG_MAX_FLASH_BANKS_DETECT if defined */ #ifdef CFG_MAX_FLASH_BANKS_DETECT @@ -176,46 +169,151 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT #endif +typedef unsigned long flash_sect_t; + +/* CFI standard query structure */ +struct cfi_qry { + u8 qry[3]; + u16 p_id; + u16 p_adr; + u16 a_id; + u16 a_adr; + u8 vcc_min; + u8 vcc_max; + u8 vpp_min; + u8 vpp_max; + u8 word_write_timeout_typ; + u8 buf_write_timeout_typ; + u8 block_erase_timeout_typ; + u8 chip_erase_timeout_typ; + u8 word_write_timeout_max; + u8 buf_write_timeout_max; + u8 block_erase_timeout_max; + u8 chip_erase_timeout_max; + u8 dev_size; + u16 interface_desc; + u16 max_buf_write_size; + u8 num_erase_regions; + u32 erase_region_info[NUM_ERASE_REGIONS]; +} __attribute__((packed)); + +struct cfi_pri_hdr { + u8 pri[3]; + u8 major_version; + u8 minor_version; +} __attribute__((packed)); + +static void flash_write8(u8 value, void *addr) +{ + __raw_writeb(value, addr); +} + +static void flash_write16(u16 value, void *addr) +{ + __raw_writew(value, addr); +} + +static void flash_write32(u32 value, void *addr) +{ + __raw_writel(value, addr); +} + +static void flash_write64(u64 value, void *addr) +{ + /* No architectures currently implement __raw_writeq() */ + *(volatile u64 *)addr = value; +} + +static u8 flash_read8(void *addr) +{ + return __raw_readb(addr); +} + +static u16 flash_read16(void *addr) +{ + return __raw_readw(addr); +} + +static u32 flash_read32(void *addr) +{ + return __raw_readl(addr); +} + +static u64 flash_read64(void *addr) +{ + /* No architectures currently implement __raw_readq() */ + return *(volatile u64 *)addr; +} /*----------------------------------------------------------------------- - * Functions */ +#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info = 0; -typedef unsigned long flash_sect_t; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } -static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); -static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); -static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); -static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); -static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); -static void flash_read_jedec_ids (flash_info_t * info); -static int flash_detect_cfi (flash_info_t * info); -static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); -static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, - ulong tout, char *prompt); -ulong flash_get_size (ulong base, int banknum); -#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) -static flash_info_t *flash_get_info(ulong base); -#endif -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} #endif +unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) +{ + if (sect != (info->sector_count - 1)) + return info->start[sect + 1] - info->start[sect]; + else + return info->start[0] + info->size - info->start[sect]; +} + /*----------------------------------------------------------------------- * create an address based on the offset and the port width */ -inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset) +static inline void * +flash_map (flash_info_t * info, flash_sect_t sect, uint offset) { - return ((uchar *) (info->start[sect] + (offset * info->portwidth))); + unsigned int byte_offset = offset * info->portwidth; + + return map_physmem(info->start[sect] + byte_offset, + flash_sector_size(info, sect) - byte_offset, + MAP_NOCACHE); +} + +static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, + unsigned int offset, void *addr) +{ + unsigned int byte_offset = offset * info->portwidth; + + unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset); +} + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +{ + int i; + uchar *cp = (uchar *) cmdbuf; + +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) + for (i = info->portwidth; i > 0; i--) +#else + for (i = 1; i <= info->portwidth; i++) +#endif + *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; } #ifdef DEBUG /*----------------------------------------------------------------------- * Debug support */ -void print_longlong (char *str, unsigned long long data) +static void print_longlong (char *str, unsigned long long data) { int i; char *cp; @@ -224,28 +322,25 @@ void print_longlong (char *str, unsigned long long data) for (i = 0; i < 8; i++) sprintf (&str[i * 2], "%2.2x", *cp++); } -static void flash_printqry (flash_info_t * info, flash_sect_t sect) + +static void flash_printqry (struct cfi_qry *qry) { - cfiptr_t cptr; + u8 *p = (u8 *)qry; int x, y; - for (x = 0; x < 0x40; x += 16U / info->portwidth) { - cptr.cp = - flash_make_addr (info, sect, - x + FLASH_OFFSET_CFI_RESP); - debug ("%p : ", cptr.cp); + for (x = 0; x < sizeof(struct cfi_qry); x += 16) { + debug("%02x : ", x); + for (y = 0; y < 16; y++) + debug("%2.2x ", p[x + y]); + debug(" "); for (y = 0; y < 16; y++) { - debug ("%2.2x ", cptr.cp[y]); - } - debug (" "); - for (y = 0; y < 16; y++) { - if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) { - debug ("%c", cptr.cp[y]); - } else { - debug ("."); - } + unsigned char c = p[x + y]; + if (c >= 0x20 && c <= 0x7e) + debug("%c", c); + else + debug("."); } - debug ("\n"); + debug("\n"); } } #endif @@ -254,192 +349,608 @@ static void flash_printqry (flash_info_t * info, flash_sect_t sect) /*----------------------------------------------------------------------- * read a character at a port width address */ -inline uchar flash_read_uchar (flash_info_t * info, uint offset) +static inline uchar flash_read_uchar (flash_info_t * info, uint offset) { uchar *cp; + uchar retval; - cp = flash_make_addr (info, 0, offset); + cp = flash_map (info, 0, offset); #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) - return (cp[0]); + retval = flash_read8(cp); #else - return (cp[info->portwidth - 1]); + retval = flash_read8(cp + info->portwidth - 1); #endif + flash_unmap (info, 0, offset, cp); + return retval; } /*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. + * read a long word by picking the least significant byte of each maximum + * port size word. Swap for ppc format. */ -ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) +static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, + uint offset) { uchar *addr; - ushort retval; + ulong retval; #ifdef DEBUG int x; #endif - addr = flash_make_addr (info, sect, offset); + addr = flash_map (info, sect, offset); #ifdef DEBUG - debug ("ushort addr is at %p info->portwidth = %d\n", addr, + debug ("long addr is at %p info->portwidth = %d\n", addr, info->portwidth); - for (x = 0; x < 2 * info->portwidth; x++) { - debug ("addr[%x] = 0x%x\n", x, addr[x]); + for (x = 0; x < 4 * info->portwidth; x++) { + debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); } #endif #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) - retval = ((addr[(info->portwidth)] << 8) | addr[0]); + retval = ((flash_read8(addr) << 16) | + (flash_read8(addr + info->portwidth) << 24) | + (flash_read8(addr + 2 * info->portwidth)) | + (flash_read8(addr + 3 * info->portwidth) << 8)); #else - retval = ((addr[(2 * info->portwidth) - 1] << 8) | - addr[info->portwidth - 1]); + retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | + (flash_read8(addr + info->portwidth - 1) << 16) | + (flash_read8(addr + 4 * info->portwidth - 1) << 8) | + (flash_read8(addr + 3 * info->portwidth - 1))); #endif + flash_unmap(info, sect, offset, addr); - debug ("retval = 0x%x\n", retval); return retval; } -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maximum - * port size word. Swap for ppc format. +/* + * Write a proper sized command to the correct address */ -ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, + uint offset, uchar cmd) { - uchar *addr; - ulong retval; + void *addr; + cfiword_t cword; + + addr = flash_map (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, + cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + flash_write8(cword.c, addr); + break; + case FLASH_CFI_16BIT: + debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, + cmd, cword.w, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + flash_write16(cword.w, addr); + break; + case FLASH_CFI_32BIT: + debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, + cmd, cword.l, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + flash_write32(cword.l, addr); + break; + case FLASH_CFI_64BIT: #ifdef DEBUG - int x; + { + char str[20]; + + print_longlong (str, cword.ll); + + debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", + addr, cmd, str, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + } #endif - addr = flash_make_addr (info, sect, offset); + flash_write64(cword.ll, addr); + break; + } + + /* Ensure all the instructions are fully finished */ + sync(); + + flash_unmap(info, sect, offset, addr); +} +static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) +{ + flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); + flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal (flash_info_t * info, flash_sect_t sect, + uint offset, uchar cmd) +{ + void *addr; + cfiword_t cword; + int retval; + + addr = flash_map (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + + debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + debug ("is= %x %x\n", flash_read8(addr), cword.c); + retval = (flash_read8(addr) == cword.c); + break; + case FLASH_CFI_16BIT: + debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); + retval = (flash_read16(addr) == cword.w); + break; + case FLASH_CFI_32BIT: + debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l); + retval = (flash_read32(addr) == cword.l); + break; + case FLASH_CFI_64BIT: #ifdef DEBUG - debug ("long addr is at %p info->portwidth = %d\n", addr, - info->portwidth); - for (x = 0; x < 4 * info->portwidth; x++) { - debug ("addr[%x] = 0x%x\n", x, addr[x]); - } -#endif -#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) - retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | - (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); -#else - retval = (addr[(2 * info->portwidth) - 1] << 24) | - (addr[(info->portwidth) - 1] << 16) | - (addr[(4 * info->portwidth) - 1] << 8) | - addr[(3 * info->portwidth) - 1]; + { + char str1[20]; + char str2[20]; + + print_longlong (str1, flash_read64(addr)); + print_longlong (str2, cword.ll); + debug ("is= %s %s\n", str1, str2); + } #endif + retval = (flash_read64(addr) == cword.ll); + break; + default: + retval = 0; + break; + } + flash_unmap(info, sect, offset, addr); + return retval; } +/*----------------------------------------------------------------------- + */ +static int flash_isset (flash_info_t * info, flash_sect_t sect, + uint offset, uchar cmd) +{ + void *addr; + cfiword_t cword; + int retval; + + addr = flash_map (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((flash_read8(addr) & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((flash_read16(addr) & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((flash_read16(addr) & cword.l) == cword.l); + break; + case FLASH_CFI_64BIT: + retval = ((flash_read64(addr) & cword.ll) == cword.ll); + break; + default: + retval = 0; + break; + } + flash_unmap(info, sect, offset, addr); + + return retval; +} /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +static int flash_toggle (flash_info_t * info, flash_sect_t sect, + uint offset, uchar cmd) { - unsigned long size = 0; - int i; + void *addr; + cfiword_t cword; + int retval; -#ifdef CFG_FLASH_PROTECTION - char *s = getenv("unlock"); + addr = flash_map (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((flash_read8(addr) & cword.c) != + (flash_read8(addr) & cword.c)); + break; + case FLASH_CFI_16BIT: + retval = ((flash_read16(addr) & cword.w) != + (flash_read16(addr) & cword.w)); + break; + case FLASH_CFI_32BIT: + retval = ((flash_read32(addr) & cword.l) != + (flash_read32(addr) & cword.l)); + break; + case FLASH_CFI_64BIT: + retval = ((flash_read64(addr) & cword.ll) != + (flash_read64(addr) & cword.ll)); + break; + default: + retval = 0; + break; + } + flash_unmap(info, sect, offset, addr); + + return retval; +} + +/* + * flash_is_busy - check to see if the flash is busy + * + * This routine checks the status of the chip and returns true if the + * chip is busy. + */ +static int flash_is_busy (flash_info_t * info, flash_sect_t sect) +{ + int retval; + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: +#ifdef CONFIG_FLASH_CFI_LEGACY + case CFI_CMDSET_AMD_LEGACY: #endif + retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); + break; + default: + retval = 0; + } + debug ("flash_is_busy: %d\n", retval); + return retval; +} - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size (bank_base[i], i); - if (flash_info[i].flash_id == FLASH_UNKNOWN) { -#ifndef CFG_FLASH_QUIET_TEST - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i+1, flash_info[i].size, flash_info[i].size << 20); -#endif /* CFG_FLASH_QUIET_TEST */ - } -#ifdef CFG_FLASH_PROTECTION - else if ((s != NULL) && (strcmp(s, "yes") == 0)) { - /* - * Only the U-Boot image and it's environment is protected, - * all other sectors are unprotected (unlocked) if flash - * hardware protection is used (CFG_FLASH_PROTECTION) and - * the environment variable "unlock" is set to "yes". - */ - if (flash_info[i].legacy_unlock) { - int k; +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check (flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt) +{ + ulong start; - /* - * Disable legacy_unlock temporarily, since - * flash_real_protect would relock all other sectors - * again otherwise. - */ - flash_info[i].legacy_unlock = 0; +#if CFG_HZ != 1000 + tout *= CFG_HZ/1000; +#endif - /* - * Legacy unlocking (e.g. Intel J3) -> unlock only one - * sector. This will unlock all sectors. - */ - flash_real_protect (&flash_info[i], 0, 0); + /* Wait for command completion */ + start = get_timer (0); + while (flash_is_busy (info, sector)) { + if (get_timer (start) > tout) { + printf ("Flash %s timeout at address %lx data %lx\n", + prompt, info->start[sector], + flash_read_long (info, sector, 0)); + flash_write_cmd (info, sector, 0, info->cmd_reset); + return ERR_TIMOUT; + } + udelay (1); /* also triggers watchdog */ + } + return ERR_OK; +} - flash_info[i].legacy_unlock = 1; +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise + * do a full status check. + * + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt) +{ + int retcode; - /* - * Manually mark other sectors as unlocked (unprotected) - */ - for (k = 1; k < flash_info[i].sector_count; k++) - flash_info[i].protect[k] = 0; - } else { - /* - * No legancy unlocking -> unlock all sectors - */ - flash_protect (FLAG_PROTECT_CLEAR, - flash_info[i].start[0], - flash_info[i].start[0] + flash_info[i].size - 1, - &flash_info[i]); + retcode = flash_status_check (info, sector, tout, prompt); + switch (info->vendor) { + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + if ((retcode == ERR_OK) + && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf ("Flash %s error at address %lx\n", prompt, + info->start[sector]); + if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | + FLASH_STATUS_PSLBS)) { + puts ("Command Sequence Error.\n"); + } else if (flash_isset (info, sector, 0, + FLASH_STATUS_ECLBS)) { + puts ("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset (info, sector, 0, + FLASH_STATUS_PSLBS)) { + puts ("Locking Error\n"); + } + if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { + puts ("Block locked.\n"); + retcode = ERR_PROTECTED; } + if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) + puts ("Vpp Low Error.\n"); } -#endif /* CFG_FLASH_PROTECTION */ + flash_write_cmd (info, sector, 0, info->cmd_reset); + break; + default: + break; } + return retcode; +} - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CFG_MONITOR_BASE)); +/*----------------------------------------------------------------------- + */ +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) +{ +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) + unsigned short w; + unsigned int l; + unsigned long long ll; #endif - /* Environment protection ON by default */ -#ifdef CFG_ENV_IS_IN_FLASH - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - flash_get_info(CFG_ENV_ADDR)); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) + w = c; + w <<= 8; + cword->w = (cword->w >> 8) | w; +#else + cword->w = (cword->w << 8) | c; #endif - - /* Redundant environment protection ON by default */ -#ifdef CFG_ENV_ADDR_REDUND - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - flash_get_info(CFG_ENV_ADDR_REDUND)); + break; + case FLASH_CFI_32BIT: +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) + l = c; + l <<= 24; + cword->l = (cword->l >> 8) | l; +#else + cword->l = (cword->l << 8) | c; #endif - return (size); + break; + case FLASH_CFI_64BIT: +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) + ll = c; + ll <<= 56; + cword->ll = (cword->ll >> 8) | ll; +#else + cword->ll = (cword->ll << 8) | c; +#endif + break; + } +} + +/* loop through the sectors from the highest address when the passed + * address is greater or equal to the sector address we have a match + */ +static flash_sect_t find_sector (flash_info_t * info, ulong addr) +{ + flash_sect_t sector; + + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; } /*----------------------------------------------------------------------- */ -#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) -static flash_info_t *flash_get_info(ulong base) +static int flash_write_cfiword (flash_info_t * info, ulong dest, + cfiword_t cword) { - int i; - flash_info_t * info = 0; + void *dstaddr; + int flag; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) + dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE); + + /* Check if Flash is (sufficiently) erased */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((flash_read8(dstaddr) & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((flash_read16(dstaddr) & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((flash_read32(dstaddr) & cword.l) == cword.l); + break; + case FLASH_CFI_64BIT: + flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); + break; + default: + flag = 0; + break; + } + if (!flag) { + unmap_physmem(dstaddr, info->portwidth); + return 2; + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + switch (info->vendor) { + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); + break; + case CFI_CMDSET_AMD_EXTENDED: + case CFI_CMDSET_AMD_STANDARD: +#ifdef CONFIG_FLASH_CFI_LEGACY + case CFI_CMDSET_AMD_LEGACY: +#endif + flash_unlock_seq (info, 0); + flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); + break; + } + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flash_write8(cword.c, dstaddr); + break; + case FLASH_CFI_16BIT: + flash_write16(cword.w, dstaddr); + break; + case FLASH_CFI_32BIT: + flash_write32(cword.l, dstaddr); + break; + case FLASH_CFI_64BIT: + flash_write64(cword.ll, dstaddr); + break; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + unmap_physmem(dstaddr, info->portwidth); + + return flash_full_status_check (info, find_sector (info, dest), + info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, + int len) +{ + flash_sect_t sector; + int cnt; + int retcode; + void *src = cp; + void *dst = map_physmem(dest, len, MAP_NOCACHE); + + sector = find_sector (info, dest); + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + retcode = flash_status_check (info, sector, + info->buffer_write_tout, + "write to buffer"); + if (retcode == ERR_OK) { + /* reduce the number of loops by the width of + * the port */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + case FLASH_CFI_64BIT: + cnt = len >> 3; + break; + default: + retcode = ERR_INVAL; + goto out_unmap; + } + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flash_write8(flash_read8(src), dst); + src += 1, dst += 1; + break; + case FLASH_CFI_16BIT: + flash_write16(flash_read16(src), dst); + src += 2, dst += 2; + break; + case FLASH_CFI_32BIT: + flash_write32(flash_read32(src), dst); + src += 4, dst += 4; + break; + case FLASH_CFI_64BIT: + flash_write64(flash_read64(src), dst); + src += 8, dst += 8; + break; + default: + retcode = ERR_INVAL; + goto out_unmap; + } + } + flash_write_cmd (info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check ( + info, sector, info->buffer_write_tout, + "buffer write"); + } + + break; + + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + flash_unlock_seq(info,0); + flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER); + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + flash_write8(flash_read8(src), dst); + src += 1, dst += 1; + } break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + flash_write16(flash_read16(src), dst); + src += 2, dst += 2; + } + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + flash_write32(flash_read32(src), dst); + src += 4, dst += 4; + } + break; + case FLASH_CFI_64BIT: + cnt = len >> 3; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + flash_write64(flash_read64(src), dst); + src += 8, dst += 8; + } + break; + default: + retcode = ERR_INVAL; + goto out_unmap; + } + + flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check (info, sector, + info->buffer_write_tout, + "buffer write"); + break; + + default: + debug ("Unknown Command Set\n"); + retcode = ERR_INVAL; + break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; +out_unmap: + unmap_physmem(dst, len); + return retcode; } -#endif +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + /*----------------------------------------------------------------------- */ @@ -465,7 +976,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); } else { putc ('\n'); } @@ -476,18 +988,33 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) switch (info->vendor) { case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: - flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + flash_write_cmd (info, sect, 0, + FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sect, 0, + FLASH_CMD_BLOCK_ERASE); + flash_write_cmd (info, sect, 0, + FLASH_CMD_ERASE_CONFIRM); break; case CFI_CMDSET_AMD_STANDARD: case CFI_CMDSET_AMD_EXTENDED: flash_unlock_seq (info, sect); - flash_write_cmd (info, sect, AMD_ADDR_ERASE_START, - AMD_CMD_ERASE_START); + flash_write_cmd (info, sect, + info->addr_unlock1, + AMD_CMD_ERASE_START); flash_unlock_seq (info, sect); - flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR); + flash_write_cmd (info, sect, 0, + AMD_CMD_ERASE_SECTOR); + break; +#ifdef CONFIG_FLASH_CFI_LEGACY + case CFI_CMDSET_AMD_LEGACY: + flash_unlock_seq (info, 0); + flash_write_cmd (info, 0, info->addr_unlock1, + AMD_CMD_ERASE_START); + flash_unlock_seq (info, 0); + flash_write_cmd (info, sect, 0, + AMD_CMD_ERASE_SECTOR); break; +#endif default: debug ("Unkown flash vendor %d\n", info->vendor); @@ -516,10 +1043,15 @@ void flash_print_info (flash_info_t * info) return; } - printf ("CFI conformant FLASH (%d x %d)", + printf ("%s FLASH (%d x %d)", + info->name, (info->portwidth << 3), (info->chipwidth << 3)); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); + if (info->size < 1024*1024) + printf (" Size: %ld kB in %d Sectors\n", + info->size >> 10, info->sector_count); + else + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); printf (" "); switch (info->vendor) { case CFI_CMDSET_INTEL_STANDARD: @@ -534,6 +1066,11 @@ void flash_print_info (flash_info_t * info) case CFI_CMDSET_AMD_EXTENDED: printf ("AMD Extended"); break; +#ifdef CONFIG_FLASH_CFI_LEGACY + case CFI_CMDSET_AMD_LEGACY: + printf ("AMD Legacy"); + break; +#endif default: printf ("Unknown (%d)", info->vendor); break; @@ -547,7 +1084,8 @@ void flash_print_info (flash_info_t * info) info->erase_blk_tout, info->write_tout); if (info->buffer_size > 1) { - printf (" Buffer write timeout: %ld ms, buffer size: %d bytes\n", + printf (" Buffer write timeout: %ld ms, " + "buffer size: %d bytes\n", info->buffer_write_tout, info->buffer_size); } @@ -565,10 +1103,7 @@ void flash_print_info (flash_info_t * info) /* * Check if whole sector is erased */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; + size = flash_sector_size(info, i); erased = 1; flash = (volatile unsigned long *) info->start[i]; size = size >> 2; /* divide by 4 for longword access */ @@ -603,7 +1138,7 @@ void flash_print_info (flash_info_t * info) int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) { ulong wp; - ulong cp; + uchar *p; int aln; cfiword_t cword; int i, rc; @@ -612,26 +1147,28 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) int buffered_size; #endif /* get lower aligned address */ - /* get lower aligned address */ wp = (addr & ~(info->portwidth - 1)); /* handle unaligned start */ if ((aln = addr - wp) != 0) { cword.l = 0; - cp = wp; - for (i = 0; i < aln; ++i, ++cp) - flash_add_byte (info, &cword, (*(uchar *) cp)); + p = map_physmem(wp, info->portwidth, MAP_NOCACHE); + for (i = 0; i < aln; ++i) + flash_add_byte (info, &cword, flash_read8(p + i)); for (; (i < info->portwidth) && (cnt > 0); i++) { flash_add_byte (info, &cword, *src++); cnt--; - cp++; } - for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte (info, &cword, (*(uchar *) cp)); - if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + for (; (cnt == 0) && (i < info->portwidth); ++i) + flash_add_byte (info, &cword, flash_read8(p + i)); + + rc = flash_write_cfiword (info, wp, cword); + unmap_physmem(p, info->portwidth); + if (rc != 0) return rc; - wp = cp; + + wp += i; } /* handle the aligned part */ @@ -682,13 +1219,14 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) * handle unaligned tail bytes */ cword.l = 0; - for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { + p = map_physmem(wp, info->portwidth, MAP_NOCACHE); + for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { flash_add_byte (info, &cword, *src++); --cnt; } - for (; i < info->portwidth; ++i, ++cp) { - flash_add_byte (info, &cword, (*(uchar *) cp)); - } + for (; i < info->portwidth; ++i) + flash_add_byte (info, &cword, flash_read8(p + i)); + unmap_physmem(p, info->portwidth); return flash_write_cfiword (info, wp, cword); } @@ -740,10 +1278,11 @@ void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, uchar *dst; dst = buffer; - src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION); + src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION); flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); memcpy (dst, src + offset, len); flash_write_cmd (info, 0, 0, info->cmd_reset); + flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); } /* @@ -754,418 +1293,310 @@ void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, { uchar *src; - src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION); + src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION); flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); memcpy (buffer, src + offset, len); flash_write_cmd (info, 0, 0, info->cmd_reset); + flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); } #endif /* CFG_FLASH_PROTECTION */ -/* - * flash_is_busy - check to see if the flash is busy - * This routine checks the status of the chip and returns true if the chip is busy +/*----------------------------------------------------------------------- + * Reverse the order of the erase regions in the CFI QRY structure. + * This is needed for chips that are either a) correctly detected as + * top-boot, or b) buggy. */ -static int flash_is_busy (flash_info_t * info, flash_sect_t sect) +static void cfi_reverse_geometry(struct cfi_qry *qry) { - int retval; + unsigned int i, j; + u32 tmp; - switch (info->vendor) { - case CFI_CMDSET_INTEL_STANDARD: - case CFI_CMDSET_INTEL_EXTENDED: - retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); - break; - case CFI_CMDSET_AMD_STANDARD: - case CFI_CMDSET_AMD_EXTENDED: - retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); - break; - default: - retval = 0; + for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { + tmp = qry->erase_region_info[i]; + qry->erase_region_info[i] = qry->erase_region_info[j]; + qry->erase_region_info[j] = tmp; } - debug ("flash_is_busy: %d\n", retval); - return retval; } /*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. + * read jedec ids from device and set corresponding fields in info struct + * + * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct + * */ -static int flash_status_check (flash_info_t * info, flash_sect_t sector, - ulong tout, char *prompt) +static void cmdset_intel_read_jedec_ids(flash_info_t *info) { - ulong start; - -#if CFG_HZ != 1000 - tout *= CFG_HZ/1000; -#endif - - /* Wait for command completion */ - start = get_timer (0); - while (flash_is_busy (info, sector)) { - if (get_timer (start) > tout) { - printf ("Flash %s timeout at address %lx data %lx\n", - prompt, info->start[sector], - flash_read_long (info, sector, 0)); - flash_write_cmd (info, sector, 0, info->cmd_reset); - return ERR_TIMOUT; - } - udelay (1); /* also triggers watchdog */ - } - return ERR_OK; + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); + udelay(1000); /* some flash are slow to respond */ + info->manufacturer_id = flash_read_uchar (info, + FLASH_OFFSET_MANUFACTURER_ID); + info->device_id = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID); + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); } -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, - ulong tout, char *prompt) +static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) { - int retcode; + info->cmd_reset = FLASH_CMD_RESET; - retcode = flash_status_check (info, sector, tout, prompt); - switch (info->vendor) { - case CFI_CMDSET_INTEL_EXTENDED: - case CFI_CMDSET_INTEL_STANDARD: - if ((retcode == ERR_OK) - && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf ("Flash %s error at address %lx\n", prompt, - info->start[sector]); - if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { - puts ("Command Sequence Error.\n"); - } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { - puts ("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { - puts ("Locking Error\n"); - } - if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { - puts ("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) - puts ("Vpp Low Error.\n"); - } - flash_write_cmd (info, sector, 0, info->cmd_reset); - break; - default: - break; + cmdset_intel_read_jedec_ids(info); + flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); + +#ifdef CFG_FLASH_PROTECTION + /* read legacy lock/unlock bit from intel flash */ + if (info->ext_addr) { + info->legacy_unlock = flash_read_uchar (info, + info->ext_addr + 5) & 0x08; } - return retcode; +#endif + + return 0; } -/*----------------------------------------------------------------------- - */ -static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) +static void cmdset_amd_read_jedec_ids(flash_info_t *info) { -#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) - unsigned short w; - unsigned int l; - unsigned long long ll; -#endif - - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) - w = c; - w <<= 8; - cword->w = (cword->w >> 8) | w; -#else - cword->w = (cword->w << 8) | c; -#endif - break; - case FLASH_CFI_32BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) - l = c; - l <<= 24; - cword->l = (cword->l >> 8) | l; -#else - cword->l = (cword->l << 8) | c; -#endif - break; - case FLASH_CFI_64BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) - ll = c; - ll <<= 56; - cword->ll = (cword->ll >> 8) | ll; -#else - cword->ll = (cword->ll << 8) | c; -#endif - break; + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + flash_unlock_seq(info, 0); + flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); + udelay(1000); /* some flash are slow to respond */ + info->manufacturer_id = flash_read_uchar (info, + FLASH_OFFSET_MANUFACTURER_ID); + info->device_id = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID); + if (info->device_id == 0x7E) { + /* AMD 3-byte (expanded) device ids */ + info->device_id2 = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID2); + info->device_id2 <<= 8; + info->device_id2 |= flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID3); } + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); } - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) { - int i; - uchar *cp = (uchar *) cmdbuf; + info->cmd_reset = AMD_CMD_RESET; -#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) - for (i = info->portwidth; i > 0; i--) -#else - for (i = 1; i <= info->portwidth; i++) -#endif - *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; + cmdset_amd_read_jedec_ids(info); + flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); + + return 0; } -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +#ifdef CONFIG_FLASH_CFI_LEGACY +static void flash_read_jedec_ids (flash_info_t * info) { + info->manufacturer_id = 0; + info->device_id = 0; + info->device_id2 = 0; - volatile cfiptr_t addr; - cfiword_t cword; - - addr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd, - cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp, - cmd, cword.w, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - *addr.wp = cword.w; + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + flash_read_jedec_ids_intel(info); break; - case FLASH_CFI_32BIT: - debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp, - cmd, cword.l, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - *addr.lp = cword.l; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + flash_read_jedec_ids_amd(info); break; - case FLASH_CFI_64BIT: -#ifdef DEBUG - { - char str[20]; - - print_longlong (str, cword.ll); - - debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", - addr.llp, cmd, str, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - } -#endif - *addr.llp = cword.ll; + default: break; } - - /* Ensure all the instructions are fully finished */ - sync(); -} - -static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) -{ - flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START); - flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK); } /*----------------------------------------------------------------------- + * Call board code to request info about non-CFI flash. + * board_flash_get_legacy needs to fill in at least: + * info->portwidth, info->chipwidth and info->interface for Jedec probing. */ -static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static int flash_detect_legacy(ulong base, int banknum) { - cfiptr_t cptr; - cfiword_t cword; - int retval; - - cptr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); + flash_info_t *info = &flash_info[banknum]; - debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - debug ("is= %x %x\n", cptr.cp[0], cword.c); - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w); - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l); - retval = (cptr.lp[0] == cword.l); - break; - case FLASH_CFI_64BIT: -#ifdef DEBUG - { - char str1[20]; - char str2[20]; + if (board_flash_get_legacy(base, banknum, info)) { + /* board code may have filled info completely. If not, we + use JEDEC ID probing. */ + if (!info->vendor) { + int modes[] = { + CFI_CMDSET_AMD_STANDARD, + CFI_CMDSET_INTEL_STANDARD + }; + int i; + + for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) { + info->vendor = modes[i]; + info->start[0] = base; + if (info->portwidth == FLASH_CFI_8BIT + && info->interface == FLASH_CFI_X8X16) { + info->addr_unlock1 = 0x2AAA; + info->addr_unlock2 = 0x5555; + } else { + info->addr_unlock1 = 0x5555; + info->addr_unlock2 = 0x2AAA; + } + flash_read_jedec_ids(info); + debug("JEDEC PROBE: ID %x %x %x\n", + info->manufacturer_id, + info->device_id, + info->device_id2); + if (jedec_flash_match(info, base)) + break; + } + } - print_longlong (str1, cptr.llp[0]); - print_longlong (str2, cword.ll); - debug ("is= %s %s\n", str1, str2); + switch(info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + info->cmd_reset = FLASH_CMD_RESET; + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + case CFI_CMDSET_AMD_LEGACY: + info->cmd_reset = AMD_CMD_RESET; + break; } -#endif - retval = (cptr.llp[0] == cword.ll); - break; - default: - retval = 0; - break; + info->flash_id = FLASH_MAN_CFI; + return 1; } - return retval; + return 0; /* use CFI */ } - -/*----------------------------------------------------------------------- - */ -static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +#else +static inline int flash_detect_legacy(ulong base, int banknum) { - cfiptr_t cptr; - cfiword_t cword; - int retval; - - cptr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - case FLASH_CFI_64BIT: - retval = ((cptr.llp[0] & cword.ll) == cword.ll); - break; - default: - retval = 0; - break; - } - return retval; + return 0; /* use CFI */ } +#endif /*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf */ -static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static void flash_read_cfi (flash_info_t *info, void *buf, + unsigned int start, size_t len) { - cfiptr_t cptr; - cfiword_t cword; - int retval; + u8 *p = buf; + unsigned int i; - cptr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c)); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w)); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l)); - break; - case FLASH_CFI_64BIT: - retval = ((cptr.llp[0] & cword.ll) != - (cptr.llp[0] & cword.ll)); - break; - default: - retval = 0; - break; - } - return retval; + for (i = 0; i < len; i++) + p[i] = flash_read_uchar(info, start + i); } -/*----------------------------------------------------------------------- - * read jedec ids from device and set corresponding fields in info struct - * - * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct - * -*/ -static void flash_read_jedec_ids (flash_info_t * info) +static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { - info->manufacturer_id = 0; - info->device_id = 0; - info->device_id2 = 0; + int cfi_offset; - switch (info->vendor) { - case CFI_CMDSET_INTEL_STANDARD: - case CFI_CMDSET_INTEL_EXTENDED: - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); - udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); - info->device_id = flash_read_uchar (info, - FLASH_OFFSET_DEVICE_ID); - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - break; - case CFI_CMDSET_AMD_STANDARD: - case CFI_CMDSET_AMD_EXTENDED: - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); - flash_unlock_seq(info, 0); - flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID); - udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); - info->device_id = flash_read_uchar (info, - FLASH_OFFSET_DEVICE_ID); - if (info->device_id == 0x7E) { - /* AMD 3-byte (expanded) device ids */ - info->device_id2 = flash_read_uchar (info, - FLASH_OFFSET_DEVICE_ID2); - info->device_id2 <<= 8; - info->device_id2 |= flash_read_uchar (info, - FLASH_OFFSET_DEVICE_ID3); + flash_write_cmd (info, 0, 0, info->cmd_reset); + for (cfi_offset=0; + cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); + cfi_offset++) { + flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], + FLASH_CMD_CFI); + if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') + && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') + && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, + sizeof(struct cfi_qry)); + info->interface = le16_to_cpu(qry->interface_desc); + + info->cfi_offset = flash_offset_cfi[cfi_offset]; + debug ("device interface is %d\n", + info->interface); + debug ("found port %d chip %d ", + info->portwidth, info->chipwidth); + debug ("port %d bits chip %d bits\n", + info->portwidth << CFI_FLASH_SHIFT_WIDTH, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + + /* calculate command offsets as in the Linux driver */ + info->addr_unlock1 = 0x555; + info->addr_unlock2 = 0x2aa; + + /* + * modify the unlock address if we are + * in compatibility mode + */ + if ( /* x8/x16 in x8 mode */ + ((info->chipwidth == FLASH_CFI_BY8) && + (info->interface == FLASH_CFI_X8X16)) || + /* x16/x32 in x16 mode */ + ((info->chipwidth == FLASH_CFI_BY16) && + (info->interface == FLASH_CFI_X16X32))) + { + info->addr_unlock1 = 0xaaa; + info->addr_unlock2 = 0x555; + } + + info->name = "CFI conformant"; + return 1; } - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); - break; - default: - break; } + + return 0; } -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi (flash_info_t * info) +static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { - int cfi_offset; debug ("flash detect cfi\n"); for (info->portwidth = CFG_FLASH_CFI_WIDTH; info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd (info, 0, 0, info->cmd_reset); - for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi)/sizeof(uint); cfi_offset++) { - flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI); - if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { - info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE); - info->cfi_offset=flash_offset_cfi[cfi_offset]; - debug ("device interface is %d\n", - info->interface); - debug ("found port %d chip %d ", - info->portwidth, info->chipwidth); - debug ("port %d bits chip %d bits\n", - info->portwidth << CFI_FLASH_SHIFT_WIDTH, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - return 1; - } - } - } + info->chipwidth <<= 1) + if (__flash_detect_cfi(info, qry)) + return 1; } debug ("not found\n"); return 0; } /* + * Manufacturer-specific quirks. Add workarounds for geometry + * reversal, etc. here. + */ +static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) +{ + /* check if flash geometry needs reversal */ + if (qry->num_erase_regions > 1) { + /* reverse geometry if top boot part */ + if (info->cfi_version < 0x3131) { + /* CFI < 1.1, try to guess from device id */ + if ((info->device_id & 0x80) != 0) + cfi_reverse_geometry(qry); + } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + /* CFI >= 1.1, deduct from top/bottom flag */ + /* note: ext_addr is valid since cfi_version > 0 */ + cfi_reverse_geometry(qry); + } + } +} + +static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) +{ + int reverse_geometry = 0; + + /* Check the "top boot" bit in the PRI */ + if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) + reverse_geometry = 1; + + /* AT49BV6416(T) list the erase regions in the wrong order. + * However, the device ID is identical with the non-broken + * AT49BV642D since u-boot only reads the low byte (they + * differ in the high byte.) So leave out this fixup for now. + */ +#if 0 + if (info->device_id == 0xd6 || info->device_id == 0xd2) + reverse_geometry = !reverse_geometry; +#endif + + if (reverse_geometry) + cfi_reverse_geometry(qry); +} + +/* * The following code cannot be run from FLASH! * */ @@ -1180,7 +1611,7 @@ ulong flash_get_size (ulong base, int banknum) uchar num_erase_regions; int erase_region_size; int erase_region_count; - int geometry_reversed = 0; + struct cfi_qry qry; info->ext_addr = 0; info->cfi_version = 0; @@ -1190,56 +1621,50 @@ ulong flash_get_size (ulong base, int banknum) info->start[0] = base; - if (flash_detect_cfi (info)) { - info->vendor = flash_read_ushort (info, 0, - FLASH_OFFSET_PRIMARY_VENDOR); - flash_read_jedec_ids (info); - flash_write_cmd (info, 0, info->cfi_offset, FLASH_CMD_CFI); - num_erase_regions = flash_read_uchar (info, - FLASH_OFFSET_NUM_ERASE_REGIONS); - info->ext_addr = flash_read_ushort (info, 0, - FLASH_OFFSET_EXT_QUERY_T_P_ADDR); + if (flash_detect_cfi (info, &qry)) { + info->vendor = le16_to_cpu(qry.p_id); + info->ext_addr = le16_to_cpu(qry.p_adr); + num_erase_regions = qry.num_erase_regions; + if (info->ext_addr) { info->cfi_version = (ushort) flash_read_uchar (info, info->ext_addr + 3) << 8; info->cfi_version |= (ushort) flash_read_uchar (info, info->ext_addr + 4); } + #ifdef DEBUG - flash_printqry (info, 0); + flash_printqry (&qry); #endif + switch (info->vendor) { case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: - default: - info->cmd_reset = FLASH_CMD_RESET; -#ifdef CFG_FLASH_PROTECTION - /* read legacy lock/unlock bit from intel flash */ - if (info->ext_addr) { - info->legacy_unlock = flash_read_uchar (info, - info->ext_addr + 5) & 0x08; - } -#endif + cmdset_intel_init(info, &qry); break; case CFI_CMDSET_AMD_STANDARD: case CFI_CMDSET_AMD_EXTENDED: - info->cmd_reset = AMD_CMD_RESET; - /* check if flash geometry needs reversal */ - if (num_erase_regions <= 1) - break; - /* reverse geometry if top boot part */ - if (info->cfi_version < 0x3131) { - /* CFI < 1.1, try to guess from device id */ - if ((info->device_id & 0x80) != 0) { - geometry_reversed = 1; - } - break; - } - /* CFI >= 1.1, deduct from top/bottom flag */ - /* note: ext_addr is valid since cfi_version > 0 */ - if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { - geometry_reversed = 1; - } + cmdset_amd_init(info, &qry); + break; + default: + printf("CFI: Unknown command set 0x%x\n", + info->vendor); + /* + * Unfortunately, this means we don't know how + * to get the chip back to Read mode. Might + * as well try an Intel-style reset... + */ + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + return 0; + } + + /* Do manufacturer-specific fixups */ + switch (info->manufacturer_id) { + case 0x0001: + flash_fixup_amd(info, &qry); + break; + case 0x001f: + flash_fixup_atmel(info, &qry); break; } @@ -1267,26 +1692,27 @@ ulong flash_get_size (ulong base, int banknum) num_erase_regions, NUM_ERASE_REGIONS); break; } - if (geometry_reversed) - tmp = flash_read_long (info, 0, - FLASH_OFFSET_ERASE_REGIONS + - (num_erase_regions - 1 - i) * 4); - else - tmp = flash_read_long (info, 0, - FLASH_OFFSET_ERASE_REGIONS + - i * 4); + + tmp = le32_to_cpu(qry.erase_region_info[i]); + debug("erase region %u: 0x%08lx\n", i, tmp); + + erase_region_count = (tmp & 0xffff) + 1; + tmp >>= 16; erase_region_size = (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) + 1; debug ("erase_region_count = %d erase_region_size = %d\n", erase_region_count, erase_region_size); for (j = 0; j < erase_region_count; j++) { + if (sect_cnt >= CFG_MAX_FLASH_SECT) { + printf("ERROR: too many flash sectors\n"); + break; + } info->start[sect_cnt] = sector; sector += (erase_region_size * size_ratio); /* - * Only read protection status from supported devices (intel...) + * Only read protection status from + * supported devices (intel...) */ switch (info->vendor) { case CFI_CMDSET_INTEL_EXTENDED: @@ -1297,7 +1723,8 @@ ulong flash_get_size (ulong base, int banknum) FLASH_STATUS_PROTECT); break; default: - info->protect[sect_cnt] = 0; /* default: not protected */ + /* default: not protected */ + info->protect[sect_cnt] = 0; } sect_cnt++; @@ -1305,20 +1732,27 @@ ulong flash_get_size (ulong base, int banknum) } info->sector_count = sect_cnt; + info->size = 1 << qry.dev_size; /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); - tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) * - (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)); - info->buffer_write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ - tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) * - (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT)); - info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ + info->size *= size_ratio; + info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); + tmp = 1 << qry.block_erase_timeout_typ; + info->erase_blk_tout = tmp * + (1 << qry.block_erase_timeout_max); + tmp = (1 << qry.buf_write_timeout_typ) * + (1 << qry.buf_write_timeout_max); + + /* round up when converting to ms */ + info->buffer_write_tout = (tmp + 999) / 1000; + tmp = (1 << qry.word_write_timeout_typ) * + (1 << qry.word_write_timeout_max); + /* round up when converting to ms */ + info->write_tout = (tmp + 999) / 1000; info->flash_id = FLASH_MAN_CFI; - if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { - info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ + if ((info->interface == FLASH_CFI_X8X16) && + (info->chipwidth == FLASH_CFI_BY8)) { + /* XXX - Need to test on x8/x16 in parallel. */ + info->portwidth >>= 1; } } @@ -1326,203 +1760,106 @@ ulong flash_get_size (ulong base, int banknum) return (info->size); } -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static flash_sect_t find_sector (flash_info_t * info, ulong addr) -{ - flash_sect_t sector; - - for (sector = info->sector_count - 1; sector >= 0; sector--) { - if (addr >= info->start[sector]) - break; - } - return sector; -} - /*----------------------------------------------------------------------- */ -static int flash_write_cfiword (flash_info_t * info, ulong dest, - cfiword_t cword) +unsigned long flash_init (void) { - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr (info, 0, 0); - cptr.cp = (uchar *) dest; - - /* Check if Flash is (sufficiently) erased */ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - case FLASH_CFI_64BIT: - flag = ((cptr.llp[0] & cword.ll) == cword.ll); - break; - default: - return 2; - } - if (!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + unsigned long size = 0; + int i; - switch (info->vendor) { - case CFI_CMDSET_INTEL_EXTENDED: - case CFI_CMDSET_INTEL_STANDARD: - flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); - break; - case CFI_CMDSET_AMD_EXTENDED: - case CFI_CMDSET_AMD_STANDARD: - flash_unlock_seq (info, 0); - flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE); - break; - } +#ifdef CFG_FLASH_PROTECTION + char *s = getenv("unlock"); +#endif - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - case FLASH_CFI_64BIT: - cptr.llp[0] = cword.ll; - break; - } + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); + if (!flash_detect_legacy (bank_base[i], i)) + flash_get_size (bank_base[i], i); + size += flash_info[i].size; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { +#ifndef CFG_FLASH_QUIET_TEST + printf ("## Unknown FLASH on Bank %d " + "- Size = 0x%08lx = %ld MB\n", + i+1, flash_info[i].size, + flash_info[i].size << 20); +#endif /* CFG_FLASH_QUIET_TEST */ + } +#ifdef CFG_FLASH_PROTECTION + else if ((s != NULL) && (strcmp(s, "yes") == 0)) { + /* + * Only the U-Boot image and it's environment + * is protected, all other sectors are + * unprotected (unlocked) if flash hardware + * protection is used (CFG_FLASH_PROTECTION) + * and the environment variable "unlock" is + * set to "yes". + */ + if (flash_info[i].legacy_unlock) { + int k; - return flash_full_status_check (info, find_sector (info, dest), - info->write_tout, "write"); -} + /* + * Disable legacy_unlock temporarily, + * since flash_real_protect would + * relock all other sectors again + * otherwise. + */ + flash_info[i].legacy_unlock = 0; -#ifdef CFG_FLASH_USE_BUFFER_WRITE + /* + * Legacy unlocking (e.g. Intel J3) -> + * unlock only one sector. This will + * unlock all sectors. + */ + flash_real_protect (&flash_info[i], 0, 0); -static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, - int len) -{ - flash_sect_t sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; + flash_info[i].legacy_unlock = 1; - switch (info->vendor) { - case CFI_CMDSET_INTEL_STANDARD: - case CFI_CMDSET_INTEL_EXTENDED: - src.cp = cp; - dst.cp = (uchar *) dest; - sector = find_sector (info, dest); - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if ((retcode = flash_status_check (info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - /* reduce the number of loops by the width of the port */ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - case FLASH_CFI_64BIT: - cnt = len >> 3; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - case FLASH_CFI_64BIT: - *dst.llp++ = *src.llp++; - break; - default: - return ERR_INVAL; - break; - } + /* + * Manually mark other sectors as + * unlocked (unprotected) + */ + for (k = 1; k < flash_info[i].sector_count; k++) + flash_info[i].protect[k] = 0; + } else { + /* + * No legancy unlocking -> unlock all sectors + */ + flash_protect (FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + + flash_info[i].size - 1, + &flash_info[i]); } - flash_write_cmd (info, sector, 0, - FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check (info, sector, - info->buffer_write_tout, - "buffer write"); } - return retcode; - - case CFI_CMDSET_AMD_STANDARD: - case CFI_CMDSET_AMD_EXTENDED: - src.cp = cp; - dst.cp = (uchar *) dest; - sector = find_sector (info, dest); - - flash_unlock_seq(info,0); - flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER); +#endif /* CFG_FLASH_PROTECTION */ + } - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) *dst.lp++ = *src.lp++; - break; - case FLASH_CFI_64BIT: - cnt = len >> 3; - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) *dst.llp++ = *src.llp++; - break; - default: - return ERR_INVAL; - } + /* Monitor protection ON by default */ +#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CFG_MONITOR_BASE)); +#endif - flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check (info, sector, info->buffer_write_tout, - "buffer write"); - return retcode; + /* Environment protection ON by default */ +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + flash_get_info(CFG_ENV_ADDR)); +#endif - default: - debug ("Unknown Command Set\n"); - return ERR_INVAL; - } + /* Redundant environment protection ON by default */ +#ifdef CFG_ENV_ADDR_REDUND + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + flash_get_info(CFG_ENV_ADDR_REDUND)); +#endif + return (size); } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ #endif /* CFG_FLASH_CFI */ diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c new file mode 100644 index 0000000000..94e87cbf00 --- /dev/null +++ b/drivers/mtd/jedec_flash.c @@ -0,0 +1,311 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, <michael@schwingen.org> + * + * based in great part on jedec_probe.c from linux kernel: + * (C) 2000 Red Hat. GPL'd. + * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* The DEBUG define must be before common to enable debugging */ +/*#define DEBUG*/ + +#include <common.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/byteorder.h> +#include <environment.h> + +#define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY + +/* Manufacturers */ +#define MANUFACTURER_AMD 0x0001 +#define MANUFACTURER_SST 0x00BF + +/* AMD */ +#define AM29DL800BB 0x22C8 +#define AM29DL800BT 0x224A + +#define AM29F800BB 0x2258 +#define AM29F800BT 0x22D6 +#define AM29LV400BB 0x22BA +#define AM29LV400BT 0x22B9 +#define AM29LV800BB 0x225B +#define AM29LV800BT 0x22DA +#define AM29LV160DT 0x22C4 +#define AM29LV160DB 0x2249 +#define AM29F017D 0x003D +#define AM29F016D 0x00AD +#define AM29F080 0x00D5 +#define AM29F040 0x00A4 +#define AM29LV040B 0x004F +#define AM29F032B 0x0041 +#define AM29F002T 0x00B0 + +/* SST */ +#define SST39LF800 0x2781 +#define SST39LF160 0x2782 +#define SST39VF1601 0x234b +#define SST39LF512 0x00D4 +#define SST39LF010 0x00D5 +#define SST39LF020 0x00D6 +#define SST39LF040 0x00D7 +#define SST39SF010A 0x00B5 +#define SST39SF020A 0x00B6 + + +/* + * Unlock address sets for AMD command sets. + * Intel command sets use the MTD_UADDR_UNNECESSARY. + * Each identifier, except MTD_UADDR_UNNECESSARY, and + * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. + * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure + * initialization need not require initializing all of the + * unlock addresses for all bit widths. + */ +enum uaddr { + MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ + MTD_UADDR_0x0555_0x02AA, + MTD_UADDR_0x0555_0x0AAA, + MTD_UADDR_0x5555_0x2AAA, + MTD_UADDR_0x0AAA_0x0555, + MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ + MTD_UADDR_UNNECESSARY, /* Does not require any address */ +}; + + +struct unlock_addr { + u32 addr1; + u32 addr2; +}; + + +/* + * I don't like the fact that the first entry in unlock_addrs[] + * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, + * should not be used. The problem is that structures with + * initializers have extra fields initialized to 0. It is _very_ + * desireable to have the unlock address entries for unsupported + * data widths automatically initialized - that means that + * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here + * must go unused. + */ +static const struct unlock_addr unlock_addrs[] = { + [MTD_UADDR_NOT_SUPPORTED] = { + .addr1 = 0xffff, + .addr2 = 0xffff + }, + + [MTD_UADDR_0x0555_0x02AA] = { + .addr1 = 0x0555, + .addr2 = 0x02aa + }, + + [MTD_UADDR_0x0555_0x0AAA] = { + .addr1 = 0x0555, + .addr2 = 0x0aaa + }, + + [MTD_UADDR_0x5555_0x2AAA] = { + .addr1 = 0x5555, + .addr2 = 0x2aaa + }, + + [MTD_UADDR_0x0AAA_0x0555] = { + .addr1 = 0x0AAA, + .addr2 = 0x0555 + }, + + [MTD_UADDR_DONT_CARE] = { + .addr1 = 0x0000, /* Doesn't matter which address */ + .addr2 = 0x0000 /* is used - must be last entry */ + }, + + [MTD_UADDR_UNNECESSARY] = { + .addr1 = 0x0000, + .addr2 = 0x0000 + } +}; + + +struct amd_flash_info { + const __u16 mfr_id; + const __u16 dev_id; + const char *name; + const int DevSize; + const int NumEraseRegions; + const int CmdSet; + const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */ + const ulong regions[6]; +}; + +#define ERASEINFO(size,blocks) (size<<8)|(blocks-1) + +#define SIZE_64KiB 16 +#define SIZE_128KiB 17 +#define SIZE_256KiB 18 +#define SIZE_512KiB 19 +#define SIZE_1MiB 20 +#define SIZE_2MiB 21 +#define SIZE_4MiB 22 +#define SIZE_8MiB 23 + +static const struct amd_flash_info jedec_table[] = { +#ifdef CFG_FLASH_LEGACY_256Kx8 + { + .mfr_id = MANUFACTURER_SST, + .dev_id = SST39LF020, + .name = "SST 39LF020", + .uaddr = { + [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ + }, + .DevSize = SIZE_256KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x01000,64), + } + }, +#endif +#ifdef CFG_FLASH_LEGACY_512Kx8 + { + .mfr_id = MANUFACTURER_AMD, + .dev_id = AM29LV040B, + .name = "AMD AM29LV040B", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, + { + .mfr_id = MANUFACTURER_SST, + .dev_id = SST39LF040, + .name = "SST 39LF040", + .uaddr = { + [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x01000,128), + } + }, +#endif +}; + + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + + +static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base) +{ + int i,j; + int sect_cnt; + int size_ratio; + int total_size; + enum uaddr uaddr_idx; + + size_ratio = info->portwidth / info->chipwidth; + + debug("Found JEDEC Flash: %s\n", jedec_entry->name); + info->vendor = jedec_entry->CmdSet; + /* Todo: do we need device-specific timeouts? */ + info->erase_blk_tout = 30000; + info->buffer_write_tout = 1000; + info->write_tout = 100; + info->name = jedec_entry->name; + + /* copy unlock addresses from device table to CFI info struct. This + is just here because the addresses are in the table anyway - if + the flash is not detected due to wrong unlock addresses, + flash_detect_legacy would have to try all of them before we even + get here. */ + switch(info->chipwidth) { + case FLASH_CFI_8BIT: + uaddr_idx = jedec_entry->uaddr[0]; + break; + case FLASH_CFI_16BIT: + uaddr_idx = jedec_entry->uaddr[1]; + break; + case FLASH_CFI_32BIT: + uaddr_idx = jedec_entry->uaddr[2]; + break; + default: + uaddr_idx = MTD_UADDR_NOT_SUPPORTED; + break; + } + + debug("unlock address index %d\n", uaddr_idx); + info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1; + info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2; + debug("unlock addresses are 0x%x/0x%x\n", info->addr_unlock1, info->addr_unlock2); + + sect_cnt = 0; + total_size = 0; + for (i = 0; i < jedec_entry->NumEraseRegions; i++) { + ulong erase_region_size = jedec_entry->regions[i] >> 8; + ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1; + + total_size += erase_region_size * erase_region_count; + debug ("erase_region_count = %d erase_region_size = %d\n", + erase_region_count, erase_region_size); + for (j = 0; j < erase_region_count; j++) { + if (sect_cnt >= CFG_MAX_FLASH_SECT) { + printf("ERROR: too many flash sectors\n"); + break; + } + info->start[sect_cnt] = base; + base += (erase_region_size * size_ratio); + sect_cnt++; + } + } + info->sector_count = sect_cnt; + info->size = total_size * size_ratio; +} + +/*----------------------------------------------------------------------- + * match jedec ids against table. If a match is found, fill flash_info entry + */ +int jedec_flash_match(flash_info_t *info, ulong base) +{ + int ret = 0; + int i; + ulong mask = 0xFFFF; + if (info->chipwidth == 1) + mask = 0xFF; + + for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { + if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) && + (jedec_table[i].dev_id & mask) == (info->device_id & mask)) { + fill_info(info, &jedec_table[i], base); + ret = 1; + break; + } + } + return ret; +} diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 1e778844a5..68e45e17b3 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -112,6 +112,29 @@ fsl_pci_init(struct pci_controller *hose) pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); enabled = ltssm >= PCI_LTSSM_L0; +#ifdef CONFIG_FSL_PCIE_RESET + if (ltssm == 1) { + int i; + debug("....PCIe link error. " + "LTSSM=0x%02x.", ltssm); + pci->pdb_stat |= 0x08000000; /* assert PCIe reset */ + temp32 = pci->pdb_stat; + udelay(100); + debug(" Asserting PCIe reset @%x = %x\n", + &pci->pdb_stat, pci->pdb_stat); + pci->pdb_stat &= ~0x08000000; /* clear reset */ + asm("sync;isync"); + for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { + pci_hose_read_config_word(hose, dev, PCI_LTSSM, + <ssm); + udelay(1000); + debug("....PCIe link error. " + "LTSSM=0x%02x.\n", ltssm); + } + enabled = ltssm >= PCI_LTSSM_L0; + } +#endif + if (!enabled) { debug("....PCIE link error. Skipping scan." "LTSSM=0x%02x\n", ltssm); diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 55528c889e..bba1ab8510 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -30,6 +30,7 @@ COBJS-y += pxa_pcmcia.o COBJS-y += rpx_pcmcia.o COBJS-y += ti_pci1410a.o COBJS-y += tqm8xx_pcmcia.o +COBJS-y += marubun_pcmcia.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/pcmcia/marubun_pcmcia.c b/drivers/pcmcia/marubun_pcmcia.c new file mode 100644 index 0000000000..7b112af922 --- /dev/null +++ b/drivers/pcmcia/marubun_pcmcia.c @@ -0,0 +1,113 @@ +/* + * Marubun MR-SHPC-01 PCMCIA controller device driver + * + * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <config.h> +#include <pcmcia.h> +#include <asm/io.h> + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CONFIG_PCMCIA +#endif + +#if defined(CONFIG_PCMCIA) \ + && (defined(CONFIG_MARUBUN_PCCARD)) + +/* MR-SHPC-01 register */ +#define MRSHPC_MODE (CFG_MARUBUN_MRSHPC + 4) +#define MRSHPC_OPTION (CFG_MARUBUN_MRSHPC + 6) +#define MRSHPC_CSR (CFG_MARUBUN_MRSHPC + 8) +#define MRSHPC_ISR (CFG_MARUBUN_MRSHPC + 10) +#define MRSHPC_ICR (CFG_MARUBUN_MRSHPC + 12) +#define MRSHPC_CPWCR (CFG_MARUBUN_MRSHPC + 14) +#define MRSHPC_MW0CR1 (CFG_MARUBUN_MRSHPC + 16) +#define MRSHPC_MW1CR1 (CFG_MARUBUN_MRSHPC + 18) +#define MRSHPC_IOWCR1 (CFG_MARUBUN_MRSHPC + 20) +#define MRSHPC_MW0CR2 (CFG_MARUBUN_MRSHPC + 22) +#define MRSHPC_MW1CR2 (CFG_MARUBUN_MRSHPC + 24) +#define MRSHPC_IOWCR2 (CFG_MARUBUN_MRSHPC + 26) +#define MRSHPC_CDCR (CFG_MARUBUN_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (CFG_MARUBUN_MRSHPC + 30) + +int pcmcia_on (void) +{ + printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + /* Init */ + outw( 0x0000 , MRSHPC_MODE ); + + if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */ + if ((inw(MRSHPC_CSR) & 0x0080) == 0){ + outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ + }else{ + outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */ + } + udelay( 100000 ); /* wait for power on */ + }else{ + return 1; + } + /* + * PC-Card window open + * flag == COMMON/ATTRIBUTE/IO + */ + /* common window open */ + outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */ + if ((inw(MRSHPC_CSR) & 0x4000) != 0) + outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */ + else + outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */ + + /* attribute window open */ + outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */ + if ((inw(MRSHPC_CSR) & 0x4000) != 0) + outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */ + else + outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */ + + /* I/O window open */ + outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */ + outw(0x0008,MRSHPC_CDCR); /* I/O card mode */ + if ((inw(MRSHPC_CSR) & 0x4000) != 0) + outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */ + else + outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */ + + outw(0x0000,MRSHPC_ISR); + outw(0x2000,MRSHPC_ICR); + outb(0x00,(CFG_MARUBUN_MW2 + 0x206)); + outb(0x42,(CFG_MARUBUN_MW2 + 0x200)); + + return 0; +} + +int pcmcia_off (void) +{ + printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + return 0; +} + +#endif /* CONFIG_MARUBUN_PCCARD */ diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 1d6016ef87..e5ee611350 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -40,6 +40,7 @@ COBJS-y += ds164x.o COBJS-y += ds174x.o COBJS-y += ds3231.o COBJS-y += m41t11.o +COBJS-y += m41t60.o COBJS-y += max6900.o COBJS-y += m48t35ax.o COBJS-y += mc146818.o diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c new file mode 100644 index 0000000000..7c80143e68 --- /dev/null +++ b/drivers/rtc/m41t60.c @@ -0,0 +1,261 @@ +/* + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org + * + * based on rtc/m41t11.c which is ... + * + * (C) Copyright 2002 + * Andrew May, Viasat Inc, amay@viasat.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * STMicroelectronics M41T60 serial access real-time clock + */ + +/* #define DEBUG 1 */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> + +#if defined(CONFIG_RTC_M41T60) && defined(CFG_I2C_RTC_ADDR) && \ + defined(CONFIG_CMD_DATE) + +static unsigned bcd2bin(uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd(unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +/* + * Convert between century and "century bits" (CB1 and CB0). These routines + * assume years are in the range 1900 - 2299. + */ + +static unsigned char year2cb(unsigned const year) +{ + if (year < 1900 || year >= 2300) + printf("M41T60 RTC: year %d out of range\n", year); + + return (year / 100) & 0x3; +} + +static unsigned cb2year(unsigned const cb) +{ + return 1900 + 100 * ((cb + 1) & 0x3); +} + +/* + * These are simple defines for the chip local to here so they aren't too + * verbose. DAY/DATE aren't nice but that is how they are on the data sheet. + */ +#define RTC_SEC 0x0 +#define RTC_MIN 0x1 +#define RTC_HOUR 0x2 +#define RTC_DAY 0x3 +#define RTC_DATE 0x4 +#define RTC_MONTH 0x5 +#define RTC_YEAR 0x6 + +#define RTC_REG_CNT 7 + +#define RTC_CTRL 0x7 + +#if defined(DEBUG) +static void rtc_dump(char const *const label) +{ + uchar data[8]; + + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + printf("I2C read failed in rtc_dump()\n"); + return; + } + printf("RTC dump %s: %02X-%02X-%02X-%02X-%02X-%02X-%02X-%02X\n", + label, data[0], data[1], data[2], data[3], + data[4], data[5], data[6], data[7]); +} +#else +#define rtc_dump(label) +#endif + +static uchar *rtc_validate(void) +{ + /* + * This routine uses the OUT bit and the validity of the time values to + * determine whether there has been an initial power-up since the last + * time the routine was run. It assumes that the OUT bit is not being + * used for any other purpose. + */ + static const uchar daysInMonth[0x13] = { + 0x00, 0x31, 0x29, 0x31, 0x30, 0x31, 0x30, 0x31, + 0x31, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x30, 0x31 + }; + static uchar data[8]; + uchar min, date, month, years; + + rtc_dump("begin validate"); + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + printf("I2C read failed in rtc_validate()\n"); + return 0; + } + /* + * If the OUT bit is "1", there has been a loss of power, so stop the + * oscillator so it can be "kick-started" as per data sheet. + */ + if (0x00 != (data[RTC_CTRL] & 0x80)) { + printf("M41T60 RTC clock lost power.\n"); + data[RTC_SEC] = 0x80; + if (i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) { + printf("I2C write failed in rtc_validate()\n"); + return 0; + } + } + /* + * If the oscillator is stopped or the date is invalid, then reset the + * OUT bit to "0", reset the date registers, and start the oscillator. + */ + min = data[RTC_MIN] & 0x7F; + date = data[RTC_DATE]; + month = data[RTC_MONTH] & 0x3F; + years = data[RTC_YEAR]; + if (0x59 < data[RTC_SEC] || 0x09 < (data[RTC_SEC] & 0x0F) || + 0x59 < min || 0x09 < (min & 0x0F) || + 0x23 < data[RTC_HOUR] || 0x09 < (data[RTC_HOUR] & 0x0F) || + 0x07 < data[RTC_DAY] || 0x00 == data[RTC_DAY] || + 0x12 < month || + 0x99 < years || 0x09 < (years & 0x0F) || + daysInMonth[month] < date || 0x09 < (date & 0x0F) || 0x00 == date || + (0x29 == date && 0x02 == month && + ((0x00 != (years & 0x03)) || + (0x00 == years && 0x00 != (data[RTC_MONTH] & 0xC0))))) { + printf("Resetting M41T60 RTC clock.\n"); + /* + * Set to 00:00:00 1900-01-01 (Monday) + */ + data[RTC_SEC] = 0x00; + data[RTC_MIN] &= 0x80; /* preserve OFIE bit */ + data[RTC_HOUR] = 0x00; + data[RTC_DAY] = 0x02; + data[RTC_DATE] = 0x01; + data[RTC_MONTH] = 0xC1; + data[RTC_YEAR] = 0x00; + data[RTC_CTRL] &= 0x7F; /* reset OUT bit */ + + if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + printf("I2C write failed in rtc_validate()\n"); + return 0; + } + } + return data; +} + +void rtc_get(struct rtc_time *tmp) +{ + uchar const *const data = rtc_validate(); + + if (!data) + return; + + tmp->tm_sec = bcd2bin(data[RTC_SEC] & 0x7F); + tmp->tm_min = bcd2bin(data[RTC_MIN] & 0x7F); + tmp->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3F); + tmp->tm_mday = bcd2bin(data[RTC_DATE] & 0x3F); + tmp->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1F); + tmp->tm_year = cb2year(data[RTC_MONTH] >> 6) + bcd2bin(data[RTC_YEAR]); + tmp->tm_wday = bcd2bin(data[RTC_DAY] & 0x07) - 1; + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +void rtc_set(struct rtc_time *tmp) +{ + uchar *const data = rtc_validate(); + + if (!data) + return; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + data[RTC_SEC] = (data[RTC_SEC] & 0x80) | (bin2bcd(tmp->tm_sec) & 0x7F); + data[RTC_MIN] = (data[RTC_MIN] & 0X80) | (bin2bcd(tmp->tm_min) & 0X7F); + data[RTC_HOUR] = bin2bcd(tmp->tm_hour) & 0x3F; + data[RTC_DATE] = bin2bcd(tmp->tm_mday) & 0x3F; + data[RTC_MONTH] = bin2bcd(tmp->tm_mon) & 0x1F; + data[RTC_YEAR] = bin2bcd(tmp->tm_year % 100); + data[RTC_MONTH] |= year2cb(tmp->tm_year) << 6; + data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07; + if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) { + printf("I2C write failed in rtc_set()\n"); + return; + } +} + +void rtc_reset(void) +{ + uchar *const data = rtc_validate(); + char const *const s = getenv("rtccal"); + + if (!data) + return; + + rtc_dump("begin reset"); + /* + * If environmental variable "rtccal" is present, it must be a hex value + * between 0x00 and 0x3F, inclusive. The five least-significan bits + * represent the calibration magnitude, and the sixth bit the sign bit. + * If these do not match the contents of the hardware register, that + * register is updated. The value 0x00 imples no correction. Consult + * the M41T60 documentation for further details. + */ + if (s) { + unsigned long const l = simple_strtoul(s, 0, 16); + + if (l <= 0x3F) { + if ((data[RTC_CTRL] & 0x3F) != l) { + printf("Setting RTC calibration to 0x%02X\n", + l); + data[RTC_CTRL] &= 0xC0; + data[RTC_CTRL] |= (uchar) l; + } + } else + printf("environment parameter \"rtccal\" not valid: " + "ignoring\n"); + } + /* + * Turn off frequency test. + */ + data[RTC_CTRL] &= 0xBF; + if (i2c_write(CFG_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) { + printf("I2C write failed in rtc_reset()\n"); + return; + } + rtc_dump("end reset"); +} +#endif /* CONFIG_RTC_M41T60 && CFG_I2C_RTC_ADDR && CONFIG_CMD_DATE */ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 735c630006..ee2b780857 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -35,6 +35,7 @@ COBJS-y += serial_max3100.o COBJS-y += serial_pl010.o COBJS-y += serial_pl011.o COBJS-y += serial_xuartlite.o +COBJS-y += serial_sh.o COBJS-y += usbtty.o COBJS := $(COBJS-y) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c new file mode 100644 index 0000000000..ee44ba2644 --- /dev/null +++ b/drivers/serial/serial_sh.c @@ -0,0 +1,177 @@ +/* + * SuperH SCIF device driver. + * Copyright (c) 2007 Nobuhiro Iwamatsu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#ifdef CFG_SCIF_CONSOLE + +#if defined (CONFIG_CONS_SCIF0) +#define SCIF_BASE SCIF0_BASE +#elif defined (CONFIG_CONS_SCIF1) +#define SCIF_BASE SCIF1_BASE +#else +#error "Default SCIF doesn't set....." +#endif + +#define SCSMR (vu_short *)(SCIF_BASE + 0x0) +#define SCBRR (vu_char *)(SCIF_BASE + 0x4) +#define SCSCR (vu_short *)(SCIF_BASE + 0x8) +#define SCFTDR (vu_char *)(SCIF_BASE + 0xC) +#define SCFSR (vu_short *)(SCIF_BASE + 0x10) +#define SCFRDR (vu_char *)(SCIF_BASE + 0x14) +#define SCFCR (vu_short *)(SCIF_BASE + 0x18) +#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) +#if defined(CONFIG_SH4A) +#define SCRFDR (vu_short *)(SCIF_BASE + 0x20) +#define SCSPTR (vu_short *)(SCIF_BASE + 0x24) +#define SCLSR (vu_short *)(SCIF_BASE + 0x28) +#define SCRER (vu_short *)(SCIF_BASE + 0x2C) +#elif defined (CONFIG_SH4) +#define SCSPTR (vu_short *)(SCIF_BASE + 0x20) +#define SCLSR (vu_short *)(SCIF_BASE + 0x24) +#elif defined (CONFIG_SH3) +#define SCLSR (vu_short *)(SCIF_BASE + 0x24) +#endif + +#define SCR_RE (1 << 4) +#define SCR_TE (1 << 5) +#define FCR_RFRST (1 << 1) /* RFCL */ +#define FCR_TFRST (1 << 2) /* TFCL */ +#define FSR_DR (1 << 0) +#define FSR_RDF (1 << 1) +#define FSR_FER (1 << 3) +#define FSR_BRK (1 << 4) +#define FSR_FER (1 << 3) +#define FSR_TEND (1 << 6) +#define FSR_ER (1 << 7) + +/*----------------------------------------------------------------------*/ + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int divisor = gd->baudrate * 32; + + *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / + (gd->baudrate * 32) - 1; +} + +int serial_init (void) +{ + *SCSCR = (SCR_RE | SCR_TE); + *SCSMR = 0 ; + *SCSMR = 0; + *SCFCR = (FCR_RFRST | FCR_TFRST); + *SCFCR; + *SCFCR = 0; + + serial_setbrg(); + return 0; +} + +static int serial_tx_fifo_level (void) +{ + return (*SCFDR >> 8) & 0x1F; +} + +static int serial_rx_fifo_level (void) +{ + return (*SCFDR >> 0) & 0x1F; +} + +void serial_raw_putc (const char c) +{ + unsigned int fsr_bits_to_clear; + + while (1) { + if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ + fsr_bits_to_clear = FSR_TEND; + break; + } + } + + *SCFTDR = c; + if (fsr_bits_to_clear != 0) + *SCFSR &= ~fsr_bits_to_clear; +} + +void serial_putc (const char c) +{ + if (c == '\n') + serial_raw_putc ('\r'); + serial_raw_putc (c); +} + +void serial_puts (const char *s) +{ + char c; + while ((c = *s++) != 0) + serial_putc (c); +} + +int serial_tstc (void) +{ + return serial_rx_fifo_level() ? 1 : 0; +} + +#define FSR_ERR_CLEAR 0x0063 +#define RDRF_CLEAR 0x00fc +#define LSR_ORER 1 +void handle_error( void ){ + + (void)*SCFSR ; + *SCFSR = FSR_ERR_CLEAR ; + (void)*SCLSR ; + *SCLSR = 0x00 ; +} + +int serial_getc_check( void ){ + unsigned short status; + + status = *SCFSR ; + + if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) + handle_error(); + if( *SCLSR & LSR_ORER ) + handle_error(); + return (status & ( FSR_DR | FSR_RDF )); +} + +int serial_getc (void) +{ + unsigned short status ; + char ch; + while(!serial_getc_check()); + + ch = *SCFRDR; + status = *SCFSR ; + + *SCFSR = RDRF_CLEAR ; + + if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) + handle_error(); + + if( *SCLSR & LSR_ORER ) + handle_error(); + + return ch ; +} + +#endif /* CFG_SCIF_CONSOLE */ diff --git a/examples/Makefile b/examples/Makefile index e9b4974be4..71a8c7f3ab 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -61,6 +61,11 @@ ifeq ($(ARCH),avr32) LOAD_ADDR = 0x00000000 endif +ifeq ($(ARCH),sh) +LOAD_ADDR = 0x8C000000 +endif + + include $(TOPDIR)/config.mk ELF = hello_world diff --git a/examples/stubs.c b/examples/stubs.c index 26df6e06a1..571c4d50a4 100644 --- a/examples/stubs.c +++ b/examples/stubs.c @@ -132,7 +132,7 @@ gd_t *global_data; */ #define EXPORT_FUNC(x) \ asm volatile ( \ -" .globl _" #x "\n_" \ +" .globl _" #x "\n_" \ #x ":\n" \ " P0 = [P5 + %0]\n" \ " P0 = [P0 + %1]\n" \ @@ -151,6 +151,22 @@ gd_t *global_data; : \ : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \ : "r8"); +#elif defined(CONFIG_SH) +/* + * r13 holds the pointer to the global_data. r1 is a call clobbered. + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ + " .align 2\n" \ + " .globl " #x "\n" \ + #x ":\n" \ + " mov r13, r1\n" \ + " add %0, r1\n" \ + " add %1, r1\n" \ + " jmp @r1\n" \ + " nop\n" \ + " nop\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1"); #else #error stubs definition missing for this architecture #endif diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 47c18e7e86..029b7f9eeb 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -34,6 +34,32 @@ static inline void sync(void) } /* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +/* * Generic virtual read/write. Note that we don't support half-word * read/writes. We define __arch_*[bl] here, and leave __arch_*w * to the architecture specific code. diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h new file mode 100644 index 0000000000..29b1fd663d --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/chip-features.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__ +#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__ + +/* Currently, all the AP700x chips have these */ +#define AT32AP700x_CHIP_HAS_USART +#define AT32AP700x_CHIP_HAS_MMCI + +/* Only AP7000 has ethernet interface */ +#ifdef CONFIG_AT32AP7000 +#define AT32AP700x_CHIP_HAS_MACB +#endif + +#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index 7e20d97b7f..ea84c0874c 100644 --- a/include/asm-avr32/arch-at32ap7000/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -22,6 +22,8 @@ #ifndef __ASM_AVR32_ARCH_CLK_H__ #define __ASM_AVR32_ARCH_CLK_H__ +#include <asm/arch/chip-features.h> + #ifdef CONFIG_PLL #define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) #else @@ -50,10 +52,13 @@ static inline unsigned long get_sdram_clk_rate(void) { return get_hsb_clk_rate(); } +#ifdef AT32AP700x_CHIP_HAS_USART static inline unsigned long get_usart_clk_rate(unsigned int dev_id) { return get_pba_clk_rate(); } +#endif +#ifdef AT32AP700x_CHIP_HAS_USART static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { return get_pbb_clk_rate(); @@ -62,9 +67,12 @@ static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) { return get_hsb_clk_rate(); } +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI static inline unsigned long get_mci_clk_rate(void) { return get_pbb_clk_rate(); } +#endif #endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h index e4812d4d08..b10a3e4f86 100644 --- a/include/asm-avr32/arch-at32ap7000/gpio.h +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -22,6 +22,7 @@ #ifndef __ASM_AVR32_ARCH_GPIO_H__ #define __ASM_AVR32_ARCH_GPIO_H__ +#include <asm/arch/chip-features.h> #include <asm/arch/memory-map.h> #define NR_GPIO_CONTROLLERS 5 @@ -201,12 +202,19 @@ void gpio_select_periph_A(unsigned int pin, int use_pullup); void gpio_select_periph_B(unsigned int pin, int use_pullup); void gpio_enable_ebi(void); + +#ifdef AT32AP700x_CHIP_HAS_USART void gpio_enable_usart0(void); void gpio_enable_usart1(void); void gpio_enable_usart2(void); void gpio_enable_usart3(void); +#endif +#ifdef AT32AP700x_CHIP_HAS_MACB void gpio_enable_macb0(void); void gpio_enable_macb1(void); +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI void gpio_enable_mmci(void); +#endif #endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap700x/hmatrix2.h index b0e787a92f..b0e787a92f 100644 --- a/include/asm-avr32/arch-at32ap7000/hmatrix2.h +++ b/include/asm-avr32/arch-at32ap700x/hmatrix2.h diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h index 5513e88e7b..5513e88e7b 100644 --- a/include/asm-avr32/arch-at32ap7000/memory-map.h +++ b/include/asm-avr32/arch-at32ap700x/memory-map.h diff --git a/include/asm-avr32/arch-at32ap7000/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h index fcfbbb3c6c..fcfbbb3c6c 100644 --- a/include/asm-avr32/arch-at32ap7000/mmc.h +++ b/include/asm-avr32/arch-at32ap700x/mmc.h diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index 3c0d569233..ba14674cf7 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -93,4 +93,36 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + * + * This implementation works for memory below 512MiB (flash, etc.) as + * well as above 3.5GiB (internal peripherals.) + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (1 << 7) +#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) +#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + if (flags == MAP_WRBACK) + return (void *)P1SEGADDR(paddr); + else + return (void *)P2SEGADDR(paddr); +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long len) +{ + +} + #endif /* __ASM_AVR32_IO_H */ diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 332d2c6437..512e13d1ca 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -41,6 +41,32 @@ static inline void sync(void) } /* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +/* * These are for ISA/PCI shared memory _only_ and should never be used * on any other type of memory, including Zorro memory. They are meant to * access the bus in the bus byte order which is little-endian!. diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index e64d788fa7..db4f442817 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -205,4 +205,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index e14a581dc1..91d759219d 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -28,6 +28,20 @@ #include <asm/byteorder.h> +/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates + * two accesses to memory, which may be undesirable for some devices. + */ +#define __raw_readb(addr) \ + ({ u8 __v = (*(volatile u8 *) (addr)); __v; }) +#define __raw_readw(addr) \ + ({ u16 __v = (*(volatile u16 *) (addr)); __v; }) +#define __raw_readl(addr) \ + ({ u32 __v = (*(volatile u32 *) (addr)); __v; }) + +#define __raw_writeb(addr,b) (void)((*(volatile u8 *) (addr)) = (b)) +#define __raw_writew(addr,w) (void)((*(volatile u16 *) (addr)) = (w)) +#define __raw_writel(addr,l) (void)((*(volatile u32 *) (addr)) = (l)) + #define readb(addr) in_8((volatile u8 *)(addr)) #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) #if !defined(__BIG_ENDIAN) @@ -218,4 +232,31 @@ static inline void sync(void) * compatibility (CFI driver) */ } + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* __ASM_M68K_IO_H__ */ diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h index 1c77ade4f1..90d18428ad 100644 --- a/include/asm-microblaze/io.h +++ b/include/asm-microblaze/io.h @@ -129,4 +129,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* __MICROBLAZE_IO_H__ */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 1e060f7c31..e27d1f159d 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -465,4 +465,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* _ASM_IO_H */ diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h index d77695abb9..6fc339fb01 100644 --- a/include/asm-nios/io.h +++ b/include/asm-nios/io.h @@ -23,6 +23,14 @@ #ifndef __ASM_NIOS_IO_H_ #define __ASM_NIOS_IO_H_ +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + #define readb(addr)\ ({unsigned char val;\ asm volatile( " pfxio 0 \n"\ @@ -101,4 +109,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* __ASM_NIOS_IO_H_ */ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 5bb5322952..a52b95cf23 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -29,10 +29,44 @@ static inline void sync(void) __asm__ __volatile__ ("sync" : : : "memory"); } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + extern unsigned char inb (unsigned char *port); extern unsigned short inw (unsigned short *port); extern unsigned inl (unsigned port); +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + #define readb(addr)\ ({unsigned char val;\ asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 496fc72da3..d769d70120 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -720,11 +720,10 @@ typedef struct ccsr_tsec { } ccsr_tsec_t; /* - * PIC Registers(0x2_6000-0x4_0000-0x8_0000) + * PIC Registers(0x4_0000-0x8_0000) */ typedef struct ccsr_pic { - char res0[106496]; /* 0x26000-0x40000 */ - char res1[64]; + char res1[64]; /* 0x40000 */ uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ char res2[12]; uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ @@ -1619,25 +1618,25 @@ typedef struct ccsr_gur { #define PORDEVSR_PCI (0x00800000) /* PCI Mode */ -typedef struct immap { - ccsr_local_ecm_t im_local_ecm; - ccsr_ddr_t im_ddr; - ccsr_i2c_t im_i2c; - ccsr_duart_t im_duart; - ccsr_lbc_t im_lbc; - ccsr_pcix_t im_pcix; - ccsr_pcix_t im_pcix2; - char reserved[90112]; - ccsr_l2cache_t im_l2cache; - ccsr_dma_t im_dma; - ccsr_tsec_t im_tsec1; - ccsr_tsec_t im_tsec2; - ccsr_pic_t im_pic; - ccsr_cpm_t im_cpm; - ccsr_rio_t im_rio; - ccsr_gur_t im_gur; -} immap_t; - -extern immap_t *immr; +#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) +#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) +#define CFG_MPC85xx_ECM_OFFSET (0x0000) +#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) +#define CFG_MPC85xx_DDR_OFFSET (0x2000) +#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) +#define CFG_MPC85xx_LBC_OFFSET (0x5000) +#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) +#define CFG_MPC85xx_PCIX_OFFSET (0x8000) +#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET) +#define CFG_MPC85xx_PCIX2_OFFSET (0x9000) +#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET) +#define CFG_MPC85xx_L2_OFFSET (0x20000) +#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET) +#define CFG_MPC85xx_DMA_OFFSET (0x21000) +#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET) +#define CFG_MPC85xx_PIC_OFFSET (0x40000) +#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET) +#define CFG_MPC85xx_CPM_OFFSET (0x80000) +#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h index bd732b6688..6715064c94 100644 --- a/include/asm-ppc/immap_fsl_pci.h +++ b/include/asm-ppc/immap_fsl_pci.h @@ -144,7 +144,9 @@ typedef struct ccsr_pci { u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ - char res23[456]; /* (- #x1000 #xe38) 456 */ + char res23[200]; + u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ + char res24[252]; } ccsr_fsl_pci_t; #endif /*__IMMAP_fsl_pci__*/ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 11dfa1c57b..91c9c1e4c6 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -121,13 +121,43 @@ static inline void isync(void) #define iobarrier_w() eieio() /* + * Non ordered and non-swapping "raw" accessors + */ +#define __iomem +#define PCI_FIX_ADDR(addr) (addr) + +static inline unsigned char __raw_readb(const volatile void __iomem *addr) +{ + return *(volatile unsigned char *)PCI_FIX_ADDR(addr); +} +static inline unsigned short __raw_readw(const volatile void __iomem *addr) +{ + return *(volatile unsigned short *)PCI_FIX_ADDR(addr); +} +static inline unsigned int __raw_readl(const volatile void __iomem *addr) +{ + return *(volatile unsigned int *)PCI_FIX_ADDR(addr); +} +static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) +{ + *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v; +} +static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) +{ + *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v; +} +static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) +{ + *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v; +} + +/* * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. * * Read operations have additional twi & isync to make sure the read * is actually performed (i.e. the data has come back) before we start * executing any following instructions. */ -#define __iomem extern inline int in_8(const volatile unsigned char __iomem *addr) { int ret; @@ -208,4 +238,30 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h index f854df633a..daddb554d4 100644 --- a/include/asm-ppc/iopin_85xx.h +++ b/include/asm-ppc/iopin_85xx.h @@ -23,121 +23,121 @@ typedef struct { extern __inline__ void iopin_set_high (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_low (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_high (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_low (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_out (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_in (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_out (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_in (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_odr (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_act (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_odr (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_act (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_ded (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_gen (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_ded (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_gen (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index edcb3b9ca3..b19abe73a0 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -413,7 +413,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_PEX 0x00200000 +#define LAWAR_TRGT_IF_PCIE1 0x00200000 +#define LAWAR_TRGT_IF_PCIE2 0x00100000 +#define LAWAR_TRGT_IF_PCIE3 0x00300000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h new file mode 100644 index 0000000000..410fba46ef --- /dev/null +++ b/include/asm-sh/bitops.h @@ -0,0 +1,151 @@ +#ifndef __ASM_SH_BITOPS_H +#define __ASM_SH_BITOPS_H + +#ifdef __KERNEL__ +#include <asm/irqflags.h> +/* For __swab32 */ +#include <asm/byteorder.h> + +static inline void set_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a |= mask; + local_irq_restore(flags); +} + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() +static inline void clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a &= ~mask; + local_irq_restore(flags); +} + +static inline void change_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a ^= mask; + local_irq_restore(flags); +} + +static inline int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a |= mask; + local_irq_restore(flags); + + return retval; +} + +static inline int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + local_irq_restore(flags); + + return retval; +} + +static inline int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a ^= mask; + local_irq_restore(flags); + + return retval; +} + +static inline unsigned long ffz(unsigned long word) +{ + unsigned long result; + + __asm__("1:\n\t" + "shlr %1\n\t" + "bt/s 1b\n\t" + " add #1, %0" + : "=r" (result), "=r" (word) + : "0" (~0L), "1" (word) + : "t"); + return result; +} + +/** + * ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline int ffs (int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_BITOPS_H */ diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h new file mode 100644 index 0000000000..25626a0760 --- /dev/null +++ b/include/asm-sh/byteorder.h @@ -0,0 +1,30 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_SH_BYTEORDER_H_ +#define __ASM_SH_BYTEORDER_H_ + +#include <config.h> +#include <asm/types.h> + +#ifdef __LITTLE_ENDIAN__ +#include <linux/byteorder/little_endian.h> +#else +#include <linux/byteorder/big_endian.h> +#endif + +#endif diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h new file mode 100644 index 0000000000..265803956d --- /dev/null +++ b/include/asm-sh/cpu_sh4.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH4_H_ +#define _ASM_CPU_SH4_H_ + +/* cache control */ +#define CCR_CACHE_STOP 0x00000808 +#define CCR_CACHE_ENABLE 0x00000101 +#define CCR_CACHE_ICI 0x00000800 + +#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 +#define CACHE_OC_WAY_SHIFT 14 +#define CACHE_OC_NUM_ENTRIES 512 +#define CACHE_OC_ENTRY_SHIFT 5 + +#if defined (CONFIG_CPU_SH7750) +#include <asm/cpu_sh7750.h> +#elif defined (CONFIG_CPU_SH7722) +#include <asm/cpu_sh7722.h> +#else +#error "Unknown SH4 variant" +#endif + +#endif /* _ASM_CPU_SH4_H_ */ diff --git a/include/asm-sh/cpu_sh7722.h b/include/asm-sh/cpu_sh7722.h new file mode 100644 index 0000000000..13d4a77ede --- /dev/null +++ b/include/asm-sh/cpu_sh7722.h @@ -0,0 +1,1337 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * SH7722 Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH7722_H_ +#define _ASM_CPU_SH7722_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000090d + +/* EXP */ +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 + +/* MMU */ +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define PASCR 0xFF000070 +#define IRMCR 0xFF000078 + +/* CACHE */ +#define CCR 0xFF00001C +#define RAMCR 0xFF000074 + +/* XY MEMORY */ +#define XSA 0xFF000050 +#define YSA 0xFF000054 +#define XDA 0xFF000058 +#define YDA 0xFF00005C +#define XPR 0xFF000060 +#define YPR 0xFF000064 +#define XEA 0xFF000068 +#define YEA 0xFF00006C + +/* INTC */ +#define ICR0 0xA4140000 +#define ICR1 0xA414001C +#define INTPRI0 0xA4140010 +#define INTREQ0 0xA4140024 +#define INTMSK0 0xA4140044 +#define INTMSKCLR0 0xA4140064 +#define NMIFCR 0xA41400C0 +#define USERIMASK 0xA4700000 +#define IPRA 0xA4080000 +#define IPRB 0xA4080004 +#define IPRC 0xA4080008 +#define IPRD 0xA408000C +#define IPRE 0xA4080010 +#define IPRF 0xA4080014 +#define IPRG 0xA4080018 +#define IPRH 0xA408001C +#define IPRI 0xA4080020 +#define IPRJ 0xA4080024 +#define IPRK 0xA4080028 +#define IPRL 0xA408002C +#define IMR0 0xA4080080 +#define IMR1 0xA4080084 +#define IMR2 0xA4080088 +#define IMR3 0xA408008C +#define IMR4 0xA4080090 +#define IMR5 0xA4080094 +#define IMR6 0xA4080098 +#define IMR7 0xA408009C +#define IMR8 0xA40800A0 +#define IMR9 0xA40800A4 +#define IMR10 0xA40800A8 +#define IMR11 0xA40800AC +#define IMCR0 0xA40800C0 +#define IMCR1 0xA40800C4 +#define IMCR2 0xA40800C8 +#define IMCR3 0xA40800CC +#define IMCR4 0xA40800D0 +#define IMCR5 0xA40800D4 +#define IMCR6 0xA40800D8 +#define IMCR7 0xA40800DC +#define IMCR8 0xA40800E0 +#define IMCR9 0xA40800E4 +#define IMCR10 0xA40800E8 +#define IMCR11 0xA40800EC +#define MFI_IPRA 0xA40B0000 +#define MFI_IPRB 0xA40B0004 +#define MFI_IPRC 0xA40B0008 +#define MFI_IPRD 0xA40B000C +#define MFI_IPRE 0xA40B0010 +#define MFI_IPRF 0xA40B0014 +#define MFI_IPRG 0xA40B0018 +#define MFI_IPRH 0xA40B001C +#define MFI_IPRI 0xA40B0020 +#define MFI_IPRJ 0xA40B0024 +#define MFI_IPRK 0xA40B0028 +#define MFI_IPRL 0xA40B002C +#define MFI_IMR0 0xA40B0080 +#define MFI_IMR1 0xA40B0084 +#define MFI_IMR2 0xA40B0088 +#define MFI_IMR3 0xA40B008C +#define MFI_IMR4 0xA40B0090 +#define MFI_IMR5 0xA40B0094 +#define MFI_IMR6 0xA40B0098 +#define MFI_IMR7 0xA40B009C +#define MFI_IMR8 0xA40B00A0 +#define MFI_IMR9 0xA40B00A4 +#define MFI_IMR10 0xA40B00A8 +#define MFI_IMR11 0xA40B00AC +#define MFI_IMCR0 0xA40B00C0 +#define MFI_IMCR1 0xA40B00C4 +#define MFI_IMCR2 0xA40B00C8 +#define MFI_IMCR3 0xA40B00CC +#define MFI_IMCR4 0xA40B00D0 +#define MFI_IMCR5 0xA40B00D4 +#define MFI_IMCR6 0xA40B00D8 +#define MFI_IMCR7 0xA40B00DC +#define MFI_IMCR8 0xA40B00E0 +#define MFI_IMCR9 0xA40B00E4 +#define MFI_IMCR10 0xA40B00E8 +#define MFI_IMCR11 0xA40B00EC + +/* BSC */ +#define CMNCR 0xFEC10000 +#define CS0BCR 0xFEC10004 +#define CS2BCR 0xFEC10008 +#define CS4BCR 0xFEC10010 +#define CS5ABCR 0xFEC10014 +#define CS5BBCR 0xFEC10018 +#define CS6ABCR 0xFEC1001C +#define CS6BBCR 0xFEC10020 +#define CS0WCR 0xFEC10024 +#define CS2WCR 0xFEC10028 +#define CS4WCR 0xFEC10030 +#define CS5AWCR 0xFEC10034 +#define CS5BWCR 0xFEC10038 +#define CS6AWCR 0xFEC1003C +#define CS6BWCR 0xFEC10040 +#define RBWTCNT 0xFEC10054 + +/* SBSC */ +#define SBSC_SDCR 0xFE400008 +#define SBSC_SDWCR 0xFE40000C +#define SBSC_SDPCR 0xFE400010 +#define SBSC_RTCSR 0xFE400014 +#define SBSC_RTCNT 0xFE400018 +#define SBSC_RTCOR 0xFE40001C +#define SBSC_RFCR 0xFE400020 + +/* DMAC */ +#define SAR_0 0xFE008020 +#define DAR_0 0xFE008024 +#define TCR_0 0xFE008028 +#define CHCR_0 0xFE00802C +#define SAR_1 0xFE008030 +#define DAR_1 0xFE008034 +#define TCR_1 0xFE008038 +#define CHCR_1 0xFE00803C +#define SAR_2 0xFE008040 +#define DAR_2 0xFE008044 +#define TCR_2 0xFE008048 +#define CHCR_2 0xFE00804C +#define SAR_3 0xFE008050 +#define DAR_3 0xFE008054 +#define TCR_3 0xFE008058 +#define CHCR_3 0xFE00805C +#define SAR_4 0xFE008070 +#define DAR_4 0xFE008074 +#define TCR_4 0xFE008078 +#define CHCR_4 0xFE00807C +#define SAR_5 0xFE008080 +#define DAR_5 0xFE008084 +#define TCR_5 0xFE008088 +#define CHCR_5 0xFE00808C +#define SARB_0 0xFE008120 +#define DARB_0 0xFE008124 +#define TCRB_0 0xFE008128 +#define SARB_1 0xFE008130 +#define DARB_1 0xFE008134 +#define TCRB_1 0xFE008138 +#define SARB_2 0xFE008140 +#define DARB_2 0xFE008144 +#define TCRB_2 0xFE008148 +#define SARB_3 0xFE008150 +#define DARB_3 0xFE008154 +#define TCRB_3 0xFE008158 +#define DMAOR 0xFE008060 +#define DMARS_0 0xFE009000 +#define DMARS_1 0xFE009004 +#define DMARS_2 0xFE009008 + +/* CPG */ +#define FRQCR 0xA4150000 +#define VCLKCR 0xA4150004 +#define SCLKACR 0xA4150008 +#define SCLKBCR 0xA415000C +#define PLLCR 0xA4150024 +#define DLLFRQ 0xA4150050 + +/* LOW POWER MODE */ +#define STBCR 0xA4150020 +#define MSTPCR0 0xA4150030 +#define MSTPCR1 0xA4150034 +#define MSTPCR2 0xA4150038 +#define BAR 0xA4150040 + +/* RWDT */ +#define RWTCNT 0xA4520000 +#define RWTCSR 0xA4520004 +#define WTCNT RWTCNT + + +/* TMU */ +#define TSTR 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 + +/* TPU */ +#define TPU_TSTR 0xA4C90000 +#define TPU_TCR0 0xA4C90010 +#define TPU_TMDR0 0xA4C90014 +#define TPU_TIOR0 0xA4C90018 +#define TPU_TIER0 0xA4C9001C +#define TPU_TSR0 0xA4C90020 +#define TPU_TCNT0 0xA4C90024 +#define TPU_TGR0A 0xA4C90028 +#define TPU_TGR0B 0xA4C9002C +#define TPU_TGR0C 0xA4C90030 +#define TPU_TGR0D 0xA4C90034 +#define TPU_TCR1 0xA4C90050 +#define TPU_TMDR1 0xA4C90054 +#define TPU_TIER1 0xA4C9005C +#define TPU_TSR1 0xA4C90060 +#define TPU_TCNT1 0xA4C90064 +#define TPU_TGR1A 0xA4C90068 +#define TPU_TGR1B 0xA4C9006C +#define TPU_TGR1C 0xA4C90070 +#define TPU_TGR1D 0xA4C90074 +#define TPU_TCR2 0xA4C90090 +#define TPU_TMDR2 0xA4C90094 +#define TPU_TIER2 0xA4C9009C +#define TPU_TSR2 0xA4C900A0 +#define TPU_TCNT2 0xA4C900A4 +#define TPU_TGR2A 0xA4C900A8 +#define TPU_TGR2B 0xA4C900AC +#define TPU_TGR2C 0xA4C900B0 +#define TPU_TGR2D 0xA4C900B4 +#define TPU_TCR3 0xA4C900D0 +#define TPU_TMDR3 0xA4C900D4 +#define TPU_TIER3 0xA4C900DC +#define TPU_TSR3 0xA4C900E0 +#define TPU_TCNT3 0xA4C900E4 +#define TPU_TGR3A 0xA4C900E8 +#define TPU_TGR3B 0xA4C900EC +#define TPU_TGR3C 0xA4C900F0 +#define TPU_TGR3D 0xA4C900F4 + +/* CMT */ +#define CMSTR 0xA44A0000 +#define CMCSR 0xA44A0060 +#define CMCNT 0xA44A0064 +#define CMCOR 0xA44A0068 + +/* SIO */ +#define SIOMDR 0xA4500000 +#define SIOCTR 0xA4500004 +#define SIOSTBCR0 0xA4500008 +#define SIOSTBCR1 0xA450000C +#define SIOTDR 0xA4500014 +#define SIORDR 0xA4500018 +#define SIOSTR 0xA450001C +#define SIOIER 0xA4500020 +#define SIOSCR 0xA4500024 + +/* SIOF */ +#define SIMDR0 0xA4410000 +#define SISCR0 0xA4410002 +#define SITDAR0 0xA4410004 +#define SIRDAR0 0xA4410006 +#define SICDAR0 0xA4410008 +#define SICTR0 0xA441000C +#define SIFCTR0 0xA4410010 +#define SISTR0 0xA4410014 +#define SIIER0 0xA4410016 +#define SITDR0 0xA4410020 +#define SIRDR0 0xA4410024 +#define SITCR0 0xA4410028 +#define SIRCR0 0xA441002C +#define SPICR0 0xA4410030 +#define SIMDR1 0xA4420000 +#define SISCR1 0xA4420002 +#define SITDAR1 0xA4420004 +#define SIRDAR1 0xA4420006 +#define SICDAR1 0xA4420008 +#define SICTR1 0xA442000C +#define SIFCTR1 0xA4420010 +#define SISTR1 0xA4420014 +#define SIIER1 0xA4420016 +#define SITDR1 0xA4420020 +#define SIRDR1 0xA4420024 +#define SITCR1 0xA4420028 +#define SIRCR1 0xA442002C +#define SPICR1 0xA4420030 + +/* SCIF */ +/* +#define SCSMR 0xFFE00000 +#define SCBRR 0xFFE00004 +#define SCSCR 0xFFE00008 +#define SCFTDR 0xFFE0000C +#define SCFSR 0xFFE00010 +#define SCFRDR 0xFFE00014 +#define SCFCR 0xFFE00018 +#define SCFDR 0xFFE0001C +#define SCLSR 0xFFE00024 +#define SCSMR1 0xFFE10000 +#define SCBRR1 0xFFE10004 +#define SCSCR1 0xFFE10008 +#define SCFTDR1 0xFFE1000C +#define SCFSR1 0xFFE10010 +#define SCFRDR1 0xFFE10014 +#define SCFCR1 0xFFE10018 +#define SCFDR1 0xFFE1001C +#define SCLSR1 0xFFE10024 +#define SCSMR2 0xFFE20000 +#define SCBRR2 0xFFE20004 +#define SCSCR2 0xFFE20008 +#define SCFTDR2 0xFFE2000C +#define SCFSR2 0xFFE20010 +#define SCFRDR2 0xFFE20014 +#define SCFCR2 0xFFE20018 +#define SCFDR2 0xFFE2001C +#define SCLSR2 0xFFE20024 +#define SCSMR3 0xFFE30000 +#define SCBRR3 0xFFE30004 +#define SCSCR3 0xFFE30008 +#define SCFTDR3 0xFFE3000C +#define SCFSR3 0xFFE30010 +#define SCFRDR3 0xFFE30014 +#define SCFCR3 0xFFE30018 +#define SCFDR3 0xFFE3001C +#define SCLSR3 0xFFE30024 +*/ +#define SCIF0_BASE 0xFFE00000 + +/* SIM */ +#define SIM_SCSMR 0xA4490000 +#define SIM_SCBRR 0xA4490002 +#define SIM_SCSCR 0xA4490004 +#define SIM_SCTDR 0xA4490006 +#define SIM_SCSSR 0xA4490008 +#define SIM_SCRDR 0xA449000A +#define SIM_SCSCMR 0xA449000C +#define SIM_SCSC2R 0xA449000E +#define SIM_SCWAIT 0xA4490010 +#define SIM_SCGRD 0xA4490012 +#define SIM_SCSMPL 0xA4490014 +#define SIM_SCDMAEN 0xA4490016 + +/* IrDA */ +#define IRIF_INIT1 0xA45D0012 +#define IRIF_INIT2 0xA45D0014 +#define IRIF_RINTCLR 0xA45D0016 +#define IRIF_TINTCLR 0xA45D0018 +#define IRIF_SIR0 0xA45D0020 +#define IRIF_SIR1 0xA45D0022 +#define IRIF_SIR2 0xA45D0024 +#define IRIF_SIR3 0xA45D0026 +#define IRIF_SIR_FRM 0xA45D0028 +#define IRIF_SIR_EOF 0xA45D002A +#define IRIF_SIR_FLG 0xA45D002C +#define IRIF_SIR_STS2 0xA45D002E +#define IRIF_UART0 0xA45D0030 +#define IRIF_UART1 0xA45D0032 +#define IRIF_UART2 0xA45D0034 +#define IRIF_UART3 0xA45D0036 +#define IRIF_UART4 0xA45D0038 +#define IRIF_UART5 0xA45D003A +#define IRIF_UART6 0xA45D003C +#define IRIF_UART7 0xA45D003E +#define IRIF_CRC0 0xA45D0040 +#define IRIF_CRC1 0xA45D0042 +#define IRIF_CRC2 0xA45D0044 +#define IRIF_CRC3 0xA45D0046 +#define IRIF_CRC4 0xA45D0048 + +/* IIC */ +#define ICDR0 0xA4470000 +#define ICCR0 0xA4470004 +#define ICSR0 0xA4470008 +#define ICIC0 0xA447000C +#define ICCL0 0xA4470010 +#define ICCH0 0xA4470014 +#define ICDR1 0xA4750000 +#define ICCR1 0xA4750004 +#define ICSR1 0xA4750008 +#define ICIC1 0xA475000C +#define ICCL1 0xA4750010 +#define ICCH1 0xA4750014 + +/* FLCTL */ +#define FLCMNCR 0xA4530000 +#define FLCMDCR 0xA4530004 +#define FLCMCDR 0xA4530008 +#define FLADR 0xA453000C +#define FLDATAR 0xA4530010 +#define FLDTCNTR 0xA4530014 +#define FLINTDMACR 0xA4530018 +#define FLBSYTMR 0xA453001C +#define FLBSYCNT 0xA4530020 +#define FLDTFIFO 0xA4530024 +#define FLECFIFO 0xA4530028 +#define FLTRCR 0xA453002C +#define FLADR2 0xA453003C + +/* MFI */ +#define MFIIDX 0xA4C10000 +#define MFIGSR 0xA4C10004 +#define MFISCR 0xA4C10008 +#define MFIMCR 0xA4C1000C +#define MFIIICR 0xA4C10010 +#define MFIEICR 0xA4C10014 +#define MFIADR 0xA4C10018 +#define MFIDATA 0xA4C1001C +#define MFIRCR 0xA4C10020 +#define MFIINTEVT 0xA4C1002C +#define MFIIMASK 0xA4C10030 +#define MFIBCR 0xA4C10040 +#define MFIADRW 0xA4C10044 +#define MFIADRR 0xA4C10048 +#define MFIDATAW 0xA4C1004C +#define MFIDATAR 0xA4C10050 +#define MFIMCRW 0xA4C10054 +#define MFIMCRR 0xA4C10058 +#define MFIDNRW 0xA4C1005C +#define MFIDNRR 0xA4C10060 +#define MFISIZEW 0xA4C10064 +#define MFISIZER 0xA4C10068 +#define MFIDEVCR 0xA4C10038 +#define MFISM4 0xA4C10080 + +/* VPU */ +#define VP4_CTRL 0xFE900000 +#define VP4_VOL_CTRL 0xFE900004 +#define VP4_IMAGE_SIZE 0xFE900008 +#define VP4_MB_NUM 0xFE90000C +#define VP4_DWY_ADDR 0xFE900010 +#define VP4_DWC_ADDR 0xFE900014 +#define VP4_D2WY_ADDR 0xFE900018 +#define VP4_D2WC_ADDR 0xFE90001C +#define VP4_DP1_ADDR 0xFE900020 +#define VP4_DP2_ADDR 0xFE900024 +#define VP4_STRS_ADDR 0xFE900028 +#define VP4_STRE_ADDR 0xFE90002C +#define VP4_VOP_CTRL 0xFE900030 +#define VP4_VOP_TIME 0xFE900034 +#define VP4_263_CTRL 0xFE900038 +#define VP4_264_CTRL 0xFE90003C +#define VP4_VLC_CTRL 0xFE900040 +#define VP4_ENDIAN 0xFE900044 +#define VP4_CMD 0xFE900048 +#define VP4_ME_TH1 0xFE90004C +#define VP4_ME_TH2 0xFE900050 +#define VP4_ME_COSTMB 0xFE900054 +#define VP4_ME_SKIP 0xFE900058 +#define VP4_ME_CTRL 0xFE90005C +#define VP4_MBRF_CTRL 0xFE900060 +#define VP4_MC_CTRL 0xFE900064 +#define VP4_PRED_CTRL 0xFE900068 +#define VP4_SLC_SIZE 0xFE90006C +#define VP4_VOP_MINBIT 0xFE900070 +#define VP4_MB_MAXBIT 0xFE900074 +#define VP4_MB_TBIT 0xFE900078 +#define VP4_RCQNT 0xFE90007C +#define VP4_RCRP 0xFE900080 +#define VP4_RCDJ 0xFE900084 +#define VP4_RCWQ 0xFE900088 +#define VP4_FWD_TIME 0xFE900094 +#define VP4_BWD_TIME 0xFE900098 +#define VP4_PST_TIME 0xFE90009C +#define VP4_ILTFRAME 0xFE9000A0 +#define VP4_EC_REF 0xFE9000A4 +#define VP4_STATUS 0xFE900100 +#define VP4_IRQ_ENB 0xFE900104 +#define VP4_IRQ_STA 0xFE900108 +#define VP4_VOP_BIT 0xFE90010C +#define VP4_PRV_BIT 0xFE900110 +#define VP4_SLC_MB 0xFE900114 +#define VP4_QSUM 0xFE900118 +#define VP4_DEC_ERR 0xFE90011C +#define VP4_ERR_AREA 0xFE900120 +#define VP4_NEXT_CODE 0xFE900124 +#define VP4_MB_ATTR 0xFE900128 +#define VP4_DBMON 0xFE90012C +#define VP4_DEBUG 0xFE900130 +#define VP4_ERR_DET 0xFE900134 +#define VP4_CLK_STOP 0xFE900138 +#define VP4_MB_SADA 0xFE90013C +#define VP4_MB_SADR 0xFE900140 +#define VP4_MAT_RAM 0xFE901000 +#define VP4_NC_RAM 0xFE902000 +#define WT 0xFE9020CC +#define VP4_CPY_ADDR 0xFE902264 +#define VP4_CPC_ADDR 0xFE902268 +#define VP4_R0Y_ADDR 0xFE90226C +#define VP4_R0C_ADDR 0xFE902270 +#define VP4_R1Y_ADDR 0xFE902274 +#define VP4_R1C_ADDR 0xFE902278 +#define VP4_R2Y_ADDR 0xFE90227C +#define VP4_R2C_ADDR 0xFE902280 +#define VP4_R3Y_ADDR 0xFE902284 +#define VP4_R3C_ADDR 0xFE902288 +#define VP4_R4Y_ADDR 0xFE90228C +#define VP4_R4C_ADDR 0xFE902290 +#define VP4_R5Y_ADDR 0xFE902294 +#define VP4_R5C_ADDR 0xFE902298 +#define VP4_R6Y_ADDR 0xFE90229C +#define VP4_R6C_ADDR 0xFE9022A0 +#define VP4_R7Y_ADDR 0xFE9022A4 +#define VP4_R7C_ADDR 0xFE9022A8 +#define VP4_R8Y_ADDR 0xFE9022AC +#define VP4_R8C_ADDR 0xFE9022B0 +#define VP4_R9Y_ADDR 0xFE9022B4 +#define VP4_R9C_ADDR 0xFE9022B8 +#define VP4_RAY_ADDR 0xFE9022BC +#define VP4_RAC_ADDR 0xFE9022C0 +#define VP4_RBY_ADDR 0xFE9022C4 +#define VP4_RBC_ADDR 0xFE9022C8 +#define VP4_RCY_ADDR 0xFE9022CC +#define VP4_RCC_ADDR 0xFE9022D0 +#define VP4_RDY_ADDR 0xFE9022D4 +#define VP4_RDC_ADDR 0xFE9022D8 +#define VP4_REY_ADDR 0xFE9022DC +#define VP4_REC_ADDR 0xFE9022E0 +#define VP4_RFY_ADDR 0xFE9022E4 +#define VP4_RFC_ADDR 0xFE9022E8 + +/* VIO(CEU) */ +#define CAPSR 0xFE910000 +#define CAPCR 0xFE910004 +#define CAMCR 0xFE910008 +#define CMCYR 0xFE91000C +#define CAMOR 0xFE910010 +#define CAPWR 0xFE910014 +#define CAIFR 0xFE910018 +#define CSTCR 0xFE910020 +#define CSECR 0xFE910024 +#define CRCNTR 0xFE910028 +#define CRCMPR 0xFE91002C +#define CFLCR 0xFE910030 +#define CFSZR 0xFE910034 +#define CDWDR 0xFE910038 +#define CDAYR 0xFE91003C +#define CDACR 0xFE910040 +#define CDBYR 0xFE910044 +#define CDBCR 0xFE910048 +#define CBDSR 0xFE91004C +#define CLFCR 0xFE910060 +#define CDOCR 0xFE910064 +#define CDDCR 0xFE910068 +#define CDDAR 0xFE91006C +#define CEIER 0xFE910070 +#define CETCR 0xFE910074 +#define CSTSR 0xFE91007C +#define CSRTR 0xFE910080 +#define CDAYR2 0xFE910090 +#define CDACR2 0xFE910094 +#define CDBYR2 0xFE910098 +#define CDBCR2 0xFE91009C + +/* VIO(VEU) */ +#define VESTR 0xFE920000 +#define VESWR 0xFE920010 +#define VESSR 0xFE920014 +#define VSAYR 0xFE920018 +#define VSACR 0xFE92001C +#define VBSSR 0xFE920020 +#define VEDWR 0xFE920030 +#define VDAYR 0xFE920034 +#define VDACR 0xFE920038 +#define VTRCR 0xFE920050 +#define VRFCR 0xFE920054 +#define VRFSR 0xFE920058 +#define VENHR 0xFE92005C +#define VFMCR 0xFE920070 +#define VVTCR 0xFE920074 +#define VHTCR 0xFE920078 +#define VAPCR 0xFE920080 +#define VECCR 0xFE920084 +#define VAFXR 0xFE920090 +#define VSWPR 0xFE920094 +#define VEIER 0xFE9200A0 +#define VEVTR 0xFE9200A4 +#define VSTAR 0xFE9200B0 +#define VBSRR 0xFE9200B4 + +/* VIO(BEU) */ +#define BESTR 0xFE930000 +#define BSMWR1 0xFE930010 +#define BSSZR1 0xFE930014 +#define BSAYR1 0xFE930018 +#define BSACR1 0xFE93001C +#define BSAAR1 0xFE930020 +#define BSIFR1 0xFE930024 +#define BSMWR2 0xFE930028 +#define BSSZR2 0xFE93002C +#define BSAYR2 0xFE930030 +#define BSACR2 0xFE930034 +#define BSAAR2 0xFE930038 +#define BSIFR2 0xFE93003C +#define BSMWR3 0xFE930040 +#define BSSZR3 0xFE930044 +#define BSAYR3 0xFE930048 +#define BSACR3 0xFE93004C +#define BSAAR3 0xFE930050 +#define BSIFR3 0xFE930054 +#define BTPSR 0xFE930058 +#define BMSMWR1 0xFE930070 +#define BMSSZR1 0xFE930074 +#define BMSAYR1 0xFE930078 +#define BMSACR1 0xFE93007C +#define BMSMWR2 0xFE930080 +#define BMSSZR2 0xFE930084 +#define BMSAYR2 0xFE930088 +#define BMSACR2 0xFE93008C +#define BMSMWR3 0xFE930090 +#define BMSSZR3 0xFE930094 +#define BMSAYR3 0xFE930098 +#define BMSACR3 0xFE93009C +#define BMSMWR4 0xFE9300A0 +#define BMSSZR4 0xFE9300A4 +#define BMSAYR4 0xFE9300A8 +#define BMSACR4 0xFE9300AC +#define BMSIFR 0xFE9300F0 +#define BBLCR0 0xFE930100 +#define BBLCR1 0xFE930104 +#define BPROCR 0xFE930108 +#define BMWCR0 0xFE93010C +#define BLOCR1 0xFE930114 +#define BLOCR2 0xFE930118 +#define BLOCR3 0xFE93011C +#define BMLOCR1 0xFE930120 +#define BMLOCR2 0xFE930124 +#define BMLOCR3 0xFE930128 +#define BMLOCR4 0xFE93012C +#define BMPCCR1 0xFE930130 +#define BMPCCR2 0xFE930134 +#define BPKFR 0xFE930140 +#define BPCCR0 0xFE930144 +#define BPCCR11 0xFE930148 +#define BPCCR12 0xFE93014C +#define BPCCR21 0xFE930150 +#define BPCCR22 0xFE930154 +#define BPCCR31 0xFE930158 +#define BPCCR32 0xFE93015C +#define BDMWR 0xFE930160 +#define BDAYR 0xFE930164 +#define BDACR 0xFE930168 +#define BAFXR 0xFE930180 +#define BSWPR 0xFE930184 +#define BEIER 0xFE930188 +#define BEVTR 0xFE93018C +#define BRCNTR 0xFE930194 +#define BSTAR 0xFE930198 +#define BBRSTR 0xFE93019C +#define BRCHR 0xFE9301A0 +#define CLUT 0xFE933000 + +/* JPU */ +#define JCMOD 0xFEA00000 +#define JCCMD 0xFEA00004 +#define JCSTS 0xFEA00008 +#define JCQTN 0xFEA0000C +#define JCHTN 0xFEA00010 +#define JCDRIU 0xFEA00014 +#define JCDRID 0xFEA00018 +#define JCVSZU 0xFEA0001C +#define JCVSZD 0xFEA00020 +#define JCHSZU 0xFEA00024 +#define JCHSZD 0xFEA00028 +#define JCDTCU 0xFEA0002C +#define JCDTCM 0xFEA00030 +#define JCDTCD 0xFEA00034 +#define JINTE 0xFEA00038 +#define JINTS 0xFEA0003C +#define JCDERR 0xFEA00040 +#define JCRST 0xFEA00044 +#define JIFCNT 0xFEA00060 +#define JIFECNT 0xFEA00070 +#define JIFESYA1 0xFEA00074 +#define JIFESCA1 0xFEA00078 +#define JIFESYA2 0xFEA0007C +#define JIFESCA2 0xFEA00080 +#define JIFESMW 0xFEA00084 +#define JIFESVSZ 0xFEA00088 +#define JIFESHSZ 0xFEA0008C +#define JIFEDA1 0xFEA00090 +#define JIFEDA2 0xFEA00094 +#define JIFEDRSZ 0xFEA00098 +#define JIFDCNT 0xFEA000A0 +#define JIFDSA1 0xFEA000A4 +#define JIFDSA2 0xFEA000A8 +#define JIFDDRSZ 0xFEA000AC +#define JIFDDMW 0xFEA000B0 +#define JIFDDVSZ 0xFEA000B4 +#define JIFDDHSZ 0xFEA000B8 +#define JIFDDYA1 0xFEA000BC +#define JIFDDCA1 0xFEA000C0 +#define JIFDDYA2 0xFEA000C4 +#define JIFDDCA2 0xFEA000C8 +#define JCQTBL0 0xFEA10000 +#define JCQTBL1 0xFEA10040 +#define JCQTBL2 0xFEA10080 +#define JCQTBL3 0xFEA100C0 +#define JCHTBD0 0xFEA10100 +#define JCHTBA0 0xFEA10120 +#define JCHTBD1 0xFEA10200 +#define JCHTBA1 0xFEA10220 + +/* LCDC */ +#define MLDDCKPAT1R 0xFE940400 +#define MLDDCKPAT2R 0xFE940404 +#define SLDDCKPAT1R 0xFE940408 +#define SLDDCKPAT2R 0xFE94040C +#define LDDCKR 0xFE940410 +#define LDDCKSTPR 0xFE940414 +#define MLDMT1R 0xFE940418 +#define MLDMT2R 0xFE94041C +#define MLDMT3R 0xFE940420 +#define MLDDFR 0xFE940424 +#define MLDSM1R 0xFE940428 +#define MLDSM2R 0xFE94042C +#define MLDSA1R 0xFE940430 +#define MLDSA2R 0xFE940434 +#define MLDMLSR 0xFE940438 +#define MLDWBFR 0xFE94043C +#define MLDWBCNTR 0xFE940440 +#define MLDWBAR 0xFE940444 +#define MLDHCNR 0xFE940448 +#define MLDHSYNR 0xFE94044C +#define MLDVLNR 0xFE940450 +#define MLDVSYNR 0xFE940454 +#define MLDHPDR 0xFE940458 +#define MLDVPDR 0xFE94045C +#define MLDPMR 0xFE940460 +#define LDPALCR 0xFE940464 +#define LDINTR 0xFE940468 +#define LDSR 0xFE94046C +#define LDCNT1R 0xFE940470 +#define LDCNT2R 0xFE940474 +#define LDRCNTR 0xFE940478 +#define LDDDSR 0xFE94047C +#define LDRCR 0xFE940484 +#define LDCMRKRGBR 0xFE9404C4 +#define LDCMRKCMYR 0xFE9404C8 +#define LDCMRK1R 0xFE9404CC +#define LDCMRK2R 0xFE9404D0 +#define LDCMGKRGBR 0xFE9404D4 +#define LDCMGKCMYR 0xFE9404D8 +#define LDCMGK1R 0xFE9404DC +#define LDCMGK2R 0xFE9404E0 +#define LDCMBKRGBR 0xFE9404E4 +#define LDCMBKCMYR 0xFE9404E8 +#define LDCMBK1R 0xFE9404EC +#define LDCMBK2R 0xFE9404F0 +#define LDCMHKPR 0xFE9404F4 +#define LDCMHKQR 0xFE9404F8 +#define LDCMSELR 0xFE9404FC +#define LDCMTVR 0xFE940500 +#define LDCMTVSELR 0xFE940504 +#define LDCMDTHR 0xFE940508 +#define LDCMCNTR 0xFE94050C +#define SLDMT1R 0xFE940600 +#define SLDMT2R 0xFE940604 +#define SLDMT3R 0xFE940608 +#define SLDDFR 0xFE94060C +#define SLDSM1R 0xFE940610 +#define SLDSM2R 0xFE940614 +#define SLDSA1R 0xFE940618 +#define SLDSA2R 0xFE94061C +#define SLDMLSR 0xFE940620 +#define SLDHCNR 0xFE940624 +#define SLDHSYNR 0xFE940628 +#define SLDVLNR 0xFE94062C +#define SLDVSYNR 0xFE940630 +#define SLDHPDR 0xFE940634 +#define SLDVPDR 0xFE940638 +#define SLDPMR 0xFE94063C +#define LDDWD0R 0xFE940800 +#define LDDWD1R 0xFE940804 +#define LDDWD2R 0xFE940808 +#define LDDWD3R 0xFE94080C +#define LDDWD4R 0xFE940810 +#define LDDWD5R 0xFE940814 +#define LDDWD6R 0xFE940818 +#define LDDWD7R 0xFE94081C +#define LDDWD8R 0xFE940820 +#define LDDWD9R 0xFE940824 +#define LDDWDAR 0xFE940828 +#define LDDWDBR 0xFE94082C +#define LDDWDCR 0xFE940830 +#define LDDWDDR 0xFE940834 +#define LDDWDER 0xFE940838 +#define LDDWDFR 0xFE94083C +#define LDDRDR 0xFE940840 +#define LDDWAR 0xFE940900 +#define LDDRAR 0xFE940904 +#define LDPR00 0xFE940000 + +/* VOU */ +#define VOUER 0xFE960000 +#define VOUCR 0xFE960004 +#define VOUSTR 0xFE960008 +#define VOUVCR 0xFE96000C +#define VOUISR 0xFE960010 +#define VOUBCR 0xFE960014 +#define VOUDPR 0xFE960018 +#define VOUDSR 0xFE96001C +#define VOUVPR 0xFE960020 +#define VOUIR 0xFE960024 +#define VOUSRR 0xFE960028 +#define VOUMSR 0xFE96002C +#define VOUHIR 0xFE960030 +#define VOUDFR 0xFE960034 +#define VOUAD1R 0xFE960038 +#define VOUAD2R 0xFE96003C +#define VOUAIR 0xFE960040 +#define VOUSWR 0xFE960044 +#define VOURCR 0xFE960048 +#define VOURPR 0xFE960050 + +/* TSIF */ +#define TSCTLR 0xA4C80000 +#define TSPIDR 0xA4C80004 +#define TSCMDR 0xA4C80008 +#define TSSTR 0xA4C8000C +#define TSTSDR 0xA4C80010 +#define TSBUFCLRR 0xA4C80014 +#define TSINTER 0xA4C80018 +#define TSPSCALER 0xA4C80020 +#define TSPSCALERR 0xA4C80024 +#define TSPCRADCMDR 0xA4C80028 +#define TSPCRADCR 0xA4C8002C +#define TSTRPCRADCR 0xA4C80030 +#define TSDPCRADCR 0xA4C80034 + +/* SIU */ +#define IFCTL 0xA454C000 +#define SRCTL 0xA454C004 +#define SFORM 0xA454C008 +#define CKCTL 0xA454C00C +#define TRDAT 0xA454C010 +#define STFIFO 0xA454C014 +#define DPAK 0xA454C01C +#define CKREV 0xA454C020 +#define EVNTC 0xA454C028 +#define SBCTL 0xA454C040 +#define SBPSET 0xA454C044 +#define SBBUS 0xA454C048 +#define SBWFLG 0xA454C058 +#define SBRFLG 0xA454C05C +#define SBWDAT 0xA454C060 +#define SBRDAT 0xA454C064 +#define SBFSTS 0xA454C068 +#define SBDVCA 0xA454C06C +#define SBDVCB 0xA454C070 +#define SBACTIV 0xA454C074 +#define DMAIA 0xA454C090 +#define DMAIB 0xA454C094 +#define DMAOA 0xA454C098 +#define DMAOB 0xA454C09C +#define SPLRI 0xA454C0B8 +#define SPRRI 0xA454C0BC +#define SPURI 0xA454C0C4 +#define SPTIS 0xA454C0C8 +#define SPSTS 0xA454C0CC +#define SPCTL 0xA454C0D0 +#define SPIRI 0xA454C0D4 +#define SPQCF 0xA454C0D8 +#define SPQCS 0xA454C0DC +#define SPQCT 0xA454C0E0 +#define DPEAK 0xA454C0F0 +#define DSLPD 0xA454C0F4 +#define DSLLV 0xA454C0F8 +#define BRGASEL 0xA454C100 +#define BRRA 0xA454C104 +#define BRGBSEL 0xA454C108 +#define BRRB 0xA454C10C + +/* USB */ +#define IFR0 0xA4480000 +#define ISR0 0xA4480010 +#define IER0 0xA4480020 +#define EPDR0I 0xA4480030 +#define EPDR0O 0xA4480034 +#define EPDR0S 0xA4480038 +#define EPDR1 0xA448003C +#define EPDR2 0xA4480040 +#define EPDR3 0xA4480044 +#define EPDR4 0xA4480048 +#define EPDR5 0xA448004C +#define EPDR6 0xA4480050 +#define EPDR7 0xA4480054 +#define EPDR8 0xA4480058 +#define EPDR9 0xA448005C +#define EPSZ0O 0xA4480080 +#define EPSZ3 0xA4480084 +#define EPSZ6 0xA4480088 +#define EPSZ9 0xA448008C +#define TRG 0xA44800A0 +#define DASTS 0xA44800A4 +#define FCLR 0xA44800AA +#define DMA 0xA44800AC +#define EPSTL 0xA44800B2 +#define CVR 0xA44800B4 +#define TSR 0xA44800B8 +#define CTLR 0xA44800BC +#define EPIR 0xA44800C0 +#define XVERCR 0xA44800D0 +#define STLMR 0xA44800D4 + +/* KEYSC */ +#define KYCR1 0xA44B0000 +#define KYCR2 0xA44B0004 +#define KYINDR 0xA44B0008 +#define KYOUTDR 0xA44B000C + +/* MMCIF */ +#define CMDR0 0xA4448000 +#define CMDR1 0xA4448001 +#define CMDR2 0xA4448002 +#define CMDR3 0xA4448003 +#define CMDR4 0xA4448004 +#define CMDR5 0xA4448005 +#define CMDSTRT 0xA4448006 +#define OPCR 0xA444800A +#define CSTR 0xA444800B +#define INTCR0 0xA444800C +#define INTCR1 0xA444800D +#define INTSTR0 0xA444800E +#define INTSTR1 0xA444800F +#define CLKON 0xA4448010 +#define CTOCR 0xA4448011 +#define VDCNT 0xA4448012 +#define TBCR 0xA4448014 +#define MODER 0xA4448016 +#define CMDTYR 0xA4448018 +#define RSPTYR 0xA4448019 +#define TBNCR 0xA444801A +#define RSPR0 0xA4448020 +#define RSPR1 0xA4448021 +#define RSPR2 0xA4448022 +#define RSPR3 0xA4448023 +#define RSPR4 0xA4448024 +#define RSPR5 0xA4448025 +#define RSPR6 0xA4448026 +#define RSPR7 0xA4448027 +#define RSPR8 0xA4448028 +#define RSPR9 0xA4448029 +#define RSPR10 0xA444802A +#define RSPR11 0xA444802B +#define RSPR12 0xA444802C +#define RSPR13 0xA444802D +#define RSPR14 0xA444802E +#define RSPR15 0xA444802F +#define RSPR16 0xA4448030 +#define RSPRD 0xA4448031 +#define DTOUTR 0xA4448032 +#define DR 0xA4448040 +#define FIFOCLR 0xA4448042 +#define DMACR 0xA4448044 +#define INTCR2 0xA4448046 +#define INTSTR2 0xA4448048 + +/* Z3D3 */ +#define DLBI 0xFD980000 +#define DLBD0 0xFD980080 +#define DLBD1 0xFD980100 +#define GEWM 0xFD984000 +#define ICD0 0xFD988000 +#define ICD1 0xFD989000 +#define ICT 0xFD98A000 +#define ILM 0xFD98C000 +#define FLM0 0xFD98C800 +#define FLM1 0xFD98D000 +#define FLUT 0xFD98D800 +#define Z3D_PC 0xFD98E400 +#define Z3D_PCSP 0xFD98E404 +#define Z3D_PAR 0xFD98E408 +#define Z3D_IMADR 0xFD98E40C +#define Z3D_BTR0 0xFD98E410 +#define Z3D_BTR1 0xFD98E414 +#define Z3D_BTR2 0xFD98E418 +#define Z3D_BTR3 0xFD98E41C +#define Z3D_LC0 0xFD98E420 +#define Z3D_LC1 0xFD98E424 +#define Z3D_LC2 0xFD98E428 +#define Z3D_LC3 0xFD98E42C +#define Z3D_FR0 0xFD98E430 +#define Z3D_FR1 0xFD98E434 +#define Z3D_FR2 0xFD98E438 +#define Z3D_SR 0xFD98E440 +#define Z3D_SMDR 0xFD98E444 +#define Z3D_PBIR 0xFD98E448 +#define Z3D_DMDR 0xFD98E44C +#define Z3D_IREG 0xFD98E460 +#define Z3D_AR00 0xFD98E480 +#define Z3D_AR01 0xFD98E484 +#define Z3D_AR02 0xFD98E488 +#define Z3D_AR03 0xFD98E48C +#define Z3D_BR00 0xFD98E490 +#define Z3D_BR01 0xFD98E494 +#define Z3D_IXR00 0xFD98E4A0 +#define Z3D_IXR01 0xFD98E4A4 +#define Z3D_IXR02 0xFD98E4A8 +#define Z3D_IXR03 0xFD98E4AC +#define Z3D_AR10 0xFD98E4C0 +#define Z3D_AR11 0xFD98E4C4 +#define Z3D_AR12 0xFD98E4C8 +#define Z3D_AR13 0xFD98E4CC +#define Z3D_BR10 0xFD98E4D0 +#define Z3D_BR11 0xFD98E4D4 +#define Z3D_IXR10 0xFD98E4E0 +#define Z3D_IXR11 0xFD98E4E4 +#define Z3D_IXR12 0xFD98E4E8 +#define Z3D_IXR13 0xFD98E4EC +#define Z3D_AR20 0xFD98E500 +#define Z3D_AR21 0xFD98E504 +#define Z3D_AR22 0xFD98E508 +#define Z3D_AR23 0xFD98E50C +#define Z3D_BR20 0xFD98E510 +#define Z3D_BR21 0xFD98E514 +#define Z3D_IXR20 0xFD98E520 +#define Z3D_IXR21 0xFD98E524 +#define Z3D_IXR22 0xFD98E528 +#define Z3D_IXR23 0xFD98E52C +#define Z3D_MR0 0xFD98E540 +#define Z3D_MR1 0xFD98E544 +#define Z3D_MR2 0xFD98E548 +#define Z3D_MR3 0xFD98E54C +#define Z3D_WORKRST 0xFD98E558 +#define Z3D_WORKWST 0xFD98E55C +#define Z3D_DBADR 0xFD98E560 +#define Z3D_DLBPRST 0xFD98E564 +#define Z3D_DLBRST 0xFD98E568 +#define Z3D_DLBWST 0xFD98E56C +#define Z3D_UDR0 0xFD98E570 +#define Z3D_UDR1 0xFD98E574 +#define Z3D_UDR2 0xFD98E578 +#define Z3D_UDR3 0xFD98E57C +#define Z3D_CCR0 0xFD98E580 +#define Z3D_CCR1 0xFD98E584 +#define Z3D_EXPR 0xFD98E588 +#define Z3D_V0_X 0xFD9A0000 +#define Z3D_V0_Y 0xFD9A0004 +#define Z3D_V0_Z 0xFD9A0008 +#define Z3D_V0_W 0xFD9A000C +#define Z3D_V0_A 0xFD9A0010 +#define Z3D_V0_R 0xFD9A0014 +#define Z3D_V0_G 0xFD9A0018 +#define Z3D_V0_B 0xFD9A001C +#define Z3D_V0_F 0xFD9A0020 +#define Z3D_V0_SR 0xFD9A0024 +#define Z3D_V0_SG 0xFD9A0028 +#define Z3D_V0_SB 0xFD9A002C +#define Z3D_V0_U0 0xFD9A0030 +#define Z3D_V0_V0 0xFD9A0034 +#define Z3D_V0_U1 0xFD9A0038 +#define Z3D_V0_V1 0xFD9A003C +#define Z3D_V1_X 0xFD9A0080 +#define Z3D_V1_Y 0xFD9A0084 +#define Z3D_V1_Z 0xFD9A0088 +#define Z3D_V1_W 0xFD9A008C +#define Z3D_V1_A 0xFD9A0090 +#define Z3D_V1_R 0xFD9A0094 +#define Z3D_V1_G 0xFD9A0098 +#define Z3D_V1_B 0xFD9A009C +#define Z3D_V1_F 0xFD9A00A0 +#define Z3D_V1_SR 0xFD9A00A4 +#define Z3D_V1_SG 0xFD9A00A8 +#define Z3D_V1_SB 0xFD9A00AC +#define Z3D_V1_U0 0xFD9A00B0 +#define Z3D_V1_V0 0xFD9A00B4 +#define Z3D_V1_U1 0xFD9A00B8 +#define Z3D_V1_V1 0xFD9A00BC +#define Z3D_V2_X 0xFD9A0100 +#define Z3D_V2_Y 0xFD9A0104 +#define Z3D_V2_Z 0xFD9A0108 +#define Z3D_V2_W 0xFD9A010C +#define Z3D_V2_A 0xFD9A0110 +#define Z3D_V2_R 0xFD9A0114 +#define Z3D_V2_G 0xFD9A0118 +#define Z3D_V2_B 0xFD9A011C +#define Z3D_V2_F 0xFD9A0120 +#define Z3D_V2_SR 0xFD9A0124 +#define Z3D_V2_SG 0xFD9A0128 +#define Z3D_V2_SB 0xFD9A012C +#define Z3D_V2_U0 0xFD9A0130 +#define Z3D_V2_V0 0xFD9A0134 +#define Z3D_V2_U1 0xFD9A0138 +#define Z3D_V2_V1 0xFD9A013C +#define Z3D_RENDER 0xFD9A0180 +#define Z3D_POLYGON_OFFSET 0xFD9A0184 +#define Z3D_VERTEX_CONTROL 0xFD9A0200 +#define Z3D_STATE_MODE 0xFD9A0204 +#define Z3D_FPU_MODE 0xFD9A0318 +#define Z3D_SCISSOR_MIN 0xFD9A0400 +#define Z3D_SCISSOR_MAX 0xFD9A0404 +#define Z3D_TEXTURE_MODE_A 0xFD9A0408 +#define Z3D_TEXTURE_MODE_B 0xFD9A040C +#define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418 +#define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C +#define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420 +#define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424 +#define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438 +#define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C +#define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440 +#define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444 +#define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448 +#define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C +#define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450 +#define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454 +#define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458 +#define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C +#define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460 +#define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464 +#define Z3D_TEXTURE_FLUSH 0xFD9A0498 +#define Z3D_GAMMA_TABLE0 0xFD9A049C +#define Z3D_GAMMA_TABLE1 0xFD9A04A0 +#define Z3D_GAMMA_TABLE2 0xFD9A04A4 +#define Z3D_ALPHA_TEST 0xFD9A0800 +#define Z3D_STENCIL_TEST 0xFD9A0804 +#define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808 +#define Z3D_MASK 0xFD9A080C +#define Z3D_FBUS_MODE 0xFD9A0810 +#define Z3D_GNT_SET 0xFD9A0814 +#define Z3D_BETWEEN_TEST 0xFD9A0818 +#define Z3D_FB_BASE 0xFD9A081C +#define Z3D_LCD_SIZE 0xFD9A0820 +#define Z3D_FB_FLUSH 0xFD9A0824 +#define Z3D_CACHE_INVALID 0xFD9A0828 +#define Z3D_SC_MODE 0xFD9A0830 +#define Z3D_SC0_MIN 0xFD9A0834 +#define Z3D_SC0_MAX 0xFD9A0838 +#define Z3D_SC1_MIN 0xFD9A083C +#define Z3D_SC1_MAX 0xFD9A0840 +#define Z3D_SC2_MIN 0xFD9A0844 +#define Z3D_SC2_MAX 0xFD9A0848 +#define Z3D_SC3_MIN 0xFD9A084C +#define Z3D_SC3_MAX 0xFD9A0850 +#define Z3D_READRESET 0xFD9A0854 +#define Z3D_DET_MIN 0xFD9A0858 +#define Z3D_DET_MAX 0xFD9A085C +#define Z3D_FB_BASE_SR 0xFD9A0860 +#define Z3D_LCD_SIZE_SR 0xFD9A0864 +#define Z3D_2D_CTRL_STATUS 0xFD9A0C00 +#define Z3D_2D_SIZE 0xFD9A0C04 +#define Z3D_2D_SRCLOC 0xFD9A0C08 +#define Z3D_2D_DSTLOC 0xFD9A0C0C +#define Z3D_2D_DMAPORT 0xFD9A0C10 +#define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14 +#define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18 +#define Z3D_2D_STPCOLOR0 0xFD9A0C1C +#define Z3D_2D_STPCOLOR1 0xFD9A0C20 +#define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24 +#define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28 +#define Z3D_2D_STPPAT_0 0xFD9A0C40 +#define Z3D_2D_STPPAT_1 0xFD9A0C44 +#define Z3D_2D_STPPAT_2 0xFD9A0C48 +#define Z3D_2D_STPPAT_3 0xFD9A0C4C +#define Z3D_2D_STPPAT_4 0xFD9A0C50 +#define Z3D_2D_STPPAT_5 0xFD9A0C54 +#define Z3D_2D_STPPAT_6 0xFD9A0C58 +#define Z3D_2D_STPPAT_7 0xFD9A0C5C +#define Z3D_2D_STPPAT_8 0xFD9A0C60 +#define Z3D_2D_STPPAT_9 0xFD9A0C64 +#define Z3D_2D_STPPAT_10 0xFD9A0C68 +#define Z3D_2D_STPPAT_11 0xFD9A0C6C +#define Z3D_2D_STPPAT_12 0xFD9A0C70 +#define Z3D_2D_STPPAT_13 0xFD9A0C74 +#define Z3D_2D_STPPAT_14 0xFD9A0C78 +#define Z3D_2D_STPPAT_15 0xFD9A0C7C +#define Z3D_2D_STPPAT_16 0xFD9A0C80 +#define Z3D_2D_STPPAT_17 0xFD9A0C84 +#define Z3D_2D_STPPAT_18 0xFD9A0C88 +#define Z3D_2D_STPPAT_19 0xFD9A0C8C +#define Z3D_2D_STPPAT_20 0xFD9A0C90 +#define Z3D_2D_STPPAT_21 0xFD9A0C94 +#define Z3D_2D_STPPAT_22 0xFD9A0C98 +#define Z3D_2D_STPPAT_23 0xFD9A0C9C +#define Z3D_2D_STPPAT_24 0xFD9A0CA0 +#define Z3D_2D_STPPAT_25 0xFD9A0CA4 +#define Z3D_2D_STPPAT_26 0xFD9A0CA8 +#define Z3D_2D_STPPAT_27 0xFD9A0CAC +#define Z3D_2D_STPPAT_28 0xFD9A0CB0 +#define Z3D_2D_STPPAT_29 0xFD9A0CB4 +#define Z3D_2D_STPPAT_30 0xFD9A0CB8 +#define Z3D_2D_STPPAT_31 0xFD9A0CBC +#define Z3D_WR_CTRL 0xFD9A1000 +#define Z3D_WR_P0 0xFD9A1004 +#define Z3D_WR_P1 0xFD9A1008 +#define Z3D_WR_P2 0xFD9A100C +#define Z3D_WR_FGC 0xFD9A1010 +#define Z3D_WR_BGC 0xFD9A1014 +#define Z3D_WR_SZ 0xFD9A1018 +#define Z3D_WR_PATPARAM 0xFD9A101C +#define Z3D_WR_PAT 0xFD9A1020 +#define Z3D_SYS_STATUS 0xFD9A1400 +#define Z3D_SYS_RESET 0xFD9A1404 +#define Z3D_SYS_CLK 0xFD9A1408 +#define Z3D_SYS_CONF 0xFD9A140C +#define Z3D_SYS_VERSION 0xFD9A1410 +#define Z3D_SYS_DBINV 0xFD9A1418 +#define Z3D_SYS_I2F_FMT 0xFD9A1420 +#define Z3D_SYS_I2F_SRC 0xFD9A1424 +#define Z3D_SYS_I2F_DST 0xFD9A1428 +#define Z3D_SYS_GBCNT 0xFD9A1430 +#define Z3D_SYS_BSYCNT 0xFD9A1434 +#define Z3D_SYS_INT_STATUS 0xFD9A1450 +#define Z3D_SYS_INT_MASK 0xFD9A1454 +#define Z3D_SYS_INT_CLEAR 0xFD9A1458 +#define TCD0 0xFD9C0000 +#define TCD1 0xFD9C0400 +#define TCD2 0xFD9C0800 +#define TCD3 0xFD9C0C00 +#define TCT0 0xFD9C1000 +#define TCT1 0xFD9C1400 +#define TCT2 0xFD9C1800 +#define TCT3 0xFD9C1C00 + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PDCR 0xA4050106 +#define PECR 0xA4050108 +#define PFCR 0xA405010A +#define PGCR 0xA405010C +#define PHCR 0xA405010E +#define PJCR 0xA4050110 +#define PKCR 0xA4050112 +#define PLCR 0xA4050114 +#define PMCR 0xA4050116 +#define PNCR 0xA4050118 +#define PQCR 0xA405011A +#define PRCR 0xA405011C +#define PSCR 0xA405011E +#define PTCR 0xA4050140 +#define PUCR 0xA4050142 +#define PVCR 0xA4050144 +#define PWCR 0xA4050146 +#define PXCR 0xA4050148 +#define PYCR 0xA405014A +#define PZCR 0xA405014C +#define PSELA 0xA405014E +#define PSELB 0xA4050150 +#define PSELC 0xA4050152 +#define PSELD 0xA4050154 +#define PSELE 0xA4050156 +#define HIZCRA 0xA4050158 +#define HIZCRB 0xA405015A +#define HIZCRC 0xA405015C +#define MSELCR 0xA405015C +#define PULCR 0xA405015E +#define DRVCR 0xA4050180 +#define SBSCR 0xA4050182 +#define AUDTHCR 0xA4050184 +#define PSELF 0xA4050186 + +/* I/O Port */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 +#define PDDR 0xA4050126 +#define PEDR 0xA4050128 +#define PFDR 0xA405012A +#define PGDR 0xA405012C +#define PHDR 0xA405012E +#define PJDR 0xA4050130 +#define PKDR 0xA4050132 +#define PLDR 0xA4050134 +#define PMDR 0xA4050136 +#define PNDR 0xA4050138 +#define PQDR 0xA405013A +#define PRDR 0xA405013C +#define PSDR 0xA405013E +#define PTDR 0xA4050160 +#define PUDR 0xA4050162 +#define PVDR 0xA4050164 +#define PWDR 0xA4050166 +#define PYDR 0xA4050168 +#define PZDR 0xA405016A + +/* UBC */ +#define CBR0 0xFF200000 +#define CRR0 0xFF200004 +#define CAR0 0xFF200008 +#define CAMR0 0xFF20000C +#define CBR1 0xFF200020 +#define CRR1 0xFF200024 +#define CAR1 0xFF200028 +#define CAMR1 0xFF20002C +#define CDR1 0xFF200030 +#define CDMR1 0xFF200034 +#define CETR1 0xFF200038 +#define CCMFR 0xFF200600 +#define CBCR 0xFF200620 + +/* H-UDI */ +#define SDIR 0xFC110000 +#define SDDRH 0xFC110008 +#define SDDRL 0xFC11000A +#define SDINT 0xFC110018 + +#endif /* _ASM_CPU_SH7722_H_ */ diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h new file mode 100644 index 0000000000..bb6461a6bf --- /dev/null +++ b/include/asm-sh/cpu_sh7750.h @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * SH7750/SH7750S/SH7750R/SH7751/SH7751R + * Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH7750_H_ +#define _ASM_CPU_SH7750_H_ + +#ifdef CONFIG_CPU_TYPE_R +#define CACHE_OC_NUM_WAYS 2 +#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ +#else +#define CACHE_OC_NUM_WAYS 1 +#define CCR_CACHE_INIT 0x0000090b +#endif + +/* OCN */ +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define BASRA 0xFF000014 +#define BASRB 0xFF000018 +#define CCR 0xFF00001C +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 +#define PTEA 0xFF000034 +#define QACR0 0xFF000038 +#define QACR1 0xFF00003C + +/* UBC */ +#define BARA 0xFF200000 +#define BAMRA 0xFF200004 +#define BBRA 0xFF200008 +#define BARB 0xFF20000C +#define BAMRB 0xFF200010 +#define BBRB 0xFF200014 +#define BDRB 0xFF200018 +#define BDMRB 0xFF20001C +#define BRCR 0xFF200020 + +/* BSC */ +#define BCR1 0xFF800000 +#define BCR2 0xFF800004 +#define BCR3 0xFF800050 +#define BCR4 0xFE0A00F0 +#define WCR1 0xFF800008 +#define WCR2 0xFF80000C +#define WCR3 0xFF800010 +#define MCR 0xFF800014 +#define PCR 0xFF800018 +#define RTCSR 0xFF80001C +#define RTCNT 0xFF800020 +#define RTCOR 0xFF800024 +#define RFCR 0xFF800028 +#define PCTRA 0xFF80002C +#define PDTRA 0xFF800030 +#define PCTRB 0xFF800040 +#define PDTRB 0xFF800044 +#define GPIOIC 0xFF800048 + +/* DMAC */ +#define SAR0 0xFFA00000 +#define DAR0 0xFFA00004 +#define DMATCR0 0xFFA00008 +#define CHCR0 0xFFA0000C +#define SAR1 0xFFA00010 +#define DAR1 0xFFA00014 +#define DMATCR1 0xFFA00018 +#define CHCR1 0xFFA0001C +#define SAR2 0xFFA00020 +#define DAR2 0xFFA00024 +#define DMATCR2 0xFFA00028 +#define CHCR2 0xFFA0002C +#define SAR3 0xFFA00030 +#define DAR3 0xFFA00034 +#define DMATCR3 0xFFA00038 +#define CHCR3 0xFFA0003C +#define DMAOR 0xFFA00040 +#define SAR4 0xFFA00050 +#define DAR4 0xFFA00054 +#define DMATCR4 0xFFA00058 + +/* CPG */ +#define FRQCR 0xFFC00000 +#define STBCR 0xFFC00004 +#define WTCNT 0xFFC00008 +#define WTCSR 0xFFC0000C +#define STBCR2 0xFFC00010 + +/* RTC */ +#define R64CNT 0xFFC80000 +#define RSECCNT 0xFFC80004 +#define RMINCNT 0xFFC80008 +#define RHRCNT 0xFFC8000C +#define RWKCNT 0xFFC80010 +#define RDAYCNT 0xFFC80014 +#define RMONCNT 0xFFC80018 +#define RYRCNT 0xFFC8001C +#define RSECAR 0xFFC80020 +#define RMINAR 0xFFC80024 +#define RHRAR 0xFFC80028 +#define RWKAR 0xFFC8002C +#define RDAYAR 0xFFC80030 +#define RMONAR 0xFFC80034 +#define RCR1 0xFFC80038 +#define RCR2 0xFFC8003C +#define RCR3 0xFFC80050 +#define RYRAR 0xFFC80054 + +/* ICR */ +#define ICR 0xFFD00000 +#define IPRA 0xFFD00004 +#define IPRB 0xFFD00008 +#define IPRC 0xFFD0000C +#define IPRD 0xFFD00010 +#define INTPRI 0xFE080000 +#define INTREQ 0xFE080020 +#define INTMSK 0xFE080040 +#define INTMSKCL 0xFE080060 + +/* CPG */ +#define CLKSTP 0xFE0A0000 +#define CLKSTPCLR 0xFE0A0008 + +/* TMU */ +#define TSTR2 0xFE100004 +#define TCOR3 0xFE100008 +#define TCNT3 0xFE10000C +#define TCR3 0xFE100010 +#define TCOR4 0xFE100014 +#define TCNT4 0xFE100018 +#define TCR4 0xFE10001C +#define TOCR 0xFFD80000 +#define TSTR0 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 +#define TCPR2 0xFFD8002C +#define TSTR TSTR0 + +/* SCI */ +#define SCSMR1 0xFFE00000 +#define SCBRR1 0xFFE00004 +#define SCSCR1 0xFFE00008 +#define SCTDR1 0xFFE0000C +#define SCSSR1 0xFFE00010 +#define SCRDR1 0xFFE00014 +#define SCSCMR1 0xFFE00018 +#define SCSPTR1 0xFFE0001C +#define SCF0_BASE SCSMR1 + +/* SCIF */ +#define SCSMR2 0xFFE80000 +#define SCBRR2 0xFFE80004 +#define SCSCR2 0xFFE80008 +#define SCFTDR2 0xFFE8000C +#define SCFSR2 0xFFE80010 +#define SCFRDR2 0xFFE80014 +#define SCFCR2 0xFFE80018 +#define SCFDR2 0xFFE8001C +#define SCSPTR2 0xFFE80020 +#define SCLSR2 0xFFE80024 +#define SCIF1_BASE SCSMR2 + +/* H-UDI */ +#define SDIR 0xFFF00000 +#define SDDR 0xFFF00008 +#define SDINT 0xFFF00014 + +#endif /* _ASM_CPU_SH7750_H_ */ diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h new file mode 100644 index 0000000000..0d2c618030 --- /dev/null +++ b/include/asm-sh/errno.h @@ -0,0 +1,156 @@ +/* + * U-boot - errno.h Error number defines + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _BLACKFIN_ERRNO_H +#define _BLACKFIN_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h new file mode 100644 index 0000000000..0a44a34cef --- /dev/null +++ b/include/asm-sh/global_data.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_SH_GLOBALDATA_H_ +#define __ASM_SH_GLOBALDATA_H_ + +typedef struct global_data +{ + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid */ + void **jt; /* Standalone app jump table */ +}gd_t; + +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13") + +#endif /* __ASM_SH_GLOBALDATA_H_ */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h new file mode 100644 index 0000000000..03427ad33b --- /dev/null +++ b/include/asm-sh/io.h @@ -0,0 +1,231 @@ +/* + * linux/include/asm-sh/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_SH_IO_H +#define __ASM_SH_IO_H + +#ifdef __KERNEL__ + +#include <linux/types.h> +#include <asm/byteorder.h> + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) __arch_putb(v,a) +#define __raw_writew(v,a) __arch_putw(v,a) +#define __raw_writel(v,a) __arch_putl(v,a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) +#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) +#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) + +#define __raw_base_readb(base,off) __arch_base_getb(base,off) +#define __raw_base_readw(base,off) __arch_base_getw(base,off) +#define __raw_base_readl(base,off) __arch_base_getl(base,off) + +/* + * Now, pick up the machine-defined IO definitions + */ +#if 0 /* XXX###XXX */ +#include <asm/arch/io.h> +#endif /* XXX###XXX */ + +/* + * IO port access primitives + * ------------------------- + * + * The SH doesn't have special IO access instructions; all IO is memory + * mapped. Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#define outb(v,p) __raw_writeb(v, p) +#define outw(v,p) __raw_writew(cpu_to_le16(v),p) +#define outl(v,p) __raw_writel(cpu_to_le32(v),p) + +#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) +#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) +#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) + +#define outsb(p,d,l) __raw_writesb(p,d,l) +#define outsw(p,d,l) __raw_writesw(p,d,l) +#define outsl(p,d,l) __raw_writesl(p,d,l) + +#define insb(p,d,l) __raw_readsb(p,d,l) +#define insw(p,d,l) __raw_readsw(p,d,l) +#define insl(p,d,l) __raw_readsl(p,d,l) + +#define outb_p(val,port) outb((val),(port)) +#define outw_p(val,port) outw((val),(port)) +#define outl_p(val,port) outl((val),(port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. If you want a + * physical address, use __ioremap instead. + */ +extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); +extern void __iounmap(void *addr); + +/* + * Generic ioremap support. + * + * Define: + * iomem_valid_addr(off,size) + * iomem_to_phys(off) + */ +#ifdef iomem_valid_addr +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret; \ + }) + +#define __arch_iounmap __iounmap +#endif + +#define ioremap(off,sz) __arch_ioremap((off),(sz),0) +#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) +#define iounmap(_addr) __arch_iounmap(_addr) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) +#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) + +#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) +#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) +#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) + +#define eth_io_copy_and_sum(s,c,l,b) \ + eth_copy_and_sum((s),__mem_pci(c),(l),(b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#elif !defined(readb) + +#define readb(addr) __raw_readb(addr) +#define readw(addr) __raw_readw(addr) +#define readl(addr) __raw_readl(addr) +#define writeb(v,addr) __raw_writeb(v, addr) +#define writew(v,addr) __raw_writew(v, addr) +#define writel(v,addr) __raw_writel(v, addr) + +#define check_signature(io,sig,len) (0) + +#endif /* __mem_pci */ + +static inline void sync(void) +{ +} +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_IO_H */ diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h new file mode 100644 index 0000000000..830e5486ac --- /dev/null +++ b/include/asm-sh/irqflags.h @@ -0,0 +1,126 @@ +#ifndef __ASM_SH_IRQFLAGS_H +#define __ASM_SH_IRQFLAGS_H + +static inline void raw_local_irq_enable(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and %1, %0\n\t" +#ifdef CONFIG_CPU_HAS_SR_RB + "stc r6_bank, %1\n\t" + "or %1, %0\n\t" +#endif + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "1" (~0x000000f0) + : "memory" + ); +} + +static inline void raw_local_irq_disable(void) +{ + unsigned long flags; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "or #0xf0, %0\n\t" + "ldc %0, sr\n\t" + : "=&z" (flags) + : /* no inputs */ + : "memory" + ); +} + +static inline void set_bl_bit(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "or %2, %0\n\t" + "and %3, %0\n\t" + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "r" (0x10000000), "r" (0xffffff0f) + : "memory" + ); +} + +static inline void clear_bl_bit(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and %2, %0\n\t" + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "1" (~0x10000000) + : "memory" + ); +} + +static inline unsigned long __raw_local_save_flags(void) +{ + unsigned long flags; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and #0xf0, %0\n\t" + : "=&z" (flags) + : /* no inputs */ + : "memory" + ); + + return flags; +} + +#define raw_local_save_flags(flags) \ + do { (flags) = __raw_local_save_flags(); } while (0) + +static inline int raw_irqs_disabled_flags(unsigned long flags) +{ + return (flags != 0); +} + +static inline int raw_irqs_disabled(void) +{ + unsigned long flags = __raw_local_save_flags(); + + return raw_irqs_disabled_flags(flags); +} + +static inline unsigned long __raw_local_irq_save(void) +{ + unsigned long flags, __dummy; + + __asm__ __volatile__ ( + "stc sr, %1\n\t" + "mov %1, %0\n\t" + "or #0xf0, %0\n\t" + "ldc %0, sr\n\t" + "mov %1, %0\n\t" + "and #0xf0, %0\n\t" + : "=&z" (flags), "=&r" (__dummy) + : /* no inputs */ + : "memory" + ); + + return flags; +} + +#define raw_local_irq_save(flags) \ + do { (flags) = __raw_local_irq_save(); } while (0) + +#define local_irq_save raw_local_irq_save + +static inline void raw_local_irq_restore(unsigned long flags) +{ + if ((flags & 0xf0) != 0xf0) + raw_local_irq_enable(); +} +#define local_irq_restore raw_local_irq_restore + +#endif /* __ASM_SH_IRQFLAGS_H */ diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h new file mode 100644 index 0000000000..c9d9fb84f1 --- /dev/null +++ b/include/asm-sh/posix_types.h @@ -0,0 +1,123 @@ +#ifndef __ASM_SH_POSIX_TYPES_H +#define __ASM_SH_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +typedef unsigned short __kernel_old_dev_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __ASM_SH_POSIX_TYPES_H */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h new file mode 100644 index 0000000000..bb9a35f643 --- /dev/null +++ b/include/asm-sh/processor.h @@ -0,0 +1,8 @@ +#ifndef _ASM_SH_PROCESSOR_H_ +#define _ASM_SH_PROCESSOR_H_ +#if defined CONFIG_SH3 +# include <asm/cpu_sh3.h> +#elif defined (CONFIG_SH4) +# include <asm/cpu_sh4.h> +#endif +#endif diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h new file mode 100644 index 0000000000..14cc1aca63 --- /dev/null +++ b/include/asm-sh/ptrace.h @@ -0,0 +1,112 @@ +#ifndef __ASM_SH_PTRACE_H +#define __ASM_SH_PTRACE_H + +/* + * Copyright (C) 1999, 2000 Niibe Yutaka + * from linux kernel code. + */ + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 15 are integer registers + * 17 - 22 are control/special registers + * 24 - 39 fp registers + * 40 - 47 xd registers + * 48 - fpscr register + * ----------------------------- + * + * We follows above, except: + * 16 --- program counter (PC) + * 22 --- syscall # + * 23 --- floating point communication register + */ +#define REG_REG0 0 +#define REG_REG15 15 + +#define REG_PC 16 + +#define REG_PR 17 +#define REG_SR 18 +#define REG_GBR 19 +#define REG_MACH 20 +#define REG_MACL 21 + +#define REG_SYSCALL 22 + +#define REG_FPREG0 23 +#define REG_FPREG15 38 +#define REG_XFREG0 39 +#define REG_XFREG15 54 + +#define REG_FPSCR 55 +#define REG_FPUL 56 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_regs { + unsigned long regs[16]; + unsigned long pc; + unsigned long pr; + unsigned long sr; + unsigned long gbr; + unsigned long mach; + unsigned long macl; + long tra; +}; + +/* + * This struct defines the way the DSP registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_dspregs { + unsigned long a1; + unsigned long a0g; + unsigned long a1g; + unsigned long m0; + unsigned long m1; + unsigned long a0; + unsigned long x0; + unsigned long x1; + unsigned long y0; + unsigned long y1; + unsigned long dsr; + unsigned long rs; + unsigned long re; + unsigned long mod; +}; + +#define PTRACE_GETDSPREGS 55 +#define PTRACE_SETDSPREGS 56 + +#ifdef __KERNEL__ +#define user_mode(regs) (((regs)->sr & 0x40000000)==0) +#define instruction_pointer(regs) ((regs)->pc) +extern void show_regs(struct pt_regs *); + +#ifdef CONFIG_SH_DSP +#define task_pt_regs(task) \ + ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ + - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1) +#else +#define task_pt_regs(task) \ + ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ + - sizeof(unsigned long)) - 1) +#endif + +static inline unsigned long profile_pc(struct pt_regs *regs) +{ + unsigned long pc = instruction_pointer(regs); + + if (pc >= 0xa0000000UL && pc < 0xc0000000UL) + pc -= 0x20000000; + return pc; +} +#endif + +#endif /* __ASM_SH_PTRACE_H */ diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h new file mode 100644 index 0000000000..27d981b79a --- /dev/null +++ b/include/asm-sh/string.h @@ -0,0 +1,162 @@ +#ifndef __ASM_SH_STRING_H +#define __ASM_SH_STRING_H + +/* + * Copyright (C) 1999 Niibe Yutaka + * But consider these trivial functions to be public domain. + * + * from linux kernel code. + */ + +#ifdef __KERNEL__ /* only set these up for kernel code */ + +#define __HAVE_ARCH_STRCPY +static inline char *strcpy(char *__dest, const char *__src) +{ + register char *__xdest = __dest; + unsigned long __dummy; + + __asm__ __volatile__("1:\n\t" + "mov.b @%1+, %2\n\t" + "mov.b %2, @%0\n\t" + "cmp/eq #0, %2\n\t" + "bf/s 1b\n\t" + " add #1, %0\n\t" + : "=r" (__dest), "=r" (__src), "=&z" (__dummy) + : "0" (__dest), "1" (__src) + : "memory", "t"); + + return __xdest; +} + +#define __HAVE_ARCH_STRNCPY +static inline char *strncpy(char *__dest, const char *__src, size_t __n) +{ + register char *__xdest = __dest; + unsigned long __dummy; + + if (__n == 0) + return __xdest; + + __asm__ __volatile__( + "1:\n" + "mov.b @%1+, %2\n\t" + "mov.b %2, @%0\n\t" + "cmp/eq #0, %2\n\t" + "bt/s 2f\n\t" + " cmp/eq %5,%1\n\t" + "bf/s 1b\n\t" + " add #1, %0\n" + "2:" + : "=r" (__dest), "=r" (__src), "=&z" (__dummy) + : "0" (__dest), "1" (__src), "r" (__src+__n) + : "memory", "t"); + + return __xdest; +} + +#define __HAVE_ARCH_STRCMP +static inline int strcmp(const char *__cs, const char *__ct) +{ + register int __res; + unsigned long __dummy; + + __asm__ __volatile__( + "mov.b @%1+, %3\n" + "1:\n\t" + "mov.b @%0+, %2\n\t" + "cmp/eq #0, %3\n\t" + "bt 2f\n\t" + "cmp/eq %2, %3\n\t" + "bt/s 1b\n\t" + " mov.b @%1+, %3\n\t" + "add #-2, %1\n\t" + "mov.b @%1, %3\n\t" + "sub %3, %2\n" + "2:" + : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) + : "0" (__cs), "1" (__ct) + : "t"); + + return __res; +} + +#define __HAVE_ARCH_STRNCMP +static inline int strncmp(const char *__cs, const char *__ct, size_t __n) +{ + register int __res; + unsigned long __dummy; + + if (__n == 0) + return 0; + + __asm__ __volatile__( + "mov.b @%1+, %3\n" + "1:\n\t" + "mov.b @%0+, %2\n\t" + "cmp/eq %6, %0\n\t" + "bt/s 2f\n\t" + " cmp/eq #0, %3\n\t" + "bt/s 3f\n\t" + " cmp/eq %3, %2\n\t" + "bt/s 1b\n\t" + " mov.b @%1+, %3\n\t" + "add #-2, %1\n\t" + "mov.b @%1, %3\n" + "2:\n\t" + "sub %3, %2\n" + "3:" + :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) + : "0" (__cs), "1" (__ct), "r" (__cs+__n) + : "t"); + + return __res; +} + +#undef __HAVE_ARCH_MEMSET +extern void *memset(void *__s, int __c, size_t __count); + +#undef __HAVE_ARCH_MEMCPY +extern void *memcpy(void *__to, __const__ void *__from, size_t __n); + +#undef __HAVE_ARCH_MEMMOVE +extern void *memmove(void *__dest, __const__ void *__src, size_t __n); + +#undef __HAVE_ARCH_MEMCHR +extern void *memchr(const void *__s, int __c, size_t __n); + +#undef __HAVE_ARCH_STRLEN +extern size_t strlen(const char *); + +/* arch/sh/lib/strcasecmp.c */ +extern int strcasecmp(const char *, const char *); + +#else /* KERNEL */ + +/* + * let user libraries deal with these, + * IMHO the kernel has no place defining these functions for user apps + */ + +#define __HAVE_ARCH_STRCPY 1 +#define __HAVE_ARCH_STRNCPY 1 +#define __HAVE_ARCH_STRCAT 1 +#define __HAVE_ARCH_STRNCAT 1 +#define __HAVE_ARCH_STRCMP 1 +#define __HAVE_ARCH_STRNCMP 1 +#define __HAVE_ARCH_STRNICMP 1 +#define __HAVE_ARCH_STRCHR 1 +#define __HAVE_ARCH_STRRCHR 1 +#define __HAVE_ARCH_STRSTR 1 +#define __HAVE_ARCH_STRLEN 1 +#define __HAVE_ARCH_STRNLEN 1 +#define __HAVE_ARCH_MEMSET 1 +#define __HAVE_ARCH_MEMCPY 1 +#define __HAVE_ARCH_MEMMOVE 1 +#define __HAVE_ARCH_MEMSCAN 1 +#define __HAVE_ARCH_MEMCMP 1 +#define __HAVE_ARCH_MEMCHR 1 +#define __HAVE_ARCH_STRTOK 1 + +#endif /* KERNEL */ +#endif /* __ASM_SH_STRING_H */ diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h new file mode 100644 index 0000000000..b353bc5c3b --- /dev/null +++ b/include/asm-sh/system.h @@ -0,0 +1,275 @@ +#ifndef __ASM_SH_SYSTEM_H +#define __ASM_SH_SYSTEM_H + +/* + * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima + * Copyright (C) 2002 Paul Mundt + * + * from linux kernel code. + */ + +#include <linux/irqflags.h> +#include <asm/types.h> + +/* + * switch_to() should switch tasks to task nr n, first + */ + +#define switch_to(prev, next, last) do { \ + struct task_struct *__last; \ + register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \ + register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \ + register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \ + register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \ + register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \ + register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \ + __asm__ __volatile__ (".balign 4\n\t" \ + "stc.l gbr, @-r15\n\t" \ + "sts.l pr, @-r15\n\t" \ + "mov.l r8, @-r15\n\t" \ + "mov.l r9, @-r15\n\t" \ + "mov.l r10, @-r15\n\t" \ + "mov.l r11, @-r15\n\t" \ + "mov.l r12, @-r15\n\t" \ + "mov.l r13, @-r15\n\t" \ + "mov.l r14, @-r15\n\t" \ + "mov.l r15, @r1 ! save SP\n\t" \ + "mov.l @r6, r15 ! change to new stack\n\t" \ + "mova 1f, %0\n\t" \ + "mov.l %0, @r2 ! save PC\n\t" \ + "mov.l 2f, %0\n\t" \ + "jmp @%0 ! call __switch_to\n\t" \ + " lds r7, pr ! with return to new PC\n\t" \ + ".balign 4\n" \ + "2:\n\t" \ + ".long __switch_to\n" \ + "1:\n\t" \ + "mov.l @r15+, r14\n\t" \ + "mov.l @r15+, r13\n\t" \ + "mov.l @r15+, r12\n\t" \ + "mov.l @r15+, r11\n\t" \ + "mov.l @r15+, r10\n\t" \ + "mov.l @r15+, r9\n\t" \ + "mov.l @r15+, r8\n\t" \ + "lds.l @r15+, pr\n\t" \ + "ldc.l @r15+, gbr\n\t" \ + : "=z" (__last) \ + : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ + "r" (__ts5), "r" (__ts6), "r" (__ts7) \ + : "r3", "t"); \ + last = __last; \ +} while (0) + +/* + * On SMP systems, when the scheduler does migration-cost autodetection, + * it needs a way to flush as much of the CPU's caches as possible. + * + * TODO: fill this in! + */ +static inline void sched_cacheflush(void) +{ +} + +#ifdef CONFIG_CPU_SH4A +#define __icbi() \ +{ \ + unsigned long __addr; \ + __addr = 0xa8000000; \ + __asm__ __volatile__( \ + "icbi %0\n\t" \ + : /* no output */ \ + : "m" (__m(__addr))); \ +} +#endif + +static inline unsigned long tas(volatile int *m) +{ + unsigned long retval; + + __asm__ __volatile__ ("tas.b @%1\n\t" + "movt %0" + : "=r" (retval): "r" (m): "t", "memory"); + return retval; +} + +/* + * A brief note on ctrl_barrier(), the control register write barrier. + * + * Legacy SH cores typically require a sequence of 8 nops after + * modification of a control register in order for the changes to take + * effect. On newer cores (like the sh4a and sh5) this is accomplished + * with icbi. + * + * Also note that on sh4a in the icbi case we can forego a synco for the + * write barrier, as it's not necessary for control registers. + * + * Historically we have only done this type of barrier for the MMUCR, but + * it's also necessary for the CCR, so we make it generic here instead. + */ +#ifdef CONFIG_CPU_SH4A +#define mb() __asm__ __volatile__ ("synco": : :"memory") +#define rmb() mb() +#define wmb() __asm__ __volatile__ ("synco": : :"memory") +#define ctrl_barrier() __icbi() +#define read_barrier_depends() do { } while(0) +#else +#define mb() __asm__ __volatile__ ("": : :"memory") +#define rmb() mb() +#define wmb() __asm__ __volatile__ ("": : :"memory") +#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") +#define read_barrier_depends() do { } while(0) +#endif + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define smp_read_barrier_depends() read_barrier_depends() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do { } while(0) +#endif + +#define set_mb(var, value) do { xchg(&var, value); } while (0) + +/* + * Jump to P2 area. + * When handling TLB or caches, we need to do it from P2 area. + */ +#define jump_to_P2() \ +do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "or %1, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy) \ + : "r" (0x20000000)); \ +} while (0) + +/* + * Back to P1 area. + */ +#define back_to_P1() \ +do { \ + unsigned long __dummy; \ + ctrl_barrier(); \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy)); \ +} while (0) + +static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) +{ + unsigned long flags, retval; + + local_irq_save(flags); + retval = *m; + *m = val; + local_irq_restore(flags); + return retval; +} + +static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) +{ + unsigned long flags, retval; + + local_irq_save(flags); + retval = *m; + *m = val & 0xff; + local_irq_restore(flags); + return retval; +} + +extern void __xchg_called_with_bad_pointer(void); + +#define __xchg(ptr, x, size) \ +({ \ + unsigned long __xchg__res; \ + volatile void *__xchg_ptr = (ptr); \ + switch (size) { \ + case 4: \ + __xchg__res = xchg_u32(__xchg_ptr, x); \ + break; \ + case 1: \ + __xchg__res = xchg_u8(__xchg_ptr, x); \ + break; \ + default: \ + __xchg_called_with_bad_pointer(); \ + __xchg__res = x; \ + break; \ + } \ + \ + __xchg__res; \ +}) + +#define xchg(ptr,x) \ + ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr)))) + +static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, + unsigned long new) +{ + __u32 retval; + unsigned long flags; + + local_irq_save(flags); + retval = *m; + if (retval == old) + *m = new; + local_irq_restore(flags); /* implies memory barrier */ + return retval; +} + +/* This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid cmpxchg(). */ +extern void __cmpxchg_called_with_bad_pointer(void); + +#define __HAVE_ARCH_CMPXCHG 1 + +static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, + unsigned long new, int size) +{ + switch (size) { + case 4: + return __cmpxchg_u32(ptr, old, new); + } + __cmpxchg_called_with_bad_pointer(); + return old; +} + +#define cmpxchg(ptr,o,n) \ + ({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, sizeof(*(ptr))); \ + }) + +extern void *set_exception_table_vec(unsigned int vec, void *handler); + +static inline void *set_exception_table_evt(unsigned int evt, void *handler) +{ + return set_exception_table_vec(evt >> 5, handler); +} + +/* XXX + * disable hlt during certain critical i/o operations + */ +#define HAVE_DISABLE_HLT +void disable_hlt(void); +void enable_hlt(void); + +#define arch_align_stack(x) (x) + +#endif diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h new file mode 100644 index 0000000000..fd00dbb82f --- /dev/null +++ b/include/asm-sh/types.h @@ -0,0 +1,59 @@ +#ifndef __ASM_SH_TYPES_H +#define __ASM_SH_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif /* __ASSEMBLY__ */ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#define BITS_PER_LONG 32 + +#ifndef __ASSEMBLY__ + + +typedef __signed__ char s8; +typedef unsigned char u8; + +typedef __signed__ short s16; +typedef unsigned short u16; + +typedef __signed__ int s32; +typedef unsigned int u32; + +typedef __signed__ long long s64; +typedef unsigned long long u64; + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_TYPES_H */ diff --git a/include/asm-sh/u-boot.h b/include/asm-sh/u-boot.h new file mode 100644 index 0000000000..b79644cfd2 --- /dev/null +++ b/include/asm-sh/u-boot.h @@ -0,0 +1,42 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __ASM_SH_U_BOOT_H_ +#define __ASM_SH_U_BOOT_H_ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_baudrate; /* Console Baudrate */ + unsigned long bi_boot_params; /* where this board expects params */ +} bd_t; + +#endif diff --git a/include/common.h b/include/common.h index edd00247eb..493417f877 100644 --- a/include/common.h +++ b/include/common.h @@ -129,20 +129,21 @@ typedef void (interrupt_handler_t)(void *); /* * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards + * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards + * and for the TQM885D board */ #if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \ - defined(CONFIG_TQM885D) + defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) # ifndef CONFIG_TQM8xxM # define CONFIG_TQM8xxM # endif #endif #if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) + defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \ + defined(CONFIG_TQM885D) # ifndef CONFIG_TQM8xxL # define CONFIG_TQM8xxL # endif @@ -497,6 +498,7 @@ ulong get_bus_freq (ulong); #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); +ulong get_ddr_freq (ulong); #endif #if defined(CONFIG_MPC86xx) typedef MPC86xx_SYS_INFO sys_info_t; diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h deleted file mode 100644 index eb47cd7ff8..0000000000 --- a/include/configs/CPCI440.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - * (C) Copyright 2002 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * board/config_CPCI440.h - configuration for esd CPCI-440 board - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_CPCI440 1 /* Board is ebony */ -#define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#if 1 -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#else -#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */ -#endif -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ - -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#if 1 /* test-only */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#undef CFG_FLASH_BASE -#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ - -#else /* test-only */ - -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#endif - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#if 0 /* test-only */ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ - -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) -#else - -#if 0 /* test-only */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ -#else -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#endif - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#if 0 /* test-only */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#endif - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#if 0 -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h index 02ae5d005d..f8b026212d 100644 --- a/include/configs/HMI10.h +++ b/include/configs/HMI10.h @@ -224,11 +224,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index be603ac117..35e1d63066 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -298,13 +298,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8540@0" -#define OF_SOC "soc8540@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 @@ -424,6 +420,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -441,6 +438,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 8dda6651ef..d2e7237895 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -309,14 +309,9 @@ extern unsigned long get_clock_freq(void); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8541@0" -#define OF_SOC "soc8541@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" -#define OF_PCI "pci@e0008000" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C @@ -422,6 +417,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -434,6 +430,7 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 13e2a2c079..545a76cc62 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -40,6 +40,7 @@ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -251,13 +252,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8544@0" -#define OF_SOC "soc8544@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ @@ -410,6 +407,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -426,6 +424,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -475,10 +474,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD #endif #define CONFIG_IPADDR 192.168.1.251 @@ -488,8 +483,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOOTFILE 8544ds/uImage.uboot #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ @@ -499,65 +494,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) -#define PCIE_ENV \ - "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ - "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ - "pcieerr=md ${a}020 1; md ${a}e00 e;" \ - "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1;" \ - "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ - "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \ - "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \ - "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ - "pci w $b.0 130 ffffffff\0" \ - "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ - "pcie1regs=setenv a e000a; run pciereg\0" \ - "pcie2regs=setenv a e0009; run pciereg\0" \ - "pcie3regs=setenv a e000b; run pciereg\0" \ - "pcie1cfg=setenv b 3; run pciecfg\0" \ - "pcie2cfg=setenv b 5; run pciecfg\0" \ - "pcie3cfg=setenv b 0; run pciecfg\0" \ - "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ - "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \ - "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \ - "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \ - "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \ - "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0" -#else -#define PCIE_ENV "" -#endif - -#if defined(CONFIG_PCI1) -#define PCI_ENV \ - "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ - "echo e;md ${a}e00 9\0" \ - "pci1regs=setenv a e0008; run pcireg\0" \ - "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1\0" \ - "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ - "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \ - "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \ - "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0" -#else -#define PCI_ENV "" -#endif - -#if defined(CONFIG_TSEC_ENET) -#define ENET_ENV \ - "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ - "md ${a}098 2\0" \ - "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ - "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ - "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ - "echo mib;md ${a}680 31\0" \ - "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ - "enet1regs=setenv a e0024; run enetreg\0" \ - "enet3regs=setenv a e0026; run enetreg\0" -#else -#define ENET_ENV "" -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -570,29 +506,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8544ds/ramdisk.uboot\0" \ - "dtbaddr=c00000\0" \ - "dtbfile=8544ds/mpc8544ds.dtb\0" \ - "bdev=sda3\0" \ - "eoi=mw e00400b0 0\0" \ - "iack=md e00400a0 1\0" \ - "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ - "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ - "ddrregs=setenv a e0002; run ddrreg\0" \ - "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ - "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ - "guregs=setenv a e00e0; run gureg\0" \ - "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ - "ecmregs=setenv a e0001; run ecmreg\0" \ - "lawregs=md e0000c08 4b\0" \ - "lbcregs=md e0005000 36\0" \ - "dma0regs=md e0021100 12\0" \ - "dma1regs=md e0021180 12\0" \ - "dma2regs=md e0021200 12\0" \ - "dma3regs=md e0021280 12\0" \ - PCIE_ENV \ - PCI_ENV \ - ENET_ENV - + "fdtaddr=c00000\0" \ + "fdtfile=8544ds/mpc8544ds.dtb\0" \ + "bdev=sda3\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -600,23 +516,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" - + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4edc7fd2b6..3f382e59a6 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -42,6 +42,7 @@ #undef CONFIG_RIO #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -333,14 +334,9 @@ extern unsigned long get_clock_freq(void); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8548@0" -#define OF_SOC "soc8548@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" -#define OF_PCI "pci@e0008000" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C @@ -483,6 +479,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -495,6 +492,7 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -568,72 +566,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_PCIE1) -#define PCIE_ENV \ - "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ - "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ - "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ - "pci d $b.0 130 1\0" \ - "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \ - "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\ - "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ - "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ - "pcie1regs=setenv a e000a; run pciereg\0" \ - "pcie1cfg=setenv b 3; run pciecfg\0" \ - "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ - "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" -#else -#define PCIE_ENV "" -#endif - -#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) -#define PCI_ENV \ - "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ - "echo e;md ${a}e00 9\0" \ - "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1\0" \ - "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ - "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" -#else -#define PCI_ENV "" -#endif - -#if defined(CONFIG_PCI1) -#define PCI_ENV1 \ - "pci1regs=setenv a e0008; run pcireg\0" \ - "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \ - "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0" -#else -#define PCI_ENV1 "" -#endif - -#if defined(CONFIG_PCI2) -#define PCI_ENV2 \ - "pci2regs=setenv a e0009; run pcireg\0" \ - "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \ - "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0" -#else -#define PCI_ENV2 "" -#endif - -#if defined(CONFIG_TSEC_ENET) -#define ENET_ENV \ - "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ - "md ${a}098 2\0" \ - "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ - "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ - "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ - "echo mib;md ${a}680 31\0" \ - "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ - "enet1regs=setenv a e0024; run enetreg\0" \ - "enet2regs=setenv a e0025; run enetreg\0" \ - "enet3regs=setenv a e0026; run enetreg\0" \ - "enet4regs=setenv a e0027; run enetreg\0" -#else -#define ENET_ENV "" -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -647,28 +579,7 @@ extern unsigned long get_clock_freq(void); "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ - "fdtfile=mpc8548cds.dtb\0" \ - "eoi=mw e00400b0 0\0" \ - "iack=md e00400a0 1\0" \ - "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ - "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ - "ddrregs=setenv a e0002; run ddrreg\0" \ - "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ - "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ - "guregs=setenv a e00e0; run gureg\0" \ - "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ - "ecmregs=setenv a e0001; run ecmreg\0" \ - "lawregs=md e0000c08 4b\0" \ - "lbcregs=md e0005000 36\0" \ - "dma0regs=md e0021100 12\0" \ - "dma1regs=md e0021180 12\0" \ - "dma2regs=md e0021200 12\0" \ - "dma3regs=md e0021280 12\0" \ - PCIE_ENV \ - PCI_ENV \ - PCI_ENV1 \ - PCI_ENV2 \ - ENET_ENV + "fdtfile=mpc8548cds.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index c414bf033e..90ef3d6b67 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -309,14 +309,9 @@ extern unsigned long get_clock_freq(void); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8555@0" -#define OF_SOC "soc8555@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" -#define OF_PCI "pci@e0008000" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C @@ -422,6 +417,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -434,6 +430,7 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index a8f362fa13..d4e0de0d32 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -289,13 +289,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8560@0" -#define OF_SOC "soc8560@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C @@ -450,6 +446,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -471,6 +468,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x1000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ @@ -525,6 +523,8 @@ #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index b9366cc994..59f490e856 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -33,7 +33,11 @@ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ -#define CONFIG_PCI +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCI controller */ +#define CONFIG_PCIE1 1 /* PCIE controller */ +#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE @@ -87,6 +91,9 @@ extern unsigned long get_clock_freq(void); #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + /* * DDR Setup */ @@ -290,14 +297,9 @@ extern unsigned long get_clock_freq(void); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8568@0" -#define OF_SOC "soc8568@e0000000" -#define OF_QE "qe@e0080000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C @@ -325,12 +327,12 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ -#define CFG_PEX_MEM_BASE 0xa0000000 -#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE -#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PEX_IO_BASE 0x00000000 -#define CFG_PEX_IO_PHYS 0xe2800000 -#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */ +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe2800000 +#define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */ #define CFG_SRIO_MEM_BASE 0xc0000000 @@ -383,6 +385,11 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + #endif /* CONFIG_PCI */ #ifndef CONFIG_NET_MULTI @@ -440,6 +447,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -452,6 +460,7 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 6b16654042..0bd77c07b6 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -288,6 +288,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ +#define CFG_EEPROM_WREN 1 /* CAT24WC08/16... */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ @@ -379,15 +380,16 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRH 0x00000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 #define CFG_GPIO0_ISR1L 0x15555445 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0014 +#define CFG_GPIO0_TCR 0x77FE0014 #define CFG_DUART_RST (0x80000000 >> 14) +#define CFG_EEPROM_WP (0x80000000 >> 0) /* * Internal Definitions diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h new file mode 100644 index 0000000000..3d2ed1e7d6 --- /dev/null +++ b/include/configs/PMC440.h @@ -0,0 +1,522 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. + * Based on the sequoia configuration file. + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * PMC440.h - configuration for esd PMC440 boards + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ + +#define CONFIG_SYS_CLK_FREQ 33333400 + +#define CONFIG_4xx_DCACHE /* enable dcache */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */ + +#define CONFIG_PRAM 0 /* use pram variable to overwrite */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 +#define CFG_PCI_MEMSIZE 0x80000000 /* 2GB! */ + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 +#define CFG_FPGA_BASE0 0xef000000 /* 32 bit */ +#define CFG_FPGA_BASE1 0xef100000 /* 16 bit */ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +#undef CONFIG_UART1_CONSOLE /* console on front panel */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#endif + +/*----------------------------------------------------------------------- + * RTC + *----------------------------------------------------------------------*/ +#define CONFIG_RTC_RX8025 + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ +#endif + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ +#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ + +#define CFG_NAND_ECCSIZE 256 +#define CFG_NAND_ECCBYTES 3 +#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) +#define CFG_NAND_OOBSIZE 16 +#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) +#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} + +#ifdef CFG_ENV_IS_IN_NAND +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/sequoia/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#endif + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_I2C_CMD_TREE 1 +#define CONFIG_I2C_MULTI_BUS 1 + +#define CFG_I2C_MULTI_EEPROMS + +#define CFG_I2C_EEPROM_ADDR 0x54 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 + +#define CFG_EEPROM_WREN 1 +#define CFG_I2C_BOOT_EEPROM_ADDR 0x52 + +/* + * standard dtt sensor configuration - bottom bit will determine local or + * remote sensor of the TMP401 + */ +#define CONFIG_DTT_SENSORS { 0, 1 } + +/* + * The PMC440 uses a TI TMP401 temperature sensor. This part + * is basically compatible to the ADM1021 that is supported + * by U-Boot. + * + * - i2c addr 0x4c + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT ouput disabled + * - local temp sensor enabled, min set to 0 deg, max set to 70 deg + * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg + */ +#define CONFIG_DTT_ADM1021 +#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME pmc440 +#define CFG_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk_410/ppc_4xx\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + CFG_ROOTPATH \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 200000 FFFA0000 60000\0" \ + "" + +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#define CFG_OHCI_BE_CONTROLLER + +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST +#define CFG_USB_OHCI_SLOT_NAME "ppc440" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#include <config_cmd_default.h> + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +/* POST support */ +/* ethernet POST sometimes freezes the CPU. + * So disable it for now until issue is solved + */ +#if 0 +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_ETHER | \ + CFG_POST_SPR) +#else +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_SPR) +#endif + +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) + +/* esd expects pram at end of physical memory. + * So no logbuffer at the moment. + */ +#if 0 +#define CONFIG_LOGBUFFER +#endif +#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#define CONFIG_SUPPORT_VFAT + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_STOP_STR " " + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +/* PCI identification */ +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */ +#define CFG_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */ +#define CFG_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC +#define CFG_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FPGA stuff + *----------------------------------------------------------------------*/ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN2 +#define CONFIG_FPGA_SPARTAN3 + +#define CONFIG_FPGA_COUNT 2 +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ + +/* + * On Sequoia CS0 and CS3 are switched when configuring for NAND booting + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_NAND_CS 2 /* NAND chip connected to CSx */ + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03017200 +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) + +/* Memory Bank 2 (NAND-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x018003c0 +#define CFG_EBC_PB2CR (CFG_NAND_ADDR | 0x1c000) +#else +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +/* Memory Bank 2 (NOR-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x03017200 +#define CFG_EBC_PB2CR (CFG_FLASH_BASE | 0xda000) + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) +#endif + +/* Memory Bank 4 (FPGA / 32Bit) initialization */ +#define CFG_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */ +#define CFG_EBC_PB4CR (CFG_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */ + +/* Memory Bank 5 (FPGA / 16Bit) initialization */ +#define CFG_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */ +#define CFG_EBC_PB5CR (CFG_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 1c6a9ae4f1..ae8d9abac1 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -335,7 +335,7 @@ #else #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ #endif /* CONFIG_TQM5200_B */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* @@ -392,6 +392,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 7a3801026f..be5b4d3f58 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -192,11 +192,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index e8b6a80b19..a0c01b65a1 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -188,15 +188,19 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index beeca6343e..f51b12e303 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -179,11 +179,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index d5609c1d48..a725e71ca2 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -177,15 +177,19 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index e35b5b2ac1..16dc3ebe92 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -183,11 +183,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index cd5212eff8..c4b459952a 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -217,15 +217,19 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index d5838dbf37..ac22c1e8b4 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -186,11 +186,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index fe3a2f020c..8601de1722 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -189,11 +189,14 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ @@ -368,7 +371,7 @@ */ #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ +#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ #define CFG_OR_TIMING_SDRAM 0x00000A00 @@ -444,7 +447,10 @@ #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* * Internal Definitions diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index f09d3d1654..2bf4a2a357 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -186,14 +186,17 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 039aa3af42..d42ffc9da2 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -186,16 +186,19 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index ca3c166524..d7e5eebae7 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -232,11 +232,14 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index f36b729cd5..8a3aa4bc4b 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -42,17 +42,10 @@ #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ #define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ #define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */ +#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ /* (it will be used if there is no */ /* 'cpuclk' variable with valid value) */ -#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CFG_MEASURE_CPUCLK -#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ @@ -83,9 +76,15 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM866M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "bootfile=/tftpboot/TQM885D/uImage\0" \ + "fdt_addr=400C0000\0" \ + "kernel_addr=40100000\0" \ + "ramdisk_addr=40280000\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=protect off 40000000 +${filesize};" \ + "erase 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "protect on 40000000 +${filesize}\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -144,7 +143,7 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ +#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ #define CONFIG_TIMESTAMP /* but print image timestmps */ @@ -230,7 +229,7 @@ #define CFG_FLASH_BASE 0x40000000 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -242,16 +241,20 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) @@ -434,26 +437,30 @@ #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) /* - * Memory Periodic Timer Prescaler - * Periodic timer for refresh, start with refresh rate for 40 MHz clock - * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) + * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) + * + * CPUclock(MHz) * 31.2 + * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 + * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 + * + * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us + * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us + * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us + * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us + * + * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will + * be met also in the default configuration, i.e. if environment variable + * 'cpuclk' is not set. */ -#define CFG_MAMR_PTA 39 +#define CFG_MAMR_PTA 128 /* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + * Memory Periodic Timer Prescaler Register (MPTPR) values. */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 +/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* * MAMR settings for SDRAM diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3a413f555d..3ca928ec93 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -52,9 +52,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -204,8 +208,6 @@ #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ -#define CONFIG_ATAPI 1 /* ATAPI for Travelstar */ - #define CFG_ATA_BASE_ADDR 0xF0100000 #define CFG_ATA_IDE0_OFFSET 0x0000 #define CFG_ATA_IDE1_OFFSET 0x0010 @@ -244,11 +246,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -281,19 +278,12 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#if 0 /* test-only */ -/* CAT24WC08/16... */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#else +#define CFG_EEPROM_WREN 1 + /* CAT24WC32/64... */ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ @@ -301,7 +291,6 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ /* 32 byte page write mode using*/ /* last 5 bits of the address */ -#endif #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE @@ -400,18 +389,20 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO */ -#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRH 0x00000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 #define CFG_GPIO0_ISR1L 0x15555440 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0017 +#define CFG_GPIO0_TCR 0x777E0017 #define CFG_DUART_RST (0x80000000 >> 14) #define CFG_LCD_ENDIAN (0x80000000 >> 7) +#define CFG_IIC_ON (0x80000000 >> 8) #define CFG_LCD0_RST (0x80000000 >> 30) #define CFG_LCD1_RST (0x80000000 >> 31) +#define CFG_EEPROM_WP (0x80000000 >> 0) /* * Internal Definitions diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h new file mode 100644 index 0000000000..194788b18d --- /dev/null +++ b/include/configs/atstk1003.h @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * Configuration settings for the ATSTK1003 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7001 1 +#define CONFIG_ATSTK1003 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mmcblk0p1 rootwait" + +#define CONFIG_BOOTCOMMAND \ + "mmcinit; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_PIO2 1 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h new file mode 100644 index 0000000000..1bad171cbf --- /dev/null +++ b/include/configs/atstk1004.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * Configuration settings for the ATSTK1003 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7002 1 +#define CONFIG_ATSTK1004 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mmcblk0p1 rootwait" + +#define CONFIG_BOOTCOMMAND \ + "mmcinit; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_PIO2 1 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 +#define CFG_SDRAM_16BIT 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 2eed9413f6..0aa4f2dcc0 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -193,8 +193,14 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty;" \ + "bootm 200000 - ${fdt_addr}\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=katmai/uImage\0" \ + "fdt_file=katmai/katmai.dtb\0" \ + "fdt_addr=400000\0" \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ "initrd_high=30000000\0" \ @@ -445,4 +451,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index bec9fde73a..f3e8601d85 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -519,6 +519,5 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "cpu@0" #endif /* __CONFIG_H */ diff --git a/include/configs/korat.h b/include/configs/korat.h new file mode 100644 index 0000000000..1ea7d4894a --- /dev/null +++ b/include/configs/korat.h @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * korat.h - configuration for Korat board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Manufacturer's information serial EEPROM parameters + *----------------------------------------------------------------------*/ +#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */ +#define MAN_SERIAL_NO_FIELD 2 +#define MAN_SERIAL_NO_LENGTH 13 +#define MAN_MAC_ADDR_FIELD 3 +#define MAN_MAC_ADDR_LENGTH 17 + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 +#define CFG_CPLD_BASE 0xc0000000 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */ +#undef CFG_INIT_RAM_DCACHE +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */ +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ +#define CONFIG_DDR_ECC /* Use ECC when available */ +#define SPD_EEPROM_ADDRESS {0x50} +#define CONFIG_PROG_SDRAM_TLB +#define CFG_DRAM_TEST + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C RTC */ +#define CONFIG_RTC_M41T60 1 +#define CFG_I2C_RTC_ADDR 0x68 + +/* I2C SYSMON (LM73) */ +#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */ +#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_MIN_TEMP -30 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME korat +#define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + CFG_ROOTPATH \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 200000 FFFA0000 60000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 3 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_I2C_CMD_TREE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_USB + +/* POST support */ +#define CONFIG_POST (CFG_POST_CACHE | \ + CFG_POST_CPU | \ + CFG_POST_ECC | \ + CFG_POST_ETHER | \ + CFG_POST_FPU | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_RTC | \ + CFG_POST_SPR | \ + CFG_POST_UART) + +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#define CONFIG_SUPPORT_VFAT + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x04017300 +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0x000DA000) + +/* Memory Bank 1 (NOR-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x04017300 +#define CFG_EBC_PB1CR (0xF8000000 | 0x000DA000) + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x04017300 +#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 9cb483d3ca..5210024d8f 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -153,7 +153,7 @@ CFG_POST_SPR | \ CFG_POST_UART) -#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_LOGBUFFER #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 2871a6cac1..8f8e867b83 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -394,6 +394,4 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,405EX@0" - #endif /* __CONFIG_H */ diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h new file mode 100644 index 0000000000..ae0d018515 --- /dev/null +++ b/include/configs/ms7722se.h @@ -0,0 +1,136 @@ +/* + * Configuation settings for the Hitachi Solution Engine 7722 + * + * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MS7722SE_H +#define __MS7722SE_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_CPU_SH7722 1 +#define CONFIG_MS7722SE 1 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_ENV + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.22 +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_GATEWAYIP 192.168.0.1 + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* SMC9111 */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE (0xB8000000) + +/* MEMORY */ +#define MS7722SE_SDRAM_BASE (0x8C000000) +#define MS7722SE_FLASH_BASE_1 (0xA0000000) +#define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ +#define CFG_PBSIZE 256 /* Buffer size for Console output */ +#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ +#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ +#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ + +/* SCIF */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF0 1 +#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */ +#undef CFG_CONSOLE_OVERWRITE_ROUTINE +#undef CFG_CONSOLE_ENV_OVERWRITE + +#define CFG_MEMTEST_START (MS7722SE_SDRAM_BASE) +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) + +#undef CFG_ALT_MEMTEST /* Enable alternate, more extensive, memory test */ +#undef CFG_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */ + +#undef CFG_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */ + +#define CFG_SDRAM_BASE (MS7722SE_SDRAM_BASE) +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */ + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ + +#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image + in Flash (NOT run time address in SDRAM) ?!? */ +#define CFG_MONITOR_LEN (128 * 1024) /* */ +#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ +#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ + +#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each + Flash chip */ + +/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ +#define CFG_MAX_FLASH_BANKS 2 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \ + CFG_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \ + } + +#define CFG_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */ +#define CFG_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */ +#define CFG_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */ + +#undef CFG_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */ + +#undef CFG_DIRECT_FLASH_TFTP + +#define CFG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_ENV_SECT_SIZE (8 * 1024) +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE)) +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) /* Offset of env Flash sector relative to CFG_FLASH_BASE */ +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE)) + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 33333333 +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +#endif /* __MS7722SE_H */ diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h new file mode 100644 index 0000000000..36681568f8 --- /dev/null +++ b/include/configs/ms7750se.h @@ -0,0 +1,108 @@ +/* + * Configuation settings for the Hitachi Solution Engine 7750 + * + * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MS7750SE_H +#define __MS7750SE_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_CPU_SH7750 1 +/* #define CONFIG_CPU_SH7751 1 */ +/* #define CONFIG_CPU_TYPE_R 1 */ +#define CONFIG_MS7750SE 1 +#define __LITTLE_ENDIAN__ 1 + +/* + * Command line configuration. + */ +/*#include <config_cmd_default.h>*/ + +#define CONFIG_CMD_DFL +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_ENV + +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_SCIF1 1 +#define BOARD_LATE_INIT 1 + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "console=ttySC0,38400" +#define CONFIG_ENV_OVERWRITE 1 + +/* SDRAM */ +#define CFG_SDRAM_BASE (0x8C000000) +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) + +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 +#define CFG_PBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } + +#define CFG_MEMTEST_START (CFG_SDRAM_BASE) +#define CFG_MEMTEST_END (TEXT_BASE - 0x100000) + +/* NOR Flash */ +/* #define CFG_FLASH_BASE (0xA1000000)*/ +#define CFG_FLASH_BASE (0xA0000000) +#define CFG_MAX_FLASH_BANKS (1) /* Max number of + * Flash memory banks + */ +#define CFG_MAX_FLASH_SECT 142 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) +#define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */ +#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ + +#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_RX_ETH_BUFFER (8) + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_CFI_BROKEN_TABLE +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + + +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_WRITE_TOUT 500 + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 33333333 +#define TMU_CLK_DIVIDER 4 +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +#endif /* __MS7750SE_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 58acbc090e..1f72b54884 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -329,6 +329,7 @@ #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK /* @@ -376,7 +377,7 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CONFIG_LOGBUFFER -#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ @@ -491,6 +492,5 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "cpu@0" #endif /* __CONFIG_H */ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index edae6f4b98..827a28f077 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -193,11 +193,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/dtt.h b/include/dtt.h index 2e8c690158..4e8aaad87f 100644 --- a/include/dtt.h +++ b/include/dtt.h @@ -31,7 +31,8 @@ defined(CONFIG_DTT_DS1621) || \ defined(CONFIG_DTT_DS1775) || \ defined(CONFIG_DTT_LM81) || \ - defined(CONFIG_DTT_ADM1021) + defined(CONFIG_DTT_ADM1021) || \ + defined(CONFIG_DTT_LM73) #define CONFIG_DTT /* We have a DTT */ @@ -119,4 +120,13 @@ extern int dtt_get_temp(int sensor); #define DTT_ADM1021_DEVID 0x41 #endif +#if defined(CONFIG_DTT_LM73) +#define DTT_READ_TEMP 0x0 +#define DTT_CONFIG 0x1 +#define DTT_TEMP_HIGH 0x2 +#define DTT_TEMP_LOW 0x3 +#define DTT_CONTROL 0x4 +#define DTT_ID 0x7 +#endif + #endif /* _DTT_H_ */ diff --git a/include/e500.h b/include/e500.h index 8e3bf8cb7d..0d73260f40 100644 --- a/include/e500.h +++ b/include/e500.h @@ -12,6 +12,7 @@ typedef struct { unsigned long freqProcessor; unsigned long freqSystemBus; + unsigned long freqDDRBus; } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ diff --git a/include/flash.h b/include/flash.h index b0bf733f18..2ed1e20fd2 100644 --- a/include/flash.h +++ b/include/flash.h @@ -52,6 +52,9 @@ typedef struct { ushort ext_addr; /* extended query table address */ ushort cfi_version; /* cfi version */ ushort cfi_offset; /* offset for cfi query */ + ulong addr_unlock1; /* unlock address 1 for AMD flash roms */ + ulong addr_unlock2; /* unlock address 2 for AMD flash roms */ + const char *name; /* human-readable name */ #endif } flash_info_t; @@ -77,6 +80,7 @@ typedef struct { #define FLASH_CFI_X8 0x00 #define FLASH_CFI_X16 0x01 #define FLASH_CFI_X8X16 0x02 +#define FLASH_CFI_X16X32 0x05 /* convert between bit value and numeric value */ #define CFI_FLASH_SHIFT_WIDTH 3 @@ -101,6 +105,13 @@ extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offse extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len); #endif /* CFG_FLASH_PROTECTION */ +#ifdef CONFIG_FLASH_CFI_LEGACY +extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info); +extern int jedec_flash_match(flash_info_t *info, ulong base); +#define CFI_CMDSET_AMD_LEGACY 0xFFF0 +#endif + + /*----------------------------------------------------------------------- * return codes from flash_write(): */ diff --git a/include/ioports.h b/include/ioports.h index cfba667cab..1134ea5208 100644 --- a/include/ioports.h +++ b/include/ioports.h @@ -26,7 +26,7 @@ typedef struct { * a 0x20 byte boundary */ #ifdef CONFIG_MPC85xx -#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20)) +#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) #else #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) #endif diff --git a/include/ppc440.h b/include/ppc440.h index 21e8836694..90e56b0989 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -19,6 +19,30 @@ | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +----------------------------------------------------------------------------*/ +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef __PPC440_H__ #define __PPC440_H__ @@ -186,54 +210,6 @@ #define sdr_plbtr 0x4200 #define sdr_mfr 0x4300 /* SDR0_MFR reg */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */ -#define DDR0_00 0x00 -#define DDR0_01 0x01 -#define DDR0_02 0x02 -#define DDR0_03 0x03 -#define DDR0_04 0x04 -#define DDR0_05 0x05 -#define DDR0_06 0x06 -#define DDR0_07 0x07 -#define DDR0_08 0x08 -#define DDR0_09 0x09 -#define DDR0_10 0x0A -#define DDR0_11 0x0B -#define DDR0_12 0x0C -#define DDR0_13 0x0D -#define DDR0_14 0x0E -#define DDR0_15 0x0F -#define DDR0_16 0x10 -#define DDR0_17 0x11 -#define DDR0_18 0x12 -#define DDR0_19 0x13 -#define DDR0_20 0x14 -#define DDR0_21 0x15 -#define DDR0_22 0x16 -#define DDR0_23 0x17 -#define DDR0_24 0x18 -#define DDR0_25 0x19 -#define DDR0_26 0x1A -#define DDR0_27 0x1B -#define DDR0_28 0x1C -#define DDR0_29 0x1D -#define DDR0_30 0x1E -#define DDR0_31 0x1F -#define DDR0_32 0x20 -#define DDR0_33 0x21 -#define DDR0_34 0x22 -#define DDR0_35 0x23 -#define DDR0_36 0x24 -#define DDR0_37 0x25 -#define DDR0_38 0x26 -#define DDR0_39 0x27 -#define DDR0_40 0x28 -#define DDR0_41 0x29 -#define DDR0_42 0x2A -#define DDR0_43 0x2B -#define DDR0_44 0x2C -#endif /*CONFIG_440EPX*/ - /*----------------------------------------------------------------------------- | SDRAM Controller +----------------------------------------------------------------------------*/ @@ -817,6 +793,448 @@ #define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ #endif /* CONFIG_440SPE */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +/*----------------------------------------------------------------------------- + | SDRAM Controller + +----------------------------------------------------------------------------*/ +#define DDR0_00 0x00 +#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +/* Status */ +#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ +/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT0 0x00010000 +/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT1 0x00020000 +/* Bit2. Single correctable ECC event detected */ +#define DDR0_00_INT_STATUS_BIT2 0x00040000 +/* Bit3. Multiple correctable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT3 0x00080000 +/* Bit4. Single uncorrectable ECC event detected. */ +#define DDR0_00_INT_STATUS_BIT4 0x00100000 +/* Bit5. Multiple uncorrectable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT5 0x00200000 +/* Bit6. DRAM initialization complete. */ +#define DDR0_00_INT_STATUS_BIT6 0x00400000 +/* Bit7. Logical OR of all lower bits. */ +#define DDR0_00_INT_STATUS_BIT7 0x00800000 + +#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 +#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_00_DLL_START_POINT_MASK 0x0000007F +#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_01 0x01 +#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 +#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 +#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ +#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_02 0x02 +#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ +#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) +#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) +#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ +#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ +#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_02_START_MASK 0x00000001 +#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) +#define DDR0_02_START_OFF 0x00000000 +#define DDR0_02_START_ON 0x00000001 + +#define DDR0_03 0x03 +#define DDR0_03_BSTLEN_MASK 0x07000000 +#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_03_CASLAT_MASK 0x00070000 +#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 +#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_03_INITAREF_MASK 0x0000000F +#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_04 0x04 +#define DDR0_04_TRC_MASK 0x1F000000 +#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_04_TRRD_MASK 0x00070000 +#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_04_TRTP_MASK 0x00000700 +#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) + +#define DDR0_05 0x05 +#define DDR0_05_TMRD_MASK 0x1F000000 +#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_05_TEMRS_MASK 0x00070000 +#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_05_TRP_MASK 0x00000F00 +#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_05_TRAS_MIN_MASK 0x000000FF +#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#define DDR0_06 0x06 +#define DDR0_06_WRITEINTERP_MASK 0x01000000 +#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_06_TWTR_MASK 0x00070000 +#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_06_TDLL_MASK 0x0000FF00 +#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_06_TRFC_MASK 0x0000007F +#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_07 0x07 +#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 +#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_07_TFAW_MASK 0x001F0000 +#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 +#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_07_AREFRESH_MASK 0x00000001 +#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_08 0x08 +#define DDR0_08_WRLAT_MASK 0x07000000 +#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_08_TCPD_MASK 0x00FF0000 +#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_08_DQS_N_EN_MASK 0x00000100 +#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 +#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_09 0x09 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_09_RTT_0_MASK 0x00030000 +#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 +#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F +#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_10 0x0A +#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ +#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_10_CS_MAP_MASK 0x00000300 +#define DDR0_10_CS_MAP_NO_MEM 0x00000000 +#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 +#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 +#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F +#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) + +#define DDR0_11 0x0B +#define DDR0_11_SREFRESH_MASK 0x01000000 +#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_11_TXSNR_MASK 0x00FF0000 +#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_11_TXSR_MASK 0x0000FF00 +#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) + +#define DDR0_12 0x0C +#define DDR0_12_TCKE_MASK 0x0000007 +#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) + +#define DDR0_14 0x0E +#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 +#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_14_REDUC_MASK 0x00010000 +#define DDR0_14_REDUC_64BITS 0x00000000 +#define DDR0_14_REDUC_32BITS 0x00010000 +#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 +#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) + +#define DDR0_17 0x11 +#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 +#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ +#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) + +#define DDR0_18 0x12 +#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 +#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 +#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 +#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F +#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_19 0x13 +#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 +#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 +#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 +#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F +#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_20 0x14 +#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 +#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 +#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 +#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F +#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_21 0x15 +#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 +#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 +#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 +#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F +#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_22 0x16 +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct */ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ +#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 +#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F +#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_23 0x17 +#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 +#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ +#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ +#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ +#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_24 0x18 +#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 +#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 +#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 +#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 +#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) +#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) + +#define DDR0_25 0x19 +#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ +#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ +#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_26 0x1A +#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 +#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_26_TREF_MASK 0x00003FFF +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) + +#define DDR0_27 0x1B +#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 +#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_27_TINIT_MASK 0x0000FFFF +#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_28 0x1C +#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 +#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF +#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) + +#define DDR0_31 0x1F +#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF +#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_32 0x20 +#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_33 0x21 +#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_34 0x22 +#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_35 0x23 +#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_36 0x24 +#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_37 0x25 +#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_38 0x26 +#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_39 0x27 +#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_40 0x28 +#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_41 0x29 +#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_42 0x2A +#define DDR0_42_ADDR_PINS_MASK 0x07000000 +#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F +#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_43 0x2B +#define DDR0_43_TWR_MASK 0x07000000 +#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_43_APREBIT_MASK 0x000F0000 +#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 +#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 +#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_44 0x2C +#define DDR0_44_TRCD_MASK 0x000000FF +#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#endif /* CONFIG_440EPX */ + /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 11d864feac..809ee3be92 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -311,6 +311,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) dma_alloc_init(); board_init_info(); + enable_interrupts(); + bd->bi_flashstart = 0; bd->bi_flashsize = 0; bd->bi_flashoffset = 0; diff --git a/lib_avr32/interrupts.c b/lib_avr32/interrupts.c index ce538f3d92..28df20db01 100644 --- a/lib_avr32/interrupts.c +++ b/lib_avr32/interrupts.c @@ -35,5 +35,5 @@ int disable_interrupts(void) sr = sysreg_read(SR); asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET)); - return SYSREG_BFEXT(GM, sr); + return !SYSREG_BFEXT(GM, sr); } diff --git a/lib_sh/Makefile b/lib_sh/Makefile new file mode 100644 index 0000000000..cf127a826c --- /dev/null +++ b/lib_sh/Makefile @@ -0,0 +1,42 @@ +# +# Copyright (c) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(ARCH).a + +SOBJS = + +COBJS = board.o sh_linux.o # time.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/lib_sh/board.c b/lib_sh/board.c new file mode 100644 index 0000000000..2cd60d76be --- /dev/null +++ b/lib_sh/board.c @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <devices.h> +#include <version.h> +#include <net.h> +#include <environment.h> + +extern void malloc_bin_reloc (void); +extern int cpu_init(void); +extern int board_init(void); +extern int dram_init(void); +extern int watchdog_init(void); +extern int timer_init(void); + +const char version_string[] = U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; + +unsigned long monitor_flash_len = CFG_MONITOR_LEN; + +static unsigned long mem_malloc_start; +static unsigned long mem_malloc_end; +static unsigned long mem_malloc_brk; + +static void mem_malloc_init (void) +{ + + mem_malloc_start = (TEXT_BASE - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN); + mem_malloc_end = (mem_malloc_start + CFG_MALLOC_LEN - 16); + mem_malloc_brk = mem_malloc_start; + memset ((void *) mem_malloc_start, 0, + (mem_malloc_end - mem_malloc_start)); +} + +void *sbrk (ptrdiff_t increment) +{ + unsigned long old = mem_malloc_brk; + unsigned long new = old + increment; + + if ((new < mem_malloc_start) || + (new > mem_malloc_end)) { + return NULL; + } + + mem_malloc_brk = new; + return (void *) old; +} + +static int sh_flash_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_flashsize = flash_init(); + printf("FLASH: %dMB\n", gd->bd->bi_flashsize / (1024*1024)); + + return 0; +} + +#if defined(CONFIG_CMD_NAND) +void nand_init (void); +static int sh_nand_init(void) +{ + printf("NAND: "); + nand_init(); /* go init the NAND */ + return 0; +} +#endif /* CONFIG_CMD_NAND */ + +#if defined(CONFIG_CMD_IDE) +#include <ide.h> +static int sh_marubun_init(void) +{ + puts ("IDE: "); + ide_init(); + return 0; +} +#endif /* (CONFIG_CMD_IDE) */ + +static int sh_mem_env_init(void) +{ + mem_malloc_init(); + malloc_bin_reloc(); + env_relocate(); + jumptable_init(); + return 0; +} + +static int sh_net_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + char *s, *e; + int i; + + gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); + s = getenv("ethaddr"); + for (i = 0; i < 6; ++i) { + gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) s = (*e) ? e + 1 : e; + } + + return 0; +} + +typedef int (init_fnc_t) (void); + +init_fnc_t *init_sequence[] = +{ + cpu_init, /* basic cpu dependent setup */ + board_init, /* basic board dependent setup */ + interrupt_init, /* set up exceptions */ + env_init, /* event init */ + serial_init, /* SCIF init */ + watchdog_init, /* watchdog init */ + console_init_f, + display_options, + checkcpu, + checkboard, /* Check support board */ + dram_init, /* SDRAM init */ + timer_init, /* SuperH Timer (TCNT0 only) init */ + sh_flash_init, /* Flash memory(NOR) init*/ + sh_mem_env_init, +#if defined(CONFIG_CMD_NAND) + sh_nand_init, /* Flash memory (NAND) init */ +#endif + devices_init, + console_init_r, + interrupt_init, +#ifdef BOARD_LATE_INIT + board_late_init, +#endif +#if defined(CONFIG_CMD_NET) + sh_net_init, /* SH specific eth init */ +#endif + NULL /* Terminate this list */ +}; + +void sh_generic_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd; + init_fnc_t **init_fnc_ptr; + char *s; + int i; + + memset (gd, 0, CFG_GBL_DATA_SIZE); + + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + + gd->bd = (bd_t *) (gd + 1); /* At end of global data */ + gd->baudrate = CONFIG_BAUDRATE; + + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + + bd = gd->bd; + bd->bi_memstart = CFG_SDRAM_BASE; + bd->bi_memsize = CFG_SDRAM_SIZE; + bd->bi_flashstart = CFG_FLASH_BASE; +#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE) + bd->bi_sramstart= CFG_SRAM_BASE; + bd->bi_sramsize = CFG_SRAM_SIZE; +#endif + bd->bi_baudrate = CONFIG_BAUDRATE; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr , i++) { + if ((*init_fnc_ptr) () != 0) { + hang(); + } + } + +#if defined(CONFIG_CMD_NET) + puts ("Net: "); + eth_initialize(gd->bd); + + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CONFIG_CMD_NET */ + + while (1) { + main_loop(); + } +} + +/***********************************************************************/ + +void hang (void) +{ + puts ("Board ERROR\n"); + for (;;); +} diff --git a/lib_sh/sh_linux.c b/lib_sh/sh_linux.c new file mode 100644 index 0000000000..14b6815cd4 --- /dev/null +++ b/lib_sh/sh_linux.c @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <command.h> +#include <asm/byteorder.h> + +extern image_header_t header; /* common/cmd_bootm.c */ + +/* The SH kernel reads arguments from the empty zero page at location + * 0 at the start of SDRAM. The following are copied from + * arch/sh/kernel/setup.c and may require tweaking if the kernel sources + * change. + */ +#define PARAM ((unsigned char *)CFG_SDRAM_BASE + 0x1000) + +#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000)) +#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004)) +#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008)) +#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c)) +#define INITRD_START (*(unsigned long *) (PARAM+0x010)) +#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014)) +/* ... */ +#define COMMAND_LINE ((char *) (PARAM+0x100)) + +#define RAMDISK_IMAGE_START_MASK 0x07FF + +#ifdef CFG_DEBUG +static void hexdump (unsigned char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + if ((i % 16) == 0) + printf ("%s%08x: ", i ? "\n" : "", (unsigned int) &buf[i]); + printf ("%02x ", buf[i]); + } + printf ("\n"); +} +#endif + +void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + image_header_t *hdr = &header; + char *bootargs = getenv("bootargs"); + void (*kernel) (void) = (void (*)(void)) ntohl (hdr->ih_ep); + + /* Setup parameters */ + memset(PARAM, 0, 0x1000); /* Clear zero page */ + strcpy(COMMAND_LINE, bootargs); + + kernel(); +} diff --git a/lib_sh/time.c b/lib_sh/time.c new file mode 100644 index 0000000000..3d33918f28 --- /dev/null +++ b/lib_sh/time.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processer.h> + +static void tmu_timer_start (unsigned int timer) +{ + if (timer > 2) + return; + + *((volatile unsigned char *) TSTR0) |= (1 << timer); +} + +int timer_init (void) +{ + *(volatile u16 *)TCR0 = 0; + + tmu_timer_start (0); + return 0; +} + +unsigned long long get_ticks (void) +{ + return (0 - *((volatile unsigned int *) TCNT0)); +} + +unsigned long get_timer (unsigned long base) +{ + return ((0 - *((volatile unsigned int *) TCNT0)) - base); +} + +void set_timer (unsigned long t) +{ + *((volatile unsigned int *) TCNT0) = (0 - t); +} + +void reset_timer (void) +{ + set_timer (0); +} + +void udelay (unsigned long usec) +{ + unsigned int start = get_timer (0); + unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000)); + + while (get_timer (0) < end) + continue; +} + +unsigned long get_tbclk (void) +{ + return CFG_HZ; +} diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 98f2775003..84bd29824d 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -90,7 +90,7 @@ $(obj)nand_boot.c: # from drivers/nand directory $(obj)nand_ecc.c: @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c + ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c ######################################################################### diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile index f1034dac24..e3f44b7774 100644 --- a/post/cpu/ppc4xx/Makefile +++ b/post/cpu/ppc4xx/Makefile @@ -24,6 +24,6 @@ LIB = libpostppc4xx.a AOBJS = cache_4xx.o -COBJS = cache.o ether.o fpu.o spr.o uart.o watchdog.o +COBJS = cache.o denali_ecc.o ether.o fpu.o spr.o uart.o watchdog.o include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c index 30d5088425..c86a150692 100644 --- a/post/cpu/ppc4xx/cache.c +++ b/post/cpu/ppc4xx/cache.c @@ -51,8 +51,6 @@ int cache_post_test4 (int tlb, void *p, int size); int cache_post_test5 (int tlb, void *p, int size); int cache_post_test6 (int tlb, void *p, int size); -static int tlb = -1; /* index to the victim TLB entry */ - #ifdef CONFIG_440 static unsigned char testarea[CACHE_POST_SIZE] __attribute__((__aligned__(CACHE_POST_SIZE))); @@ -60,9 +58,10 @@ __attribute__((__aligned__(CACHE_POST_SIZE))); int cache_post_test (int flags) { - void* virt = (void*)CFG_POST_CACHE_ADDR; + void *virt = (void *)CFG_POST_CACHE_ADDR; int ints; int res = 0; + int tlb = -1; /* index to the victim TLB entry */ /* * All 44x variants deal with cache management differently @@ -73,25 +72,23 @@ int cache_post_test (int flags) #ifdef CONFIG_440 int word0, i; - if (tlb < 0) { - /* - * Allocate a new TLB entry, since we are going to modify - * the write-through and caching inhibited storage attributes. - */ - program_tlb((u32)testarea, (u32)virt, - CACHE_POST_SIZE, TLB_WORD2_I_ENABLE); - - /* Find the TLB entry */ - for (i = 0;; i++) { - if (i >= PPC4XX_TLB_SIZE) { - printf ("Failed to program tlb entry\n"); - return -1; - } - word0 = mftlb1(i); - if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) { - tlb = i; - break; - } + /* + * Allocate a new TLB entry, since we are going to modify + * the write-through and caching inhibited storage attributes. + */ + program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE, + TLB_WORD2_I_ENABLE); + + /* Find the TLB entry */ + for (i = 0;; i++) { + if (i >= PPC4XX_TLB_SIZE) { + printf ("Failed to program tlb entry\n"); + return -1; + } + word0 = mftlb1(i); + if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) { + tlb = i; + break; } } #endif diff --git a/post/board/lwmon5/ecc.c b/post/cpu/ppc4xx/denali_ecc.c index 3fa3ba6243..77234838d9 100644 --- a/post/board/lwmon5/ecc.c +++ b/post/cpu/ppc4xx/denali_ecc.c @@ -31,7 +31,7 @@ #include <common.h> #include <watchdog.h> -#ifdef CONFIG_POST +#if defined(CONFIG_POST) && (defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) #include <post.h> @@ -47,12 +47,10 @@ #include <asm/io.h> #include <ppc440.h> -#include "../../../board/lwmon5/sdram.h" - DECLARE_GLOBAL_DATA_PTR; const static unsigned char syndrome_codes[] = { - 0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3, + 0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3, 0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB, 0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2, 0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A, @@ -65,9 +63,9 @@ const static unsigned char syndrome_codes[] = { #define ECC_START_ADDR 0x10 #define ECC_STOP_ADDR 0x2000 -#define ECC_PATTERN 0x0101010101010101ull -#define ECC_PATTERN_CORR 0x0101010101010100ull -#define ECC_PATTERN_UNCORR 0x010101010101010Full +#define ECC_PATTERN 0x01010101 +#define ECC_PATTERN_CORR 0x11010101 +#define ECC_PATTERN_UNCORR 0xF1010101 static int test_ecc_error(void) { @@ -152,68 +150,78 @@ static int test_ecc_error(void) static int test_ecc(unsigned long ecc_addr) { - volatile unsigned long long *ecc_mem; unsigned long value; - unsigned long ecc_data; - volatile unsigned long *lecc_mem; - int pret, ret = 0; + volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr; + int pret; + int ret = 0; sync(); eieio(); WATCHDOG_RESET(); - ecc_mem = (unsigned long long *)ecc_addr; - lecc_mem = (ulong *)ecc_addr; - *ecc_mem = ECC_PATTERN; + debug("Entering test_ecc(0x%08lX)\n", ecc_addr); + out_be32(ecc_mem, ECC_PATTERN); + out_be32(ecc_mem + 1, ECC_PATTERN); + in_be32(ecc_mem); pret = test_ecc_error(); - if (pret != 0) + if (pret != 0) { + debug("pret: expected 0, got %d\n", pret); ret = 1; - - /* disconnect ecc */ + } + /* test for correctable error */ + /* disconnect from ecc storage */ mfsdram(DDR0_22, value); - mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_ECC_DISABLE); - /* injecting error */ - *ecc_mem = ECC_PATTERN_CORR; + /* creating (correctable) single-bit error */ + out_be32(ecc_mem, ECC_PATTERN_CORR); /* enable ecc */ mfsdram(DDR0_22, value); - mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_ECC_ENABLE); + sync(); + eieio(); - ecc_data = *lecc_mem; + in_be32(ecc_mem); pret = test_ecc_error(); /* if read data ok, 1 correctable error must be fixed */ - if (pret != 3) + if (pret != 3) { + debug("pret: expected 3, got %d\n", pret); ret = 1; - + } /* test for uncorrectable error */ /* disconnect from ecc storage */ mfsdram(DDR0_22, value); - mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_NO_ECC_RAM); - /* injecting multiply bit error */ - - *ecc_mem = ECC_PATTERN_UNCORR; + /* creating (uncorrectable) multiple-bit error */ + out_be32(ecc_mem, ECC_PATTERN_UNCORR); /* enable ecc */ mfsdram(DDR0_22, value); - mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) + mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_ECC_ENABLE); + sync(); + eieio(); - ecc_data = *lecc_mem; - /* what the data should be read? */ - + in_be32(ecc_mem); pret = test_ecc_error(); /* info about uncorrectable error must appear */ - if (pret != 5) + if (pret != 5) { + debug("pret: expected 5, got %d\n", pret); ret = 1; + } + /* remove error from SDRAM */ + out_be32(ecc_mem, ECC_PATTERN); + /* clear error caused by read-modify-write */ + mfsdram(DDR0_00, value); + mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); sync(); eieio(); - return ret; } @@ -223,45 +231,37 @@ int ecc_post_test (int flags) unsigned long value; unsigned long iaddr; -#if CONFIG_DDR_ECC sync(); eieio(); + mfsdram(DDR0_22, value); + if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) { + debug("SDRAM ECC not enabled, skipping ECC POST.\n"); + return 0; + } + /* mask all int */ mfsdram(DDR0_01, value); - mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK) + mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF); /* clear error status */ mfsdram(DDR0_00, value); mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); - /* enable full support of ECC */ - mfsdram(DDR0_22, value); - mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) - | DDR0_22_CTRL_RAW_ECC_ENABLE); - - for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) { + for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) { ret = test_ecc(iaddr); if (ret) break; } - - /* clear error status */ - mfsdram(DDR0_00, value); - mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); - /* * Clear possible errors resulting from ECC testing. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); -#endif - return ret; } - #endif /* CONFIG_POST & CFG_POST_ECC */ -#endif /* CONFIG_POST */ +#endif /* defined(CONFIG_POST) && ... */ diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index 09f9a5fcb1..4ac7491343 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -117,11 +117,11 @@ static void ether_post_init (int devnum, int hw_addr) sync (); #endif /* reset emac */ - out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST); + out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST); sync (); for (i = 0;; i++) { - if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST)) + if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST)) break; if (i >= 1000) { printf ("Timeout resetting EMAC\n"); @@ -144,7 +144,7 @@ static void ether_post_init (int devnum, int hw_addr) else mode_reg |= EMAC_M1_OBCI_GT100; - out32 (EMAC_M1 + hw_addr, mode_reg); + out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ @@ -212,40 +212,40 @@ static void ether_post_init (int devnum, int hw_addr) /* set internal loopback mode */ #ifdef CFG_POST_ETHER_EXT_LOOPBACK - out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 | - EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | - EMAC_M1_MF_100MBPS | EMAC_M1_IST | - in32 (EMAC_M1)); + out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 | + EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | + EMAC_M1_MF_100MBPS | EMAC_M1_IST | + in_be32 ((void*)(EMAC_M1 + hw_addr))); #else - out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE | - EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | - EMAC_M1_MF_100MBPS | EMAC_M1_IST | - in32 (EMAC_M1)); + out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE | + EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | + EMAC_M1_MF_100MBPS | EMAC_M1_IST | + in_be32 ((void*)(EMAC_M1 + hw_addr))); #endif /* set transmit enable & receive enable */ - out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE); /* enable broadcast address */ - out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE); + out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE); /* set transmit request threshold register */ - out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */ + out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000); + out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000); #else /* 405s have a 16 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000); + out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000); #endif /* defined(CONFIG_440) */ - out32 (EMAC_TXM1 + hw_addr, 0xf8640000); + out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out32 (EMAC_TXM0 + hw_addr, 0x00000003); + out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003); /* Frame gap set */ - out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008); + out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008); sync (); } @@ -272,7 +272,7 @@ static void ether_post_halt (int devnum, int hw_addr) udelay (1000); } /* emac reset */ - out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST); + out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST); #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* remove clocks for EMAC internal loopback */ @@ -302,7 +302,7 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length) flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length); sync (); - out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0); + out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0); sync (); } diff --git a/post/board/lwmon5/Makefile b/sh_config.mk index c3f54e37b8..49d50f7ebd 100644 --- a/post/board/lwmon5/Makefile +++ b/sh_config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2007 +# (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -21,9 +21,4 @@ # MA 02111-1307 USA # - -LIB = libpostlwmon5.a - -COBJS = ecc.o - -include $(TOPDIR)/post/rules.mk +PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ |
