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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-01-06 22:14:20 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-01-13 07:25:04 -0800 |
| commit | fa48e51013280396f02e668a5d9f1d606d69be35 (patch) | |
| tree | 8cc117f5311b0367f14ab19dc508e1405f29f444 | |
| parent | 24ef04280cc9730679d390acb41bb02487527303 (diff) | |
| download | talos-obmc-uboot-fa48e51013280396f02e668a5d9f1d606d69be35.tar.gz talos-obmc-uboot-fa48e51013280396f02e668a5d9f1d606d69be35.zip | |
x86: Remove include/configs/coreboot.h
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | board/coreboot/coreboot/MAINTAINERS | 2 | ||||
| -rw-r--r-- | include/configs/coreboot.h | 70 |
2 files changed, 1 insertions, 71 deletions
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index 6ce66f551f..2736aa0282 100644 --- a/board/coreboot/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -2,5 +2,5 @@ COREBOOT BOARD M: Simon Glass <sjg@chromium.org> S: Maintained F: board/coreboot/coreboot/ -F: include/configs/coreboot.h +F: include/configs/chromebook_link.h F: configs/coreboot-x86_defconfig diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h deleted file mode 100644 index a0d99522b7..0000000000 --- a/include/configs/coreboot.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <configs/x86-common.h> - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_LAST_STAGE_INIT -#define CONFIG_SYS_EARLY_PCI_INIT - -#define CONFIG_SYS_CAR_ADDR 0x19200000 -#define CONFIG_SYS_CAR_SIZE (16 * 1024) -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x01400000 - -#define CONFIG_BOOTSTAGE -#define CONFIG_BOOTSTAGE_REPORT -#define CONFIG_BOOTSTAGE_FDT -#define CONFIG_CMD_BOOTSTAGE -/* Place to stash bootstage data from first-stage U-Boot */ -#define CONFIG_BOOTSTAGE_STASH 0x0110f000 -#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc -#define CONFIG_BOOTSTAGE_USER_COUNT 60 - -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} - -#define CONFIG_X86_SERIAL - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ - "stdout=vga,serial,cbmem\0" \ - "stderr=vga,serial,cbmem\0" - -#define CONFIG_NR_DRAM_BANKS 4 - -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) - -#define CONFIG_BOOTDELAY 2 - -#define CONFIG_CROS_EC -#define CONFIG_CROS_EC_LPC -#define CONFIG_CMD_CROS_EC -#define CONFIG_ARCH_EARLY_INIT_R - -#endif /* __CONFIG_H */ |
