Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master

65 files changed, 1364 insertions, 359 deletions

diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c
index 45b8195012..371f67f41d 100644
--- a/board/MAI/AmigaOneG3SE/articiaS_pci.c
+++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c
@@ -313,7 +313,7 @@ void articiaS_pci_init (void)
 		   ARTICIAS_SYS_BUS,
 		   ARTICIAS_SYS_PHYS,
 		   ARTICIAS_SYS_MAXSIZE,
-		   PCI_REGION_MEM | PCI_REGION_MEMORY);
+		   PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
     /* PCI memory space */
     pci_set_region(articiaS_hose.regions + 1,
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 06109286e9..6c40e94416 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -31,6 +31,8 @@
 #include <i2c.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Clocks in use */
 #define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
 			 CLOCK_SCCR1_LPC_EN |				\
@@ -38,6 +40,7 @@
 			 CLOCK_SCCR1_PSCFIFO_EN |			\
 			 CLOCK_SCCR1_DDR_EN |				\
 			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
 			 CLOCK_SCCR1_PCI_EN |				\
 			 CLOCK_SCCR1_TPR_EN)
 
@@ -101,6 +104,9 @@ int board_early_init_f (void)
 	 */
 	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
 	im->clk.sccr[1] = SCCR2_CLOCKS_EN;
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN;
+#endif
 
 	return 0;
 }
@@ -290,17 +296,28 @@ static  iopin_t ioregs_init[] = {
 	}
 };
 
+static  iopin_t rev2_silicon_pci_ioregs_init[] = {
+	/* FUNC0=PCI Sets next 54 to PCI pads */
+	{
+		IOCTL_PCI_AD31, 54, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+	}
+};
+
 int checkboard (void)
 {
 	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
 	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 
 	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 		brd_rev, cpld_rev);
 	/* initialize function mux & slew rate IO inter alia on IO Pins  */
 
-
 	iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
+	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
+		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+	}
 
 	return 0;
 }
@@ -312,3 +329,104 @@ void ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	debug ("init_ide_reset\n");
+
+	/*
+	 * Clear the reset bit to reset the interface
+	 * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
+	 */
+	immr->pata.pata_ata_control = 0;
+	udelay(100);
+	/* Assert the reset bit to enable the interface */
+	immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+	udelay(100);
+
+}
+
+void ide_set_reset (int idereset)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	debug ("ide_set_reset(%d)\n", idereset);
+
+	if (idereset) {
+		immr->pata.pata_ata_control = 0;
+		udelay(100);
+	} else {
+		immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+		udelay(100);
+	}
+}
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+int ide_preinit (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	long t;
+	const struct {
+		short t0;
+		short t1;
+		short t2_8;
+		short t2_16;
+		short t2i;
+		short t4;
+		short t9;
+		short tA;
+	} pio_specs = {
+		.t0    = 600,
+		.t1    =  70,
+		.t2_8  = 290,
+		.t2_16 = 165,
+		.t2i   =   0,
+		.t4    =  30,
+		.t9    =  20,
+		.tA    =  50,
+	};
+	union {
+		u32 config;
+		struct {
+			u8 field1;
+			u8 field2;
+			u8 field3;
+			u8 field4;
+		}bytes;
+	}cfg;
+
+	debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
+		(u32)&immr->pata);
+
+	/* Set the reset bit to 1 to enable the interface */
+	immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+
+	/* Init timings : we use PIO mode 0 timings */
+	t = 1000000000 / gd->ips_clk;	/* period in ns */
+	cfg.bytes.field1 = 3;
+	cfg.bytes.field2 = 3;
+	cfg.bytes.field3 = (pio_specs.t1 + t) / t;
+	cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
+
+	immr->pata.pata_time1 = cfg.config;
+
+	cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
+	cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
+	cfg.bytes.field3 = 1;
+	cfg.bytes.field4 = (pio_specs.t4 + t) / t;
+
+	immr->pata.pata_time2 = cfg.config;
+
+	cfg.config = immr->pata.pata_time3;
+	cfg.bytes.field1 = (pio_specs.t9 + t) / t;
+
+	immr->pata.pata_time3 = cfg.config;
+	debug ("PATA preinit complete.\n");
+
+	return 0;
+}
+
+#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c
index 4f7dda0e3e..41a135314f 100644
--- a/board/ads5121/ads5121_diu.c
+++ b/board/ads5121/ads5121_diu.c
@@ -37,7 +37,11 @@
 #include <video_fb.h>
 #endif
 
+#ifdef CONFIG_FSL_DIU_LOGO_BMP
 extern unsigned int FSL_Logo_BMP[];
+#else
+#define FSL_Logo_BMP NULL
+#endif
 
 static int xres, yres;
 
@@ -61,16 +65,40 @@ void diu_set_pixel_clock(unsigned int pixclock)
 	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
 }
 
+char *valid_bmp(char *addr)
+{
+	unsigned long h_addr;
+
+	h_addr = simple_strtoul(addr, NULL, 16);
+	if (h_addr < CONFIG_SYS_FLASH_BASE ||
+			h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+		printf("bmp addr %lx is not a valid flash address\n", h_addr);
+		return 0;
+	} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
+		printf("bmp addr is not a bmp\n");
+		return 0;
+	} else
+		return (char *)h_addr;
+}
+
 int ads5121_diu_init(void)
 {
 	unsigned int pixel_format;
+	char *bmp = NULL;
+	char *bmp_env;
 
 	xres = 1024;
 	yres = 768;
 	pixel_format = 0x88883316;
 
-	return fsl_diu_init(xres, pixel_format, 0,
-		     (unsigned char *)FSL_Logo_BMP);
+	debug("ads5121_diu_init\n");
+	bmp_env = getenv("diu_bmp_addr");
+	if (bmp_env) {
+		bmp = valid_bmp(bmp_env);
+	}
+	if (!bmp)
+		bmp = FSL_Logo_BMP;
+	return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp);
 }
 
 int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
diff --git a/board/ads5121/pci.c b/board/ads5121/pci.c
index b747e812ad..806c428e4c 100644
--- a/board/ads5121/pci.c
+++ b/board/ads5121/pci.c
@@ -153,7 +153,7 @@ pci_init_board(void)
 		       CONFIG_PCI_SYS_MEM_BUS,
 		       CONFIG_PCI_SYS_MEM_PHYS,
 		       gd->ram_size,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 4;
 
diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c
index a9b3fd89fb..5fbcd37cee 100644
--- a/board/amirix/ap1000/pci.c
+++ b/board/amirix/ap1000/pci.c
@@ -294,7 +294,7 @@ void pci_init_board (void)
 	pci_set_region (hose->regions + 0,
 			AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
 			AP1000_SYS_MEM_SIZE,
-			PCI_REGION_MEM | PCI_REGION_MEMORY);
+			PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI Memory space */
 	pci_set_region (hose->regions + 1,
diff --git a/board/armltd/integratorap/integratorap.c b/board/armltd/integratorap/integratorap.c
index ddacabb2ea..9631967b07 100644
--- a/board/armltd/integratorap/integratorap.c
+++ b/board/armltd/integratorap/integratorap.c
@@ -428,7 +428,7 @@ void pci_init_board (void)
 	/* System memory space */
 	pci_set_region (hose->regions + 0,
 			0x00000000, 0x40000000, 0x01000000,
-			PCI_REGION_MEM | PCI_REGION_MEMORY);
+			PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI Memory - config space */
 	pci_set_region (hose->regions + 1,
diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c
index b147ce77ef..7b764b497b 100644
--- a/board/bf537-stamp/spi_flash.c
+++ b/board/bf537-stamp/spi_flash.c
@@ -180,13 +180,7 @@ static struct manufacturer_info flash_manufacturers[] = {
  *	BF51x, BF533, BF561: SSEL2
  */
 #ifndef CONFIG_SPI_FLASH_SSEL
-# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
-     defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
-     defined(__ADSPBF51x__)
-#  define CONFIG_SPI_FLASH_SSEL 2
-# else
-#  define CONFIG_SPI_FLASH_SSEL 1
-# endif
+# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL
 #endif
 #define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL)
 
diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c
index ec0d76125e..ddfbea9a08 100644
--- a/board/dave/common/pci.c
+++ b/board/dave/common/pci.c
@@ -179,7 +179,7 @@ void pci_init(void)
   /* System memory space */
   pci_set_region(hose->regions + 0,
 		 0x00000000, 0x00000000, 0x01000000,
-		 PCI_REGION_MEM | PCI_REGION_MEMORY);
+		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
   /* PCI Memory space */
   pci_set_region(hose->regions + 1,
diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c
index 46e5a8bb17..38dd49856b 100644
--- a/board/eltec/bab7xx/pci.c
+++ b/board/eltec/bab7xx/pci.c
@@ -50,7 +50,7 @@ void pci_init_board(void)
     * so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1)
     */
 	CONFIG_SYS_PCI_MEMORY_SIZE-1,
-	PCI_REGION_MEM | PCI_REGION_MEMORY);
+	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
     /* PCI memory space */
     pci_set_region(hose->regions + 1,
diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c
index bf133b77de..29485319a5 100644
--- a/board/eltec/elppc/pci.c
+++ b/board/eltec/elppc/pci.c
@@ -45,7 +45,7 @@ void pci_init_board(void)
 	CONFIG_SYS_PCI_MEMORY_BUS,
 	CONFIG_SYS_PCI_MEMORY_PHYS,
 	CONFIG_SYS_PCI_MEMORY_SIZE,
-	PCI_REGION_MEM | PCI_REGION_MEMORY);
+	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
     /* PCI memory space */
     pci_set_region(hose->regions + 1,
diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c
index dcb764cd1f..83f810307b 100644
--- a/board/esd/common/pci.c
+++ b/board/esd/common/pci.c
@@ -179,7 +179,7 @@ void pci_init_board(void)
   /* System memory space */
   pci_set_region(hose->regions + 0,
 		 0x00000000, 0x00000000, 0x01000000,
-		 PCI_REGION_MEM | PCI_REGION_MEMORY);
+		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
   /* PCI Memory space */
   pci_set_region(hose->regions + 1,
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
index 2a48dd24ee..212fb52198 100644
--- a/board/freescale/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -228,7 +228,7 @@ void pci_init_board(void)
 		       CONFIG_SYS_PCI_SLV_MEM_LOCAL,
 		       CONFIG_SYS_PCI_SLV_MEM_BUS,
 		       CONFIG_SYS_PCI_SLV_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose[0].region_count = 4;
 
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
index fd2c172de4..8da7117ec2 100644
--- a/board/freescale/mpc8349itx/pci.c
+++ b/board/freescale/mpc8349itx/pci.c
@@ -210,7 +210,7 @@ void pci_init_board(void)
 	pci_set_region(hose->regions + 3,
 		       CONFIG_PCI_SYS_MEM_BUS,
 		       CONFIG_PCI_SYS_MEM_PHYS,
-		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 4;
 
@@ -301,7 +301,7 @@ void pci_init_board(void)
 	pci_set_region(hose->regions + 3,
 		       CONFIG_PCI_SYS_MEM_BUS,
 		       CONFIG_PCI_SYS_MEM_PHYS,
-		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 4;
 
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
index 935aca26db..7ac35dced9 100644
--- a/board/freescale/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -228,7 +228,7 @@ void pci_init_board(void)
 		       CONFIG_SYS_PCI_SLV_MEM_LOCAL,
 		       CONFIG_SYS_PCI_SLV_MEM_BUS,
 		       CONFIG_SYS_PCI_SLV_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose[0].region_count = 4;
 
diff --git a/board/pcippc2/cpc710_pci.c b/board/pcippc2/cpc710_pci.c
index bed8aeab09..ccd18e1513 100644
--- a/board/pcippc2/cpc710_pci.c
+++ b/board/pcippc2/cpc710_pci.c
@@ -215,7 +215,7 @@ void cpc710_pci_init (void)
 		 PCI_MEMORY_BUS,
 		 PCI_MEMORY_PHYS,
 		 PCI_MEMORY_MAXSIZE,
-		 PCI_REGION_MEM | PCI_REGION_MEMORY);
+		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
   /* PCI memory space */
   pci_set_region(local_hose.regions + 1,
@@ -265,7 +265,7 @@ void cpc710_pci_init (void)
 		 PCI_MEMORY_BUS,
 		 PCI_MEMORY_PHYS,
 		 PCI_MEMORY_MAXSIZE,
-		 PCI_REGION_MEMORY);
+		 PCI_REGION_SYS_MEMORY);
 
   /* PCI memory space */
   pci_set_region(cpci_hose.regions + 1,
diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c
index bf133b77de..29485319a5 100644
--- a/board/ppmc7xx/pci.c
+++ b/board/ppmc7xx/pci.c
@@ -45,7 +45,7 @@ void pci_init_board(void)
 	CONFIG_SYS_PCI_MEMORY_BUS,
 	CONFIG_SYS_PCI_MEMORY_PHYS,
 	CONFIG_SYS_PCI_MEMORY_SIZE,
-	PCI_REGION_MEM | PCI_REGION_MEMORY);
+	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
     /* PCI memory space */
     pci_set_region(hose->regions + 1,
diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
index 9022c55d57..ac5f30b46e 100644
--- a/board/sbc8349/pci.c
+++ b/board/sbc8349/pci.c
@@ -197,7 +197,7 @@ pci_init_board(void)
 		       CONFIG_PCI_SYS_MEM_BUS,
 		       CONFIG_PCI_SYS_MEM_PHYS,
 		       gd->ram_size,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 4;
 
@@ -293,7 +293,7 @@ pci_init_board(void)
 		       CONFIG_PCI_SYS_MEM_BUS,
 		       CONFIG_PCI_SYS_MEM_PHYS,
 		       gd->ram_size,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 4;
 
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 519b0f749d..a77942022a 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -470,7 +470,7 @@ pci_init_board(void)
 			       CONFIG_SYS_PCI_MEMORY_BUS,
 			       CONFIG_SYS_PCI_MEMORY_PHYS,
 			       CONFIG_SYS_PCI_MEMORY_SIZE,
-			       PCI_REGION_MEM | PCI_REGION_MEMORY);
+			       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(r++,
diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c
index 4c9192341e..6ff42937c8 100644
--- a/board/tb0229/vr4131-pci.c
+++ b/board/tb0229/vr4131-pci.c
@@ -235,7 +235,7 @@ void init_vr4131_pci (struct pci_controller *hose)
 	pci_set_region (hose->regions + 3,
 			0x00000000,
 			0x80000000,
-			0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
+			0x04000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 4;
 
diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
index 0eedf4ae46..cb2cb8d32d 100644
--- a/board/tqc/tqm834x/pci.c
+++ b/board/tqc/tqm834x/pci.c
@@ -181,7 +181,7 @@ pci_init_board(void)
 		       CONFIG_PCI_SYS_MEM_BUS,
 		       CONFIG_PCI_SYS_MEM_PHYS,
 		       CONFIG_PCI_SYS_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 3;
 
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 8e9251d4aa..b2d6f8479a 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -283,6 +283,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_SYS_MBAR)
 	print_num ("mbar",		bd->bi_mbar_base);
 #endif
+	print_str ("cpufreq",		strmhz(buf, bd->bi_intfreq));
 	print_str ("busfreq",		strmhz(buf, bd->bi_busfreq));
 #ifdef CONFIG_PCI
 	print_str ("pcifreq",		strmhz(buf, bd->bi_pcifreq));
@@ -322,7 +323,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	puts ("\nip_addr     = ");
 	print_IPaddr (bd->bi_ip_addr);
 #endif
-	printf ("\nbaudrate    = %d bps\n", bd->bi_baudrate);
+	printf ("\nbaudrate    = %ld bps\n", bd->bi_baudrate);
 
 	return 0;
 }
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index c9b9a47995..8c6ed35b32 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -45,6 +45,10 @@
 #include <mpc5xxx.h>
 #endif
 
+#ifdef CONFIG_MPC512X
+#include <mpc512x.h>
+#endif
+
 #include <ide.h>
 #include <ata.h>
 
diff --git a/common/env_nand.c b/common/env_nand.c
index 8af9e74aac..e490775ecf 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -304,9 +304,11 @@ void env_relocate_spec (void)
 	crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
 	crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
 
-	if(!crc1_ok && !crc2_ok)
+	if(!crc1_ok && !crc2_ok) {
+		free(tmp_env1);
+		free(tmp_env2);
 		return use_default();
-	else if(crc1_ok && !crc2_ok)
+	} else if(crc1_ok && !crc2_ok)
 		gd->env_valid = 1;
 	else if(!crc1_ok && crc2_ok)
 		gd->env_valid = 2;
diff --git a/common/fdt_support.c b/common/fdt_support.c
index a79bc085b2..b54f8868d9 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -646,8 +646,8 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
 	for (r = 0; r < hose->region_count; r++) {
 		u64 bus_start, phys_start, size;
 
-		/* skip if !PCI_REGION_MEMORY */
-		if (!(hose->regions[r].flags & PCI_REGION_MEMORY))
+		/* skip if !PCI_REGION_SYS_MEMORY */
+		if (!(hose->regions[r].flags & PCI_REGION_SYS_MEMORY))
 			continue;
 
 		bus_start = (u64)hose->regions[r].bus_start;
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index 6091f8cef1..ae0016de18 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -20,7 +20,7 @@
 #include "serial.h"
 
 __attribute__((always_inline))
-static inline uint32_t serial_init(void)
+static inline void serial_init(void)
 {
 #ifdef __ADSPBF54x__
 # ifdef BFIN_BOOT_UART_USE_RTS
@@ -61,25 +61,16 @@ static inline uint32_t serial_init(void)
 	}
 #endif
 
-	uint32_t old_baud;
-	if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-		old_baud = serial_early_get_baud();
-	else
-		old_baud = CONFIG_BAUDRATE;
-
 	if (BFIN_DEBUG_EARLY_SERIAL) {
+		int ucen = *pUART_GCTL & UCEN;
 		serial_early_init();
 
 		/* If the UART is off, that means we need to program
 		 * the baud rate ourselves initially.
 		 */
-		if (!old_baud) {
-			old_baud = CONFIG_BAUDRATE;
+		if (ucen != UCEN)
 			serial_early_set_baud(CONFIG_BAUDRATE);
-		}
 	}
-
-	return old_baud;
 }
 
 __attribute__((always_inline))
@@ -93,30 +84,6 @@ static inline void serial_deinit(void)
 #endif
 }
 
-/* We need to reset the baud rate when we have early debug turned on
- * or when we are booting over the UART.
- * XXX: we should fix this to calc the old baud and restore it rather
- *      than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
- *      to figure out how to avoid the division in the baud calc ...
- */
-__attribute__((always_inline))
-static inline void serial_reset_baud(uint32_t baud)
-{
-	if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-		return;
-
-#ifndef CONFIG_LDR_LOAD_BAUD
-# define CONFIG_LDR_LOAD_BAUD 115200
-#endif
-
-	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-		serial_early_set_baud(baud);
-	else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-		serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
-	else
-		serial_early_set_baud(CONFIG_BAUDRATE);
-}
-
 __attribute__((always_inline))
 static inline void serial_putc(char c)
 {
@@ -133,12 +100,22 @@ static inline void serial_putc(char c)
 }
 
 
-/* Max SCLK can be 133MHz ... dividing that by 4 gives
- * us a freq of 33MHz for SPI which should generally be
+/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
+ * us a freq of 16MHz for SPI which should generally be
  * slow enough for the slow reads the bootrom uses.
  */
+#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
+    ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
+     (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
+# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
+#else
+# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
+#endif
 #ifndef CONFIG_SPI_BAUD_INITBLOCK
-# define CONFIG_SPI_BAUD_INITBLOCK 4
+# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
+#endif
+#ifdef SPI0_BAUD
+# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
 #endif
 
 /* PLL_DIV defines */
@@ -168,11 +145,18 @@ static inline void serial_putc(char c)
 #ifndef CONFIG_EBIU_RSTCTL_VAL
 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
 #endif
+#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
+# error invalid EBIU_RSTCTL value: must not set reserved bits
+#endif
 
 #ifndef CONFIG_EBIU_MBSCTL_VAL
 # define CONFIG_EBIU_MBSCTL_VAL 0
 #endif
 
+#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
+# error invalid EBIU_DDRQUE value: must not set reserved bits
+#endif
+
 /* Make sure our voltage value is sane so we don't blow up! */
 #ifndef CONFIG_VR_CTL_VAL
 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
@@ -199,6 +183,9 @@ static inline void serial_putc(char c)
 # elif defined(__ADSPBF54x__)	/* TBD; use default */
 #  undef CONFIG_VR_CTL_VLEV
 #  define CONFIG_VR_CTL_VLEV VLEV_120
+# elif defined(__ADSPBF538__) || defined(__ADSPBF539__)	/* TBD; use default */
+#  undef CONFIG_VR_CTL_VLEV
+#  define CONFIG_VR_CTL_VLEV VLEV_125
 # endif
 
 # ifdef CONFIG_BFIN_MAC
@@ -216,10 +203,17 @@ static inline void serial_putc(char c)
 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
 #endif
 
-__attribute__((saveall))
+BOOTROM_CALLED_FUNC_ATTR
 void initcode(ADI_BOOT_DATA *bootstruct)
 {
-	uint32_t old_baud = serial_init();
+	/* Save the clock pieces that are used in baud rate calculation */
+	unsigned int sdivB, divB, vcoB;
+	serial_init();
+	if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+		sdivB = bfin_read_PLL_DIV() & 0xf;
+		vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+		divB = serial_early_get_div();
+	}
 
 #ifdef CONFIG_HW_WATCHDOG
 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
@@ -244,12 +238,11 @@ void initcode(ADI_BOOT_DATA *bootstruct)
 	 * boot.  Once we switch over to u-boot's SPI flash driver, we'll
 	 * increase the speed appropriately.
 	 */
-	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#ifdef SPI0_BAUD
-		bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
-#else
+	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
+		if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
+			bootstruct->dFlags |= BFLAG_FASTREAD;
 		bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
-#endif
+	}
 
 	serial_putc('B');
 
@@ -267,40 +260,68 @@ void initcode(ADI_BOOT_DATA *bootstruct)
 	bfin_write_SIC_IWR(1);
 #endif
 
-	serial_putc('L');
+	/* With newer bootroms, we use the helper function to set up
+	 * the memory controller.  Older bootroms lacks such helpers
+	 * so we do it ourselves.
+	 */
+	if (BOOTROM_CAPS_SYSCONTROL) {
+		serial_putc('S');
+
+		ADI_SYSCTRL_VALUES memory_settings;
+		memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+		memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
+		memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
+		memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
+		syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
+			(CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
+	} else {
+		serial_putc('L');
 
-	bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
+		bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
 
-	serial_putc('A');
+		serial_putc('A');
 
-	/* Only reprogram when needed to avoid triggering unnecessary
-	 * PLL relock sequences.
-	 */
-	if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
-		serial_putc('!');
-		bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
-		asm("idle;");
-	}
+		/* Only reprogram when needed to avoid triggering unnecessary
+		 * PLL relock sequences.
+		 */
+		if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
+			serial_putc('!');
+			bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
+			asm("idle;");
+		}
 
-	serial_putc('C');
+		serial_putc('C');
 
-	bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
+		bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 
-	serial_putc('K');
+		serial_putc('K');
 
-	/* Only reprogram when needed to avoid triggering unnecessary
-	 * PLL relock sequences.
-	 */
-	if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
-		serial_putc('!');
-		bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
-		asm("idle;");
+		/* Only reprogram when needed to avoid triggering unnecessary
+		 * PLL relock sequences.
+		 */
+		if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+			serial_putc('!');
+			bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
+			asm("idle;");
+		}
 	}
 
 	/* Since we've changed the SCLK above, we may need to update
 	 * the UART divisors (UART baud rates are based on SCLK).
+	 * Do the division by hand as there are no native instructions
+	 * for dividing which means we'd generate a libgcc reference.
 	 */
-	serial_reset_baud(old_baud);
+	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+		unsigned int sdivR, vcoR;
+		sdivR = bfin_read_PLL_DIV() & 0xf;
+		vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+		int dividend = sdivB * divB * vcoR;
+		int divisor = vcoB * sdivR;
+		unsigned int quotient;
+		for (quotient = 0; dividend > 0; ++quotient)
+			dividend -= divisor;
+		serial_early_put_div(quotient - ANOMALY_05000230);
+	}
 
 	serial_putc('F');
 
diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h
index f671096768..ce39148f83 100644
--- a/cpu/blackfin/serial.h
+++ b/cpu/blackfin/serial.h
@@ -156,16 +156,25 @@ static inline void serial_early_init(void)
 }
 
 __attribute__((always_inline))
-static inline uint32_t serial_early_get_baud(void)
+static inline void serial_early_put_div(uint16_t divisor)
 {
-	/* If the UART isnt enabled, then we are booting an LDR
-	 * from a non-UART source (so like flash) which means
-	 * the baud rate here is meaningless.
-	 */
-	if ((*pUART_GCTL & UCEN) != UCEN)
-		return 0;
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
 
-#if (0)	/* See comment for serial_reset_baud() in initcode.c */
+	/* Program the divisor to get the baud rate we want */
+	*pUART_DLL = LOB(divisor);
+	*pUART_DLH = HIB(divisor);
+	SSYNC();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint16_t serial_early_get_div(void)
+{
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH();
 	SSYNC();
@@ -173,16 +182,12 @@ static inline uint32_t serial_early_get_baud(void)
 	uint8_t dll = *pUART_DLL;
 	uint8_t dlh = *pUART_DLH;
 	uint16_t divisor = (dlh << 8) | dll;
-	uint32_t baud = get_sclk() / (divisor * 16);
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
 	ACCESS_PORT_IER();
 	SSYNC();
 
-	return baud;
-#else
-	return CONFIG_BAUDRATE;
-#endif
+	return divisor;
 }
 
 __attribute__((always_inline))
@@ -192,20 +197,7 @@ static inline void serial_early_set_baud(uint32_t baud)
 	 * weird multiplication is to make sure we over sample just
 	 * a little rather than under sample the incoming signals.
 	 */
-	uint16_t divisor = (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230;
-
-	/* Set DLAB in LCR to Access DLL and DLH */
-	ACCESS_LATCH();
-	SSYNC();
-
-	/* Program the divisor to get the baud rate we want */
-	*pUART_DLL = LOB(divisor);
-	*pUART_DLH = HIB(divisor);
-	SSYNC();
-
-	/* Clear DLAB in LCR to Access THR RBR IER */
-	ACCESS_PORT_IER();
-	SSYNC();
+	serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
 }
 
 #ifndef BFIN_IN_INITCODE
@@ -235,32 +227,6 @@ static inline void serial_early_puts(const char *s)
 #endif
 .endm
 
-/* Recursively expand calls to _serial_putc for every byte
- * passed to us.  Append a newline when we're all done.
- */
-.macro _serial_early_putc byte:req morebytes:vararg
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-	R0 = \byte;
-	call _serial_putc;
-.ifnb \morebytes
-	_serial_early_putc \morebytes
-.else
-.if (\byte != '\n')
-	_serial_early_putc '\n'
-.endif
-.endif
-#endif
-.endm
-
-/* Wrapper around recurisve _serial_early_putc macro which
- * simply prepends the string "Early: "
- */
-.macro serial_early_putc byte:req morebytes:vararg
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-	_serial_early_putc 'E', 'a', 'r', 'l', 'y', ':', ' ', \byte, \morebytes
-#endif
-.endm
-
 /* Since we embed the string right into our .text section, we need
  * to find its address.  We do this by getting our PC and adding 2
  * bytes (which is the length of the jump instruction).  Then we
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 12e8f38716..b958f8dc04 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -341,7 +341,7 @@ void pci_sc520_init(struct pci_controller *hose)
 		       SC520_PCI_MEMORY_BUS,
 		       SC520_PCI_MEMORY_PHYS,
 		       SC520_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 66f9164d56..11f70b0dbf 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -181,9 +181,14 @@ void cpu_init_f(void)
 	/* FlexBus Chipselect */
 	init_fbcs();
 
+#ifdef CONFIG_SYS_MCF_SYNCR
+	/* Set clockspeed according to board header file */
+	mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
+#else
 	/* Set clockspeed to 100MHz */
-	mbar_writeShort(MCF_FMPLL_SYNCR,
+	mbar_writeLong(MCF_FMPLL_SYNCR,
 			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
+#endif
 	while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
 }
 
@@ -219,7 +224,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 {
 	if (setclear) {
 		/* Enable Ethernet pins */
-		mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
+		mbar_writeByte(MCF_GPIO_PAR_FECI2C,
+			       (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
 	} else {
 	}
 
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index fe51fb4803..c93a5180eb 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -77,7 +77,8 @@ int get_clocks (void)
 #endif
 
 	gd->cpu_clk = CONFIG_SYS_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else
 	gd->bus_clk = gd->cpu_clk;
diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c
index c4a3b05ee6..7f9784c3cb 100644
--- a/cpu/mcf5445x/pci.c
+++ b/cpu/mcf5445x/pci.c
@@ -146,7 +146,7 @@ void pci_mcf5445x_init(struct pci_controller *hose)
 
 	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
 		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 3;
 
diff --git a/cpu/mcf547x_8x/pci.c b/cpu/mcf547x_8x/pci.c
index f5c25367fb..f867dc1279 100644
--- a/cpu/mcf547x_8x/pci.c
+++ b/cpu/mcf547x_8x/pci.c
@@ -149,7 +149,7 @@ void pci_mcf547x_8x_init(struct pci_controller *hose)
 
 	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
 		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 3;
 
diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile
index e8f1060748..297d135845 100644
--- a/cpu/mpc512x/Makefile
+++ b/cpu/mpc512x/Makefile
@@ -26,6 +26,9 @@ LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
+ifdef CONFIG_IIM
+COBJS	+= iim.o
+endif
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc512x/iim.c b/cpu/mpc512x/iim.c
new file mode 100644
index 0000000000..6cdc422594
--- /dev/null
+++ b/cpu/mpc512x/iim.c
@@ -0,0 +1,394 @@
+/*
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * ADS5121 IIM (Fusebox) Interface
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CMD_FUSE
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char cur_bank = '1';
+
+char *iim_err_msg(u32 err)
+{
+	static char *IIM_errs[] = {
+		"Parity Error in cache",
+		"Explicit Sense Cycle Error",
+		"Write to Locked Register Error",
+		"Read Protect Error",
+		"Override Protect Error",
+		"Write Protect Error"};
+
+	int i;
+
+	if (!err)
+		return "";
+	for (i = 1; i < 8; i++)
+		if (err & (1 << i))
+			printf("IIM - %s\n", IIM_errs[i-1]);
+	return "";
+}
+
+int in_range(int n, int min, int max, char *err, char *usg)
+{
+	if (n > max || n < min) {
+		printf(err);
+		printf("Usage:\n%s\n", usg);
+		return 0;
+	}
+	return 1;
+}
+
+int ads5121_fuse_read(int bank, int fstart, int num)
+{
+	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+	u32 *iim_fb, dummy;
+	int f, ctr;
+
+	out_be32(&iim->err, in_be32(&iim->err));
+	if (bank == 0)
+		iim_fb = (u32 *)&(iim->fbac0);
+	else
+		iim_fb = (u32 *)&(iim->fbac1);
+/* try a read to see if Read Protect is set */
+	dummy = in_be32(&iim_fb[0]);
+	if (in_be32(&iim->err) & IIM_ERR_RPE) {
+		printf("\tRead protect fuse is set\n");
+		out_be32(&iim->err, IIM_ERR_RPE);
+		return 0;
+	}
+	printf("Reading Bank %d cache\n", bank);
+	for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) {
+		if (ctr % 4 == 0)
+			printf("F%2d:", f);
+		printf("\t%#04x", (u8)(iim_fb[f]));
+		if (ctr % 4 == 3)
+			printf("\n");
+	}
+	if (ctr % 4 != 0)
+		printf("\n");
+}
+
+int ads5121_fuse_override(int bank, int f, u8 val)
+{
+	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+	u32 *iim_fb;
+	u32 iim_stat;
+	int i;
+
+	out_be32(&iim->err, in_be32(&iim->err));
+	if (bank == 0)
+		iim_fb = (u32 *)&(iim->fbac0);
+	else
+		iim_fb = (u32 *)&(iim->fbac1);
+/* try a read to see if Read Protect is set */
+	iim_stat = in_be32(&iim_fb[0]);
+	if (in_be32(&iim->err) & IIM_ERR_RPE) {
+		printf("Read protect fuse is set on bank %d;"
+			"Override protect may also be set\n", bank);
+		printf("An attempt will be made to override\n");
+		out_be32(&iim->err, IIM_ERR_RPE);
+	}
+	if (iim_stat & IIM_FBAC_FBOP) {
+		printf("Override protect fuse is set on bank %d\n", bank);
+		return 1;
+	}
+	if (f > IIM_FMAX) /* reset the entire bank */
+		for (i = 0; i < IIM_FMAX + 1; i++)
+			out_be32(&iim_fb[i],  0);
+	else
+		out_be32(&iim_fb[f], val);
+	return 0;
+}
+
+int ads5121_fuse_prog(cmd_tbl_t *cmdtp, int bank, char *fuseno_bitno)
+{
+	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+	int f, i, bitno;
+	u32 stat, err;
+
+	f = simple_strtol(fuseno_bitno, NULL, 10);
+	if (f == 0 && fuseno_bitno[0] != '0')
+		f = -1;
+	if (!in_range(f, 0, IIM_FMAX,
+		"<frow> must be between 0-31\n\n", cmdtp->usage))
+		return 1;
+	bitno = -1;
+	for (i = 0; i < 6; i++) {
+		if (fuseno_bitno[i] == '_') {
+			bitno = simple_strtol(&(fuseno_bitno[i+1]), NULL, 10);
+			if (bitno == 0 && fuseno_bitno[i+1] != '0')
+				bitno = -1;
+			break;
+		}
+	}
+	if (!in_range(bitno, 0, 7, "Bit number ranges from 0-7\n"
+		"Example of <frow_bitno>: \"18_4\" sets bit 4 of row 18\n",
+		cmdtp->usage))
+		return 1;
+	out_be32(&iim->err, in_be32(&iim->err));
+	out_be32(&iim->prg_p, IIM_PRG_P_SET);
+	out_be32(&iim->ua, IIM_SET_UA(bank, f));
+	out_be32(&iim->la, IIM_SET_LA(f, bitno));
+#ifdef DEBUG
+	printf("Programming disabled with DEBUG defined \n");
+	printf(""Set up to pro
+	printf("iim.ua = %x; iim.la = %x\n", iim->ua, iim->la);
+#else
+	out_be32(&iim->fctl, IIM_FCTL_PROG_PULSE | IIM_FCTL_PROG);
+	do
+		udelay(20);
+	while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
+	out_be32(&iim->prg_p, 0);
+	err = in_be32(&iim->err);
+	if (stat & IIM_STAT_PRGD) {
+		if (!(err & (IIM_ERR_WPE | IIM_ERR_WPE))) {
+			printf("Fuse is successfully set");
+			if (err)
+				printf(" - however there are other errors");
+			printf("\n");
+		}
+		iim->stat = 0;
+	}
+	if (err) {
+		iim_err_msg(err);
+		out_be32(&iim->err, in_be32(&iim->err));
+	}
+#endif
+}
+
+int ads5121_fuse_sense(int bank, int fstart, int num)
+{
+	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+	u32 iim_fbac;
+	u32 stat, err, err_hold = 0;
+	int f, ctr;
+
+	out_be32(&iim->err, in_be32(&iim->err));
+	if (bank == 0)
+		iim_fbac = in_be32(&iim->fbac0);
+	else
+		iim_fbac = in_be32(&iim->fbac1);
+	if (iim_fbac & IIM_FBAC_FBESP) {
+		printf("\tSense Protect disallows this operation\n");
+		out_be32(&iim->err, IIM_FBAC_FBESP);
+		return 1;
+	}
+	err = in_be32(&iim->err);
+	if (err) {
+		iim_err_msg(err);
+		err_hold |= err;
+	}
+	if (err & IIM_ERR_RPE)
+		printf("\tRead protect fuse is set; "
+			"Sense Protect may be set but will be attempted\n");
+	if (err)
+		out_be32(&iim->err, err);
+	printf("Sensing fuse(s) on Bank %d\n", bank);
+	for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) {
+		out_be32(&iim->ua, IIM_SET_UA(bank, f));
+		out_be32(&iim->la, IIM_SET_LA(f, 0));
+		out_be32(&iim->fctl,  IIM_FCTL_ESNS_N);
+		do
+			udelay(20);
+		while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
+		err = in_be32(&iim->err);
+		if (err & IIM_ERR_SNSE) {
+			iim_err_msg(err);
+			out_be32(&iim->err, IIM_ERR_SNSE);
+			return 1;
+		}
+		if (stat & IIM_STAT_SNSD) {
+			out_be32(&iim->stat, 0);
+			if (ctr % 4 == 0)
+				printf("F%2d:", f);
+			printf("\t%#04x", (u8)iim->sdat);
+			if (ctr % 4 == 3)
+				printf("\n");
+		}
+		if (err) {
+			err_hold |= err;
+			out_be32(&iim->err, err);
+		}
+	}
+	if (ctr % 4 != 0)
+		printf("\n");
+	if (err_hold)
+		iim_err_msg(err_hold);
+
+	return 0;
+}
+
+int ads5121_fuse_stat(int bank)
+{
+	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
+	u32 iim_fbac;
+	u32 err;
+
+	out_be32(&iim->err, in_be32(&iim->err));
+	if (bank == 0)
+		iim_fbac = in_be32(&iim->fbac0);
+	else
+		iim_fbac = in_be32(&iim->fbac1);
+	err = in_be32(&iim->err);
+	if (err)
+		iim_err_msg(err);
+	if (err & IIM_ERR_RPE  || iim_fbac & IIM_FBAC_FBRP) {
+		if (iim_fbac == 0)
+			printf("Since protection settings can't be read - "
+				"try sensing fuse row 0;\n");
+		return 0;
+	}
+	if (iim_fbac & IIM_PROTECTION)
+		printf("Protection Fuses Bank %d = %#04x:\n", bank, iim_fbac);
+	else if (!(err & IIM_ERR_RPE))
+		printf("No Protection fuses are set\n");
+	if (iim_fbac & IIM_FBAC_FBWP)
+		printf("\tWrite Protect fuse is set\n");
+	if (iim_fbac & IIM_FBAC_FBOP)
+		printf("\tOverride Protect fuse is set\n");
+	if (iim_fbac & IIM_FBAC_FBESP)
+		printf("\tSense Protect Fuse is set\n");
+	out_be32(&iim->err, in_be32(&iim->err));
+
+	return 0;
+}
+
+int do_ads5121_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int frow, n, v, bank;
+
+	if (cur_bank == '0')
+		bank = 0;
+	else
+		bank = 1;
+
+	switch (argc) {
+	case 0:
+	case 1:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 2:
+		if (strncmp(argv[1], "stat", 4) == 0)
+			return ads5121_fuse_stat(bank);
+		if (strncmp(argv[1], "read", 4) == 0)
+			return ads5121_fuse_read(bank, 0, IIM_FMAX + 1);
+		if (strncmp(argv[1], "sense", 5) == 0)
+			return ads5121_fuse_sense(bank, 0, IIM_FMAX + 1);
+		if (strncmp(argv[1], "ovride", 6) == 0)
+			return ads5121_fuse_override(bank, IIM_FMAX + 1, 0);
+		if (strncmp(argv[1], "bank", 4) == 0) {
+			printf("Active Fuse Bank is %c\n", cur_bank);
+			return 0;
+		}
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 3:
+		if (strncmp(argv[1], "bank", 4) == 0) {
+			if (argv[2][0] == '0')
+				cur_bank = '0';
+			else if (argv[2][0] == '1')
+				cur_bank = '1';
+			else {
+				printf("Usage:\n%s\n", cmdtp->usage);
+				return 1;
+			}
+
+			printf("Setting Active Fuse Bank to %c\n", cur_bank);
+			return 0;
+		}
+		if (strncmp(argv[1], "prog", 4) == 0)
+			return ads5121_fuse_prog(cmdtp, bank, argv[2]);
+
+		frow = (int)simple_strtol(argv[2], NULL, 10);
+		if (frow == 0 && argv[2][0] != '0')
+			frow = -1;
+		if (!in_range(frow, 0, IIM_FMAX,
+			"<frow> must be between 0-31\n\n", cmdtp->usage))
+			return 1;
+		if (strncmp(argv[1], "read", 4) == 0)
+			return ads5121_fuse_read(bank, frow, 1);
+		if (strncmp(argv[1], "ovride", 6) == 0)
+			return ads5121_fuse_override(bank, frow, 0);
+		if (strncmp(argv[1], "sense", 5) == 0)
+			return ads5121_fuse_sense(bank, frow, 1);
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 4:
+		frow = (int)simple_strtol(argv[2], NULL, 10);
+		if (frow == 0 && argv[2][0] != '0')
+			frow = -1;
+		if (!in_range(frow, 0, IIM_FMAX,
+			"<frow> must be between 0-31\n\n", cmdtp->usage))
+			return 1;
+		if (strncmp(argv[1], "read", 4) == 0) {
+			n = (int)simple_strtol(argv[3], NULL, 10);
+			if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
+				"<frow>+<n> must be between 1-32\n\n",
+				cmdtp->usage))
+				return 1;
+			return ads5121_fuse_read(bank, frow, n);
+		}
+		if (strncmp(argv[1], "ovride", 6) == 0) {
+			v = (int)simple_strtol(argv[3], NULL, 10);
+			return ads5121_fuse_override(bank, frow, v);
+		}
+		if (strncmp(argv[1], "sense", 5) == 0) {
+			n = (int)simple_strtol(argv[3], NULL, 10);
+			if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
+				"<frow>+<n> must be between 1-32\n\n",
+				cmdtp->usage))
+				return 1;
+			return ads5121_fuse_sense(bank, frow, n);
+		}
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	default: /* at least 5 args */
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+}
+
+U_BOOT_CMD(
+	fuse, CONFIG_SYS_MAXARGS, 0, do_ads5121_fuse,
+	"   - Read, Sense, Override or Program Fuses\n",
+	"bank <n>		- sets active Fuse Bank to 0 or 1\n"
+	"			    no args shows current active bank\n"
+	"fuse stat		- print active fuse bank's protection status\n"
+	"fuse read [<frow> [<n>]] - print <n> fuse rows starting at <frow>\n"
+	"			    no args to print entire bank's fuses\n"
+	"fuse ovride [<frow> [<v>]]- override fuses at <frow> with <v>\n"
+	"			    no <v> defaults to 0 for the row\n"
+	"			    no args resets entire bank to 0\n"
+	"			  NOTE - settings persist until hard reset\n"
+	"fuse sense [<frow>]	- senses current fuse at <frow>\n"
+	"			    no args for entire bank\n"
+	"fuse prog <frow_bit> 	- program fuse at row <frow>, bit <_bit>\n"
+	"			    <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n"
+	"			  WARNING - this is permanent\n"
+	);
+#endif /* CONFIG_CMD_FUSE */
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index a3251abf58..225738a073 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -93,7 +93,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 		       CONFIG_PCI_MEMORY_BUS,
 		       CONFIG_PCI_MEMORY_PHYS,
 		       CONFIG_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c
index a78a82850c..7ef43b72cd 100644
--- a/cpu/mpc8220/pci.c
+++ b/cpu/mpc8220/pci.c
@@ -165,7 +165,7 @@ pci_mpc8220_init(struct pci_controller *hose)
 		CONFIG_PCI_SYS_MEM_BUS,
 		CONFIG_PCI_SYS_MEM_PHYS,
 		CONFIG_PCI_SYS_MEM_SIZE,
-		PCI_REGION_MEM | PCI_REGION_MEMORY);
+		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	hose->region_count = 3;
 
diff --git a/cpu/mpc824x/pci.c b/cpu/mpc824x/pci.c
index 7e3c4c3b78..cf9cf41ae5 100644
--- a/cpu/mpc824x/pci.c
+++ b/cpu/mpc824x/pci.c
@@ -34,7 +34,7 @@ void pci_mpc824x_init (struct pci_controller *hose)
 		       CHRP_PCI_MEMORY_BUS,
 		       CHRP_PCI_MEMORY_PHYS,
 		       CHRP_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index 378d6c573a..f1e9bb4b9f 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -410,12 +410,12 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	pci_set_region (hose->regions + 0,
 			PCI_SLV_MEM_BUS,
 			PCI_SLV_MEM_LOCAL,
-			gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+			gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 #else
 	pci_set_region (hose->regions + 0,
 			CONFIG_SYS_SDRAM_BASE,
 			CONFIG_SYS_SDRAM_BASE,
-			0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
+			0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 #endif
 
 	/* PCI memory space */
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index e9965d7df3..5fe89646c0 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -89,7 +89,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
 	hose->regions[i].bus_start = 0;
 	hose->regions[i].phys_start = 0;
 	hose->regions[i].size = gd->ram_size;
-	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
diff --git a/cpu/mpc83xx/pcie.c b/cpu/mpc83xx/pcie.c
index 02150bafdc..12b5f69ced 100644
--- a/cpu/mpc83xx/pcie.c
+++ b/cpu/mpc83xx/pcie.c
@@ -109,13 +109,13 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 	hose->regions[i].bus_start = 0;
 	hose->regions[i].phys_start = 0;
 	hose->regions[i].size = gd->ram_size;
-	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 
 	i = hose->region_count++;
 	hose->regions[i].bus_start = CONFIG_SYS_IMMR;
 	hose->regions[i].phys_start = CONFIG_SYS_IMMR;
 	hose->regions[i].size = 0x100000;
-	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 
 	hose->first_busno = max_bus;
 	hose->last_busno = 0xff;
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index e8871fc459..6fd36dea35 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -179,7 +179,7 @@ void pci_405gp_init(struct pci_controller *hose)
 				       ptmpcila[i], ptmla[i],
 				       ~(ptmms[i] & 0xfffff000) + 1,
 				       PCI_REGION_MEM |
-				       PCI_REGION_MEMORY);
+				       PCI_REGION_SYS_MEMORY);
 		}
 
 	/* PCI memory spaces */
@@ -504,7 +504,7 @@ int pci_440_init (struct pci_controller *hose)
 		       CONFIG_PCI_SYS_MEM_BUS,
 		       CONFIG_PCI_SYS_MEM_PHYS,
 		       CONFIG_PCI_SYS_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY );
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
 #endif
 
 	hose->region_count = reg_num;
@@ -588,8 +588,9 @@ void pci_init_board(void)
 	int busno;
 
 	busno = pci_440_init (&ppc440_hose);
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if (defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
+    !defined(CONFIG_PCI_DISABLE_PCIE)
 	pcie_setup_hoses(busno + 1);
 #endif
 }
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index fd40d8abda..58d96bb5af 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -33,7 +33,7 @@
 
 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) ||	\
     defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
-    defined(CONFIG_PCI)
+    defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
 
 #include <asm/4xx_pcie.h>
 
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index c55e1cfbb7..ba5c120ad7 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -113,6 +113,7 @@ void fdt_pcie_setup(void *blob)
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	sys_info_t sys_info;
+	int off, ndepth = 0;
 
 	get_sys_info(&sys_info);
 
@@ -133,9 +134,28 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
 	/*
-	 * Setup all baudrates for the UARTs
+	 * Fixup all UART clocks for CPU internal UARTs
+	 * (only these UARTs are definitely clocked by gd->uart_clk)
+	 *
+	 * These UARTs are direct childs of /plb/opb. This code
+	 * does not touch any UARTs that are connected to the ebc.
 	 */
-	do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1);
+	off = fdt_path_offset(blob, "/plb/opb");
+	while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
+		/*
+		 * process all sub nodes and stop when we are back
+		 * at the starting depth
+		 */
+		if (ndepth <= 0)
+			break;
+
+		/* only update direct childs */
+		if ((ndepth == 1) &&
+		    (fdt_node_check_compatible(blob, off, "ns16550") == 0))
+			fdt_setprop(blob, off,
+				    "clock-frequency",
+				    (void*)&(gd->uart_clk), 4);
+	}
 
 	/*
 	 * Fixup all ethernet nodes
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index bfb1f9f3b5..04a9a92586 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -305,17 +305,12 @@ flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
 {
 	unsigned int byte_offset = offset * info->portwidth;
 
-	return map_physmem(info->start[sect] + byte_offset,
-			flash_sector_size(info, sect) - byte_offset,
-			MAP_NOCACHE);
+	return (void *)(info->start[sect] + byte_offset);
 }
 
 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
 		unsigned int offset, void *addr)
 {
-	unsigned int byte_offset = offset * info->portwidth;
-
-	unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset);
 }
 
 /*-----------------------------------------------------------------------
@@ -802,13 +797,11 @@ static flash_sect_t find_sector (flash_info_t * info, ulong addr)
 static int flash_write_cfiword (flash_info_t * info, ulong dest,
 				cfiword_t cword)
 {
-	void *dstaddr;
+	void *dstaddr = (void *)dest;
 	int flag;
 	flash_sect_t sect = 0;
 	char sect_found = 0;
 
-	dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE);
-
 	/* Check if Flash is (sufficiently) erased */
 	switch (info->portwidth) {
 	case FLASH_CFI_8BIT:
@@ -827,10 +820,8 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
 		flag = 0;
 		break;
 	}
-	if (!flag) {
-		unmap_physmem(dstaddr, info->portwidth);
+	if (!flag)
 		return ERR_NOT_ERASED;
-	}
 
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
@@ -873,8 +864,6 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
 	if (flag)
 		enable_interrupts ();
 
-	unmap_physmem(dstaddr, info->portwidth);
-
 	if (!sect_found)
 		sect = find_sector (info, dest);
 
@@ -890,7 +879,7 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 	int cnt;
 	int retcode;
 	void *src = cp;
-	void *dst = map_physmem(dest, len, MAP_NOCACHE);
+	void *dst = (void *)dest;
 	void *dst2 = dst;
 	int flag = 0;
 	uint offset = 0;
@@ -1052,7 +1041,6 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 	}
 
 out_unmap:
-	unmap_physmem(dst, len);
 	return retcode;
 }
 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
@@ -1301,7 +1289,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	/* handle unaligned start */
 	if ((aln = addr - wp) != 0) {
 		cword.l = 0;
-		p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
+		p = (uchar *)wp;
 		for (i = 0; i < aln; ++i)
 			flash_add_byte (info, &cword, flash_read8(p + i));
 
@@ -1313,7 +1301,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 			flash_add_byte (info, &cword, flash_read8(p + i));
 
 		rc = flash_write_cfiword (info, wp, cword);
-		unmap_physmem(p, info->portwidth);
 		if (rc != 0)
 			return rc;
 
@@ -1372,14 +1359,13 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	cword.l = 0;
-	p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
+	p = (uchar *)wp;
 	for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
 		flash_add_byte (info, &cword, *src++);
 		--cnt;
 	}
 	for (; i < info->portwidth; ++i)
 		flash_add_byte (info, &cword, flash_read8(p + i));
-	unmap_physmem(p, info->portwidth);
 
 	return flash_write_cfiword (info, wp, cword);
 }
@@ -1618,7 +1604,7 @@ static void flash_read_jedec_ids (flash_info_t * info)
  * board_flash_get_legacy needs to fill in at least:
  * info->portwidth, info->chipwidth and info->interface for Jedec probing.
  */
-static int flash_detect_legacy(ulong base, int banknum)
+static int flash_detect_legacy(phys_addr_t base, int banknum)
 {
 	flash_info_t *info = &flash_info[banknum];
 
@@ -1634,7 +1620,10 @@ static int flash_detect_legacy(ulong base, int banknum)
 
 			for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
 				info->vendor = modes[i];
-				info->start[0] = base;
+				info->start[0] =
+					(ulong)map_physmem(base,
+							   info->portwidth,
+							   MAP_NOCACHE);
 				if (info->portwidth == FLASH_CFI_8BIT
 					&& info->interface == FLASH_CFI_X8X16) {
 					info->addr_unlock1 = 0x2AAA;
@@ -1648,8 +1637,11 @@ static int flash_detect_legacy(ulong base, int banknum)
 						info->manufacturer_id,
 						info->device_id,
 						info->device_id2);
-				if (jedec_flash_match(info, base))
+				if (jedec_flash_match(info, info->start[0]))
 					break;
+				else
+					unmap_physmem((void *)info->start[0],
+						      MAP_NOCACHE);
 			}
 		}
 
@@ -1671,7 +1663,7 @@ static int flash_detect_legacy(ulong base, int banknum)
 	return 0; /* use CFI */
 }
 #else
-static inline int flash_detect_legacy(ulong base, int banknum)
+static inline int flash_detect_legacy(phys_addr_t base, int banknum)
 {
 	return 0; /* use CFI */
 }
@@ -1826,12 +1818,12 @@ static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
  * The following code cannot be run from FLASH!
  *
  */
-ulong flash_get_size (ulong base, int banknum)
+ulong flash_get_size (phys_addr_t base, int banknum)
 {
 	flash_info_t *info = &flash_info[banknum];
 	int i, j;
 	flash_sect_t sect_cnt;
-	unsigned long sector;
+	phys_addr_t sector;
 	unsigned long tmp;
 	int size_ratio;
 	uchar num_erase_regions;
@@ -1847,7 +1839,7 @@ ulong flash_get_size (ulong base, int banknum)
 	info->legacy_unlock = 0;
 #endif
 
-	info->start[0] = base;
+	info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
 
 	if (flash_detect_cfi (info, &qry)) {
 		info->vendor = le16_to_cpu(qry.p_id);
@@ -1939,7 +1931,10 @@ ulong flash_get_size (ulong base, int banknum)
 					printf("ERROR: too many flash sectors\n");
 					break;
 				}
-				info->start[sect_cnt] = sector;
+				info->start[sect_cnt] =
+					(ulong)map_physmem(sector,
+							   info->portwidth,
+							   MAP_NOCACHE);
 				sector += (erase_region_size * size_ratio);
 
 				/*
@@ -2016,7 +2011,7 @@ unsigned long flash_init (void)
 	char *s = getenv("unlock");
 #endif
 
-#define BANK_BASE(i)	(((unsigned long [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i])
+#define BANK_BASE(i)	(((phys_addr_t [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i])
 
 	/* Init: no FLASHes known */
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c
index 2d99d4d9a3..e48aceceae 100644
--- a/drivers/mtd/jedec_flash.c
+++ b/drivers/mtd/jedec_flash.c
@@ -37,10 +37,6 @@
 
 #define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
 
-/* Manufacturers */
-#define MANUFACTURER_AMD	0x0001
-#define MANUFACTURER_SST	0x00BF
-
 /* AMD */
 #define AM29DL800BB	0x22CB
 #define AM29DL800BT	0x224A
@@ -172,7 +168,7 @@ struct amd_flash_info {
 static const struct amd_flash_info jedec_table[] = {
 #ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
 	{
-		.mfr_id		= MANUFACTURER_SST,
+		.mfr_id		= (u16)SST_MANUFACT,
 		.dev_id		= SST39LF020,
 		.name		= "SST 39LF020",
 		.uaddr		= {
@@ -188,7 +184,7 @@ static const struct amd_flash_info jedec_table[] = {
 #endif
 #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
 	{
-		.mfr_id		= MANUFACTURER_AMD,
+		.mfr_id		= (u16)AMD_MANUFACT,
 		.dev_id		= AM29LV040B,
 		.name		= "AMD AM29LV040B",
 		.uaddr		= {
@@ -202,7 +198,7 @@ static const struct amd_flash_info jedec_table[] = {
 		}
 	},
 	{
-		.mfr_id		= MANUFACTURER_SST,
+		.mfr_id		= (u16)SST_MANUFACT,
 		.dev_id		= SST39LF040,
 		.name		= "SST 39LF040",
 		.uaddr		= {
@@ -216,7 +212,7 @@ static const struct amd_flash_info jedec_table[] = {
 		}
 	},
 	{
-		.mfr_id		= STM_MANUFACT,
+		.mfr_id		= (u16)STM_MANUFACT,
 		.dev_id		= STM_ID_M29W040B,
 		.name		= "ST Micro M29W040B",
 		.uaddr		= {
@@ -232,7 +228,7 @@ static const struct amd_flash_info jedec_table[] = {
 #endif
 #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
 	{
-		.mfr_id		= MANUFACTURER_AMD,
+		.mfr_id		= (u16)AMD_MANUFACT,
 		.dev_id		= AM29LV400BB,
 		.name		= "AMD AM29LV400BB",
 		.uaddr		= {
@@ -249,7 +245,7 @@ static const struct amd_flash_info jedec_table[] = {
 		}
 	},
 	{
-		.mfr_id		= MANUFACTURER_AMD,
+		.mfr_id		= (u16)AMD_MANUFACT,
 		.dev_id		= AM29LV800BB,
 		.name		= "AMD AM29LV800BB",
 		.uaddr		= {
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index cf9261786d..70b605f9d2 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -28,6 +28,8 @@
 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int nand_curr_device = -1;
 nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
 
@@ -46,6 +48,8 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
 		if (nand_scan(mtd, 1) == 0) {
 			if (!mtd->name)
 				mtd->name = (char *)default_nand_name;
+			else
+				mtd->name += gd->reloc_off;
 		} else
 			mtd->name = NULL;
 	} else {
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ef37f97b33..d33fee242f 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -75,6 +75,17 @@
 #include <jffs2/jffs2.h>
 #endif
 
+/*
+ * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
+ * a flash.  NAND flash is initialized prior to interrupts so standard timers
+ * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
+ * which is greater than (max NAND reset time / NAND status read time).
+ * A conservative default of 200000 (500 us / 25 ns) is used as a default.
+ */
+#ifndef CONFIG_SYS_NAND_RESET_CNT
+#define CONFIG_SYS_NAND_RESET_CNT 200000
+#endif
+
 /* Define default oob placement schemes for large and small page devices */
 static struct nand_ecclayout nand_oob_8 = {
 	.eccbytes = 3,
@@ -524,6 +535,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 {
 	register struct nand_chip *chip = mtd->priv;
 	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
+	uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 
 	/*
 	 * Write out the command to the device.
@@ -590,7 +602,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 			       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 		chip->cmd_ctrl(mtd,
 			       NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-		while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
+		while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
+			(rst_sts_cnt--));
 		return;
 
 		/* This applies to read commands */
@@ -626,6 +639,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 			    int column, int page_addr)
 {
 	register struct nand_chip *chip = mtd->priv;
+	uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 
 	/* Emulate NAND_CMD_READOOB */
 	if (command == NAND_CMD_READOOB) {
@@ -696,7 +710,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 			       NAND_NCE | NAND_CTRL_CHANGE);
-		while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
+		while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
+			(rst_sts_cnt--));
 		return;
 
 	case NAND_CMD_RNDOUT:
@@ -2618,7 +2633,9 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips)
 	type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
 
 	if (IS_ERR(type)) {
+#ifndef CONFIG_SYS_NAND_QUIET_TEST
 		printk(KERN_WARNING "No NAND device found!!!\n");
+#endif
 		chip->select_chip(mtd, -1);
 		return PTR_ERR(type);
 	}
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 2b733c66e3..4f1c0a0127 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -226,7 +226,8 @@ void __mii_init(void)
 	volatile FEC_T *fecp;
 	struct eth_device *dev;
 	int miispd = 0, i = 0;
-	u16 autoneg = 0;
+	u16 status = 0;
+	u16 linkgood = 0;
 
 	/* retrieve from register structure */
 	dev = eth_get_dev();
@@ -250,22 +251,32 @@ void __mii_init(void)
 
 	info->phy_addr = mii_discover_phy(dev);
 
-#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
 	while (i < MCFFEC_TOUT_LOOP) {
-		autoneg = 0;
-		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+		status = 0;
 		i++;
-
-		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+		/* Read PHY control register */
+		miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &status);
+
+		/* If phy set to autonegotiate, wait for autonegotiation done,
+		 * if phy is not autonegotiating, just wait for link up.
+		 */
+		if ((status & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
+			linkgood = (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS);
+		} else {
+			linkgood = PHY_BMSR_LS;
+		}
+		/* Read PHY status register */
+		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &status);
+		if ((status & linkgood) == linkgood)
 			break;
 
 		udelay(500);
 	}
 	if (i >= MCFFEC_TOUT_LOOP) {
-		printf("Auto Negotiation not complete\n");
+		printf("Link UP timeout\n");
 	}
 
-	/* adapt to the half/full speed settings */
+	/* adapt to the duplex and speed settings of the phy */
 	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
 	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
 }
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index db68f26009..20b2dcc767 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -72,7 +72,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
 	debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
 		(u64)bus_start, (u64)phys_start, (u64)pci_sz);
 	pci_set_region(r++, bus_start, phys_start, pci_sz,
-			PCI_REGION_MEM | PCI_REGION_MEMORY |
+			PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 			PCI_REGION_PREFETCH);
 
 	sz -= pci_sz;
@@ -84,7 +84,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
 		debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
 			(u64)bus_start, (u64)phys_start, (u64)pci_sz);
 		pci_set_region(r++, bus_start, phys_start, pci_sz,
-				PCI_REGION_MEM | PCI_REGION_MEMORY |
+				PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 				PCI_REGION_PREFETCH);
 		sz -= pci_sz;
 		bus_start += pci_sz;
@@ -108,7 +108,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
 			CONFIG_SYS_PCI64_MEMORY_BUS,
 			CONFIG_SYS_PCI_MEMORY_PHYS,
 			pci_sz,
-			PCI_REGION_MEM | PCI_REGION_MEMORY |
+			PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 			PCI_REGION_PREFETCH);
 #else
 	pci_sz = 1ull << __ilog2_u64(sz);
@@ -116,7 +116,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
 		debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
 			(u64)bus_start, (u64)phys_start, (u64)pci_sz);
 		pci_set_region(r++, bus_start, phys_start, pci_sz,
-				PCI_REGION_MEM | PCI_REGION_MEMORY |
+				PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 				PCI_REGION_PREFETCH);
 		sz -= pci_sz;
 		bus_start += pci_sz;
@@ -157,7 +157,7 @@ void fsl_pci_init(struct pci_controller *hose)
 
 	for (r=0; r<hose->region_count; r++) {
 		u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
-		if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
+		if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
 			u32 flag = PIWAR_EN | PIWAR_LOCAL |
 					PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
 			pi->pitar = (hose->regions[r].phys_start >> 12);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e2b05d8991..06b56b05f7 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -218,67 +218,121 @@ pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
  *
  */
 
-pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
-				    phys_addr_t phys_addr,
-				    unsigned long flags)
+int __pci_hose_phys_to_bus (struct pci_controller *hose,
+				phys_addr_t phys_addr,
+				unsigned long flags,
+				unsigned long skip_mask,
+				pci_addr_t *ba)
 {
 	struct pci_region *res;
 	pci_addr_t bus_addr;
 	int i;
 
-	if (!hose) {
-		printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
-		goto Done;
-	}
-
 	for (i = 0; i < hose->region_count; i++) {
 		res = &hose->regions[i];
 
 		if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 			continue;
 
+		if (res->flags & skip_mask)
+			continue;
+
 		bus_addr = phys_addr - res->phys_start + res->bus_start;
 
 		if (bus_addr >= res->bus_start &&
 			bus_addr < res->bus_start + res->size) {
-			return bus_addr;
+			*ba = bus_addr;
+			return 0;
 		}
 	}
 
-	printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
-
-Done:
-	return 0;
+	return 1;
 }
 
-phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
-				 pci_addr_t bus_addr,
-				 unsigned long flags)
+pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
+				    phys_addr_t phys_addr,
+				    unsigned long flags)
 {
-	struct pci_region *res;
-	int i;
+	pci_addr_t bus_addr = 0;
+	int ret;
 
 	if (!hose) {
-		printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
-		goto Done;
+		puts ("pci_hose_phys_to_bus: invalid hose\n");
+		return bus_addr;
+	}
+
+	/* if PCI_REGION_MEM is set we do a two pass search with preference
+	 * on matches that don't have PCI_REGION_SYS_MEMORY set */
+	if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
+		ret = __pci_hose_phys_to_bus(hose, phys_addr,
+				flags, PCI_REGION_SYS_MEMORY, &bus_addr);
+		if (!ret)
+			return bus_addr;
 	}
 
+	ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
+
+	if (ret)
+		puts ("pci_hose_phys_to_bus: invalid physical address\n");
+
+	return bus_addr;
+}
+
+int __pci_hose_bus_to_phys (struct pci_controller *hose,
+				pci_addr_t bus_addr,
+				unsigned long flags,
+				unsigned long skip_mask,
+				phys_addr_t *pa)
+{
+	struct pci_region *res;
+	int i;
+
 	for (i = 0; i < hose->region_count; i++) {
 		res = &hose->regions[i];
 
 		if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 			continue;
 
+		if (res->flags & skip_mask)
+			continue;
+
 		if (bus_addr >= res->bus_start &&
 			bus_addr < res->bus_start + res->size) {
-			return bus_addr - res->bus_start + res->phys_start;
+			*pa = (bus_addr - res->bus_start + res->phys_start);
+			return 0;
 		}
 	}
 
-	printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
+	return 1;
+}
 
-Done:
-	return 0;
+phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
+				 pci_addr_t bus_addr,
+				 unsigned long flags)
+{
+	phys_addr_t phys_addr = 0;
+	int ret;
+
+	if (!hose) {
+		puts ("pci_hose_bus_to_phys: invalid hose\n");
+		return phys_addr;
+	}
+
+	/* if PCI_REGION_MEM is set we do a two pass search with preference
+	 * on matches that don't have PCI_REGION_SYS_MEMORY set */
+	if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
+		ret = __pci_hose_bus_to_phys(hose, bus_addr,
+				flags, PCI_REGION_SYS_MEMORY, &phys_addr);
+		if (!ret)
+			return phys_addr;
+	}
+
+	ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
+
+	if (ret)
+		puts ("pci_hose_bus_to_phys: invalid physical address\n");
+
+	return phys_addr;
 }
 
 /*
diff --git a/drivers/pci/pci_ixp.c b/drivers/pci/pci_ixp.c
index aae3d3d2c1..3b303b4523 100644
--- a/drivers/pci/pci_ixp.c
+++ b/drivers/pci/pci_ixp.c
@@ -240,7 +240,7 @@ void pci_ixp_init (struct pci_controller *hose)
 	/* System memory space */
 	pci_set_region (hose->regions + 0,
 			PCI_MEMORY_BUS,
-			PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY);
+			PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region (hose->regions + 1,
diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c
index d153fc6beb..627e8a0792 100644
--- a/drivers/pci/tsi108_pci.c
+++ b/drivers/pci/tsi108_pci.c
@@ -131,7 +131,7 @@ void pci_init_board (void)
 	pci_set_region (hose->regions + 0,
 		       CONFIG_SYS_PCI_MEMORY_BUS,
 		       CONFIG_SYS_PCI_MEMORY_PHYS,
-		       CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region (hose->regions + 1,
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index e04fc298d9..0b531402e4 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -115,8 +115,9 @@ void serial_setbrg(void)
 	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
 	u32 counter;
 
-	counter = ((gd->bus_clk / gd->baudrate)) >> 5;
-	counter++;
+	/* Setting up BaudRate */
+	counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
+	counter = counter / gd->baudrate;
 
 	/* write to CTUR: divide counter upper byte */
 	uart->ubg1 = ((counter & 0xff00) >> 8);
diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/blackfin-config-pre.h
index a1fae5c9a7..9df01ad25a 100644
--- a/include/asm-blackfin/blackfin-config-pre.h
+++ b/include/asm-blackfin/blackfin-config-pre.h
@@ -60,4 +60,13 @@ static inline const char *get_bfin_boot_mode(int bfin_boot)
 }
 #endif
 
+/* Define the default SPI CS used when booting out of SPI */
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
+    defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
+    defined(__ADSPBF51x__)
+# define BFIN_BOOT_SPI_SSEL 2
+#else
+# define BFIN_BOOT_SPI_SSEL 1
+#endif
+
 #endif
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
index 7c5127ecad..035e8d8350 100644
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -7,82 +7,154 @@
  */
 
 /* This file shoule be up to date with:
- *  - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
+ *  - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
+ *  - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
 
+#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
+# define ANOMALY_BF526 1
+#else
+# define ANOMALY_BF526 0
+#endif
+#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
+# define ANOMALY_BF527 1
+#else
+# define ANOMALY_BF527 0
+#endif
+
 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
 #define ANOMALY_05000074 (1)
 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
+#define ANOMALY_05000119 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
 #define ANOMALY_05000265 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (1)
+#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (1)
+#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (1)
+#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (1)
+#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (1)
+#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0xE510
 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (1)
+#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Security Features Are Not Functional */
-#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
+#define ANOMALY_05000353 (ANOMALY_BF526)
 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
+#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
+#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
+#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
 #define ANOMALY_05000366 (1)
-/* New Feature: Higher Default CCLK Rate */
-#define ANOMALY_05000368 (1)
+/* Incorrect Default CSEL Value in PLL_DIV */
+#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
+#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
+#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (1)
-/* USB Full-speed Mode not Fully Tested */
-#define ANOMALY_05000381 (1)
-/* New Feature: Boot from OTP Memory */
-#define ANOMALY_05000385 (1)
-/* New Feature: bfrom_SysControl() Routine */
-#define ANOMALY_05000386 (1)
-/* New Feature: Programmable Preboot Settings */
-#define ANOMALY_05000387 (1)
+#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
+/* Host Must Not Read Back During Host DMA Boot */
+#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
 /* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (1)
-/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (1)
-/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (1)
-/* New Feature: Log Buffer Functionality */
-#define ANOMALY_05000394 (1)
-/* New Feature: Hook Routine Functionality */
-#define ANOMALY_05000395 (1)
-/* New Feature: Header Indirect Bit */
-#define ANOMALY_05000396 (1)
-/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
-#define ANOMALY_05000397 (1)
-/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
-#define ANOMALY_05000398 (1)
-/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
-#define ANOMALY_05000399 (1)
+#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
+#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
+#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (1)
+#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Disallows Certain User Interrupts */
+#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
+#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Lockbox firmware leaves MDMA0 channel enabled */
+#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
+/* Incorrect Default Internal Voltage Regulator Setting */
+#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
+#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
+/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
+#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+/* DEB2_URGENT Bit Not Functional */
+#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
+#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
+#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
+/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
+#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
+/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
+#define ANOMALY_05000421 (1)
+/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
+#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
+#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
+/* Internal Voltage Regulator Not Trimmed */
+#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
+#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
+#define ANOMALY_05000432 (ANOMALY_BF526)
+/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
+#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -95,10 +167,12 @@
 #define ANOMALY_05000263 (0)
 #define ANOMALY_05000266 (0)
 #define ANOMALY_05000273 (0)
+#define ANOMALY_05000285 (0)
 #define ANOMALY_05000307 (0)
 #define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
 #define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
 #define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index 7c34c38136..0d3a03429f 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,7 +7,7 @@
  */
 
 /* This file shoule be up to date with:
- *  - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ *  - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -97,11 +97,11 @@
 /* UART STB Bit Incorrectly Affects Receiver Setting */
 #define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
 /* Incorrect Revision Number in DSPID Register */
 #define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
 /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
 #define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -131,7 +131,7 @@
 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
 #define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
+#define ANOMALY_05000265 (1)
 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
 #define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
@@ -141,23 +141,23 @@
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
 #define ANOMALY_05000272 (1)
 /* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (1)
+#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
 #define ANOMALY_05000276 (1)
 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (1)
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (1)
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
 /* False Hardware Error Exception When ISR Context Is Not Restored */
-#define ANOMALY_05000281 (1)
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (1)
+#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
 /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
+#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
 /* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (1)
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
+#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
 /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
 #define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
 /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
@@ -169,30 +169,37 @@
 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
 #define ANOMALY_05000310 (1)
 /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (1)
+#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
 /* PPI Is Level-Sensitive on First Transfer */
-#define ANOMALY_05000313 (1)
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
 /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (1)
+#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
 /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
+#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
+#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
 /* UART Break Signal Issues */
 #define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
 #define ANOMALY_05000366 (1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
 /* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
+#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
-
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* These anomalies have been "phased" out of analog.com anomaly sheets and are
  * here to show running on older silicon just isn't feasible.
@@ -271,5 +278,9 @@
 #define ANOMALY_05000266 (0)
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000353 (1)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 8d7f305793..9cb39121d1 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,7 +7,7 @@
  */
 
 /* This file shoule be up to date with:
- *  - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -148,6 +148,14 @@
 #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -160,5 +168,9 @@
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000353 (1)
 #define ANOMALY_05000363 (0)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index 1dc75ef1ae..3b5430999f 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -7,7 +7,7 @@
  */
 
 /* This file shoule be up to date with:
- *  - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ *  - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -36,7 +36,7 @@
 /* TWI Slave Boot Mode Is Not Functional */
 #define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
 /* External FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
 /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
 #define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
@@ -61,6 +61,8 @@
 #define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
 /* USB Calibration Value Is Not Intialized */
 #define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0x5411
 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */
 #define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
 /* Data Lost when Core Reads SDH Data FIFO */
@@ -68,7 +70,7 @@
 /* PLL Status Register Is Inaccurate */
 #define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (1)
+#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
 #define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
 /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
@@ -86,13 +88,13 @@
 /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
 #define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
 /* USB DP/DM Data Pins May Lose State When Entering Hibernate */
 #define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
 /* Mobile DDR Operation Not Functional */
 #define ANOMALY_05000377 (1)
 /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (1)
+#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
 /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
 #define ANOMALY_05000379 (1)
 /* 8-Bit NAND Flash Boot Mode Not Functional */
@@ -126,25 +128,37 @@
 /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
 #define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
 /* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (1)
+#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
 #define ANOMALY_05000405 (1)
 /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
-#define ANOMALY_05000406 (1)
+#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
 /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (1)
+#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
 #define ANOMALY_05000408 (1)
 /* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (1)
+#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
 /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (1)
-/* FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000412 (1)
+#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
 /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
-#define ANOMALY_05000413 (1)
+#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
 /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (1)
+#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
+#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
+#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -161,5 +175,8 @@
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index e9c4ca8783..1a9e175628 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
  */
 
 /* This file shoule be up to date with:
- *  - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
+ *  - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -264,6 +264,18 @@
 #define ANOMALY_05000371 (1)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
+/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
+#define ANOMALY_05000412 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
+#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000158 (0)
@@ -271,5 +283,8 @@
 #define ANOMALY_05000273 (0)
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000353 (1)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h
index 7877616894..d25261bcd1 100644
--- a/include/asm-m68k/m5271.h
+++ b/include/asm-m68k/m5271.h
@@ -37,8 +37,27 @@
 
 #define MCF_FMPLL_SYNCR				0x120000
 #define MCF_FMPLL_SYNSR				0x120004
+
 #define MCF_FMPLL_SYNCR_MFD(x)			((x&0x7)<<24)
+#define MCF_SYNCR_MFD_4X		0x00000000
+#define MCF_SYNCR_MFD_6X		0x01000000
+#define MCF_SYNCR_MFD_8X		0x02000000
+#define MCF_SYNCR_MFD_10X		0x03000000
+#define MCF_SYNCR_MFD_12X		0x04000000
+#define MCF_SYNCR_MFD_14X		0x05000000
+#define MCF_SYNCR_MFD_16X		0x06000000
+#define MCF_SYNCR_MFD_18X		0x07000000
+
 #define MCF_FMPLL_SYNCR_RFD(x)			((x&0x7)<<19)
+#define MCF_SYNCR_RFD_DIV1		0x00000000
+#define MCF_SYNCR_RFD_DIV2		0x00080000
+#define MCF_SYNCR_RFD_DIV4		0x00100000
+#define MCF_SYNCR_RFD_DIV8		0x00180000
+#define MCF_SYNCR_RFD_DIV16		0x00200000
+#define MCF_SYNCR_RFD_DIV32		0x00280000
+#define MCF_SYNCR_RFD_DIV64		0x00300000
+#define MCF_SYNCR_RFD_DIV128		0x00380000
+
 #define MCF_FMPLL_SYNSR_LOCK			0x8
 
 #define MCF_WTM_WCR				0x140000
@@ -50,17 +69,79 @@
 #define MCF_RCM_RCR_FRCRSTOUT			0x40
 #define MCF_RCM_RCR_SOFTRST			0x80
 
+#define MCF_GPIO_PODR_ADDR			0x100000
+#define MCF_GPIO_PODR_DATAH			0x100001
+#define MCF_GPIO_PODR_DATAL			0x100002
+#define MCF_GPIO_PODR_BUSCTL			0x100003
+#define MCF_GPIO_PODR_BS			0x100004
+#define MCF_GPIO_PODR_CS			0x100005
+#define MCF_GPIO_PODR_SDRAM			0x100006
+#define MCF_GPIO_PODR_FECI2C			0x100007
+#define MCF_GPIO_PODR_UARTH			0x100008
+#define MCF_GPIO_PODR_UARTL			0x100009
+#define MCF_GPIO_PODR_QSPI			0x10000A
+#define MCF_GPIO_PODR_TIMER			0x10000B
+
+#define MCF_GPIO_PDDR_ADDR			0x100010
+#define MCF_GPIO_PDDR_DATAH			0x100011
+#define MCF_GPIO_PDDR_DATAL			0x100012
+#define MCF_GPIO_PDDR_BUSCTL			0x100013
+#define MCF_GPIO_PDDR_BS			0x100014
+#define MCF_GPIO_PDDR_CS			0x100015
+#define MCF_GPIO_PDDR_SDRAM			0x100016
+#define MCF_GPIO_PDDR_FECI2C			0x100017
+#define MCF_GPIO_PDDR_UARTH			0x100018
+#define MCF_GPIO_PDDR_UARTL			0x100019
+#define MCF_GPIO_PDDR_QSPI			0x10001A
+#define MCF_GPIO_PDDR_TIMER			0x10001B
+
+#define MCF_GPIO_PPDSDR_ADDR			0x100020
+#define MCF_GPIO_PPDSDR_DATAH			0x100021
+#define MCF_GPIO_PPDSDR_DATAL			0x100022
+#define MCF_GPIO_PPDSDR_BUSCTL			0x100023
+#define MCF_GPIO_PPDSDR_BS			0x100024
+#define MCF_GPIO_PPDSDR_CS			0x100025
+#define MCF_GPIO_PPDSDR_SDRAM			0x100026
+#define MCF_GPIO_PPDSDR_FECI2C			0x100027
+#define MCF_GPIO_PPDSDR_UARTH			0x100028
+#define MCF_GPIO_PPDSDR_UARTL			0x100029
+#define MCF_GPIO_PPDSDR_QSPI			0x10002A
+#define MCF_GPIO_PPDSDR_TIMER			0x10002B
+
+#define MCF_GPIO_PCLRR_ADDR			0x100030
+#define MCF_GPIO_PCLRR_DATAH			0x100031
+#define MCF_GPIO_PCLRR_DATAL			0x100032
+#define MCF_GPIO_PCLRR_BUSCTL			0x100033
+#define MCF_GPIO_PCLRR_BS			0x100034
+#define MCF_GPIO_PCLRR_CS			0x100035
+#define MCF_GPIO_PCLRR_SDRAM			0x100036
+#define MCF_GPIO_PCLRR_FECI2C			0x100037
+#define MCF_GPIO_PCLRR_UARTH			0x100038
+#define MCF_GPIO_PCLRR_UARTL			0x100039
+#define MCF_GPIO_PCLRR_QSPI			0x10003A
+#define MCF_GPIO_PCLRR_TIMER			0x10003B
+
 #define MCF_GPIO_PAR_AD				0x100040
+#define MCF_GPIO_PAR_BUSCTL			0x100042
+#define MCF_GPIO_PAR_BS				0x100044
 #define MCF_GPIO_PAR_CS				0x100045
 #define MCF_GPIO_PAR_SDRAM			0x100046
 #define MCF_GPIO_PAR_FECI2C			0x100047
 #define MCF_GPIO_PAR_UART			0x100048
+#define MCF_GPIO_PAR_QSPI			0x10004A
+#define MCF_GPIO_PAR_TIMER			0x10004C
+
+#define MCF_DSCR_EIM				0x100050
+#define MCF_DCSR_FEC12C 			0x100052
+#define MCF_DCSR_UART				0x100053
+#define MCF_DCSR_QSPI				0x100054
+#define MCF_DCSR_TIMER				0x100055
 
 #define MCF_CCM_CIR				0x11000A
 #define MCF_CCM_CIR_PRN_MASK			0x3F
 #define MCF_CCM_CIR_PIN_LEN			6
-#define MCF_CCM_CIR_PIN_MCF5270			0x2e
-#define MCF_CCM_CIR_PIN_MCF5271			0x80
+#define MCF_CCM_CIR_PIN_MCF5270			0x002e
+#define MCF_CCM_CIR_PIN_MCF5271			0x0032
 
 #define MCF_GPIO_AD_ADDR23			0x80
 #define MCF_GPIO_AD_ADDR22			0x40
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index cd9094519b..808786985e 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -415,7 +415,25 @@ typedef struct ioctrl512x {
  * IIM
  */
 typedef struct iim512x {
-	u8 fixme[0x1000];
+	u32 stat;		/* IIM status register */
+	u32 statm;		/* IIM status IRQ mask */
+	u32 err;		/* IIM errors register */
+	u32 emask;		/* IIM error IRQ mask  */
+	u32 fctl;		/* IIM fuse control register */
+	u32 ua;			/* IIM upper address register */
+	u32 la;			/* IIM lower address register */
+	u32 sdat;		/* IIM explicit sense data */
+	u8 res0[0x08];
+	u32 prg_p;		/* IIM program protection register */
+	u8 res1[0x10];
+	u32 divide;		/* IIM divide factor register */
+	u8 res2[0x7c0];
+	u32 fbac0;		/* IIM fuse bank 0 prot (for Freescale use) */
+	u32 fb0w0[0x1f];	/* IIM fuse bank 0 data (for Freescale use) */
+	u8 res3[0x380];
+	u32 fbac1;		/* IIM fuse bank 1 protection */
+	u32 fb1w1[0x01f];	/* IIM fuse bank 1 data */
+	u8 res4[0x380];
 } iim512x_t;
 
 /*
@@ -451,7 +469,34 @@ typedef struct lpc512x {
  * PATA
  */
 typedef struct pata512x {
-	u8 fixme[0x100];
+	/* LOCAL Registers */
+	u32 pata_time1;		/* Time register 1: PIO and tx timing parameter */
+	u32 pata_time2;		/* Time register 2: PIO timing parameter */
+	u32 pata_time3;		/* Time register 3: PIO and MDMA timing parameter */
+	u32 pata_time4;		/* Time register 4: MDMA and UDMA timing parameter */
+	u32 pata_time5;		/* Time register 5: UDMA timing parameter */
+	u32 pata_time6;		/* Time register 6: UDMA timing parameter */
+	u32 pata_fifo_data32;   /* 32bit wide dataport to/from FIFO */
+	u32 pata_fifo_data16;   /* 16bit wide dataport to/from FIFO */
+	u32 pata_fifo_fill;	/* FIFO filling in halfwords (READONLY)*/
+	u32 pata_ata_control;   /* ATA Interface control register */
+	u32 pata_irq_pending;   /* Interrupt pending register (READONLY) */
+	u32 pata_irq_enable;	/* Interrupt enable register */
+	u32 pata_irq_clear;	/* Interrupt clear register (WRITEONLY)*/
+	u32 pata_fifo_alarm;	/* fifo alarm threshold */
+	u32 res1[0x1A];
+	/* DRIVE Registers */
+	u32 pata_drive_data;	/* drive data register*/
+	u32 pata_drive_features;/* drive features register */
+	u32 pata_drive_sectcnt; /* drive sector count register */
+	u32 pata_drive_sectnum; /* drive sector number register */
+	u32 pata_drive_cyllow;  /* drive cylinder low register */
+	u32 pata_drive_cylhigh; /* drive cylinder high register */
+	u32 pata_drive_dev_head;/* drive device head register */
+	u32 pata_drive_command; /* write = drive command, read = drive status reg */
+	u32 res2[0x06];
+	u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
+	u32 res3[0x09];
 } pata512x_t;
 
 /*
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 7ddeb550b6..50b3ab2808 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -82,7 +82,10 @@
 #define CONFIG_CMD_MISC
 
 #undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMDLINE_EDITING	1 /* enables command line history */
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
@@ -116,7 +119,7 @@
 #define CONFIG_SYS_I2C_OFFSET		0x00000300
 #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds */
 #define CONFIG_BOOTFILE		"u-boot.bin"
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_NET_RETRY_COUNT	5
@@ -128,16 +131,16 @@
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
 #endif				/* FEC_ENET */
 
-#define CONFIG_HOSTNAME		M5235EVB
+#define CONFIG_HOSTNAME		M5271EVB
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"netdev=eth0\0"				\
 	"loadaddr=10000\0"			\
-	"u-boot=u-boot.bin\0"			\
-	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"uboot=u-boot.bin\0"		\
+	"load=tftp $loadaddr $uboot\0"	\
 	"upd=run load; run prog\0"		\
-	"prog=prot off ffe00000 ffe2ffff;"		\
-	"era ffe00000 ffe2ffff;"				\
-	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b $loadaddr ffe00000 $filesize;"	\
 	"save\0"				\
 	""
 
@@ -159,7 +162,17 @@
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
 #define CONFIG_SYS_HZ			1000000
+
+/* Clock configuration
+ * The external oscillator is a 25.000 MHz
+ * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
+ * bus_clk = (cpu_clk/2) (fixed ratio)
+ *
+ * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
+ * match the new clock speed. Max cpu_clk is 150 MHz.
+ */
 #define CONFIG_SYS_CLK			100000000
+#define CONFIG_SYS_MCF_SYNCR 	(MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
 
 /*
  * Low Level Configuration Settings
@@ -216,7 +229,14 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
-/* Port configuration */
-#define CONFIG_SYS_FECI2C		0xF0
+/* Chip Select 0  : Boot Flash */
+#define CONFIG_SYS_CS0_BASE	0xFFE00000
+#define CONFIG_SYS_CS0_MASK	0x001F0001
+#define CONFIG_SYS_CS0_CTRL	0x00001980
+
+/* Chip Select 1 : External SRAM */
+#define CONFIG_SYS_CS1_BASE	0x30000000
+#define CONFIG_SYS_CS1_MASK	0x00070001
+#define CONFIG_SYS_CS1_CTRL	0x00001900
 
 #endif				/* _M5271EVB_H */
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index bb3525f175..8fda3f29fa 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -47,6 +47,7 @@
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+#undef CONFIG_FSL_DIU_LOGO_BMP		/* Don't include FSL DIU binary bmp */
 
 /* video */
 #undef CONFIG_VIDEO
@@ -294,6 +295,11 @@
 #endif
 
 /*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_IIM
+
+/*
  * EEPROM configuration
  */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
@@ -348,11 +354,20 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DATE
+#undef CONFIG_CMD_FUSE
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #endif
 
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
 /*
  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
@@ -489,4 +504,48 @@
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
 
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC512X_PATA
+
+/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
+
+/* Interval between registers	*/
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define ATA_BASE_ADDR		MPC512X_PATA
+
+/*
+ * Control register bit definitions
+ */
+#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
+#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
+#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
+#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
+#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
+#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
+#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
+#define FSL_ATA_CTRL_IORDY_EN		0x01000000
+
 #endif	/* __CONFIG_H */
diff --git a/include/flash.h b/include/flash.h
index 6e2981c5ae..02c6a04314 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -33,7 +33,7 @@ typedef struct {
 	ulong	size;			/* total bank size in bytes		*/
 	ushort	sector_count;		/* number of erase units		*/
 	ulong	flash_id;		/* combined device & manufacturer code	*/
-	ulong	start[CONFIG_SYS_MAX_FLASH_SECT];   /* physical sector start addresses */
+	ulong	start[CONFIG_SYS_MAX_FLASH_SECT];   /* virtual sector start address */
 	uchar	protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status	*/
 #ifdef CONFIG_SYS_FLASH_CFI
 	uchar	portwidth;		/* the width of the port		*/
diff --git a/include/mpc512x.h b/include/mpc512x.h
index 05a206358b..0f022939da 100644
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -573,6 +573,31 @@ void iopin_initialize(iopin_t *,int);
 
  /* Register Offset Base */
 #define MPC512X_FEC		(CONFIG_SYS_IMMR + 0x02800)
+#define MPC512X_PATA		(CONFIG_SYS_IMMR + 0x10200)
+
+/* IIM control */
+#define IIM_SET_UA(bk, f)	((bk << 3) | (f >> 5))
+#define IIM_SET_LA(f, bit)	(((f & 0x0000001f) << 3) | bit)
+#define IIM_STAT_BUSY		0x00000080
+#define IIM_STAT_PRGD		0x00000002
+#define IIM_STAT_SNSD		0x00000001
+#define IIM_ERR_WPE		0x00000040
+#define IIM_ERR_OPE		0x00000020
+#define IIM_ERR_RPE		0x00000010
+#define IIM_ERR_WLRE		0x00000008
+#define IIM_ERR_SNSE		0x00000004
+#define IIM_ERR_PARITYE		0x00000002
+#define IIM_PRG_P_SET		0x000000aa
+#define IIM_PRG_P_UNSET		0
+#define IIM_FCTL_PROG_PULSE	0x00000020
+#define IIM_FCTL_PROG		0x00000001
+#define IIM_FCTL_ESNS_N		0x00000008
+#define	IIM_FBAC_FBWP		0x00000080
+#define IIM_FBAC_FBOP		0x00000040
+#define IIM_FBAC_FBRP		0x00000020
+#define	IIM_FBAC_FBESP		0x00000008
+#define IIM_PROTECTION		0x000000e8
+#define IIM_FMAX			31
 
 /* Number of I2C buses */
 #define I2C_BUS_CNT	3
diff --git a/include/pci.h b/include/pci.h
index 072273be57..35ff1e9035 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -334,7 +334,7 @@ struct pci_region {
 #define PCI_REGION_TYPE		0x00000001
 #define PCI_REGION_PREFETCH	0x00000008	/* prefetchable PCI memory */
 
-#define PCI_REGION_MEMORY	0x00000100	/* System memory */
+#define PCI_REGION_SYS_MEMORY	0x00000100	/* System memory */
 #define PCI_REGION_RO		0x00000200	/* Read-only memory */
 
 extern __inline__ void pci_set_region(struct pci_region *reg,