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| author | Tom Rini <trini@ti.com> | 2013-07-16 21:05:35 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-16 21:05:35 -0400 |
| commit | f78cb2ab1ee9206cf72d0dad044dcc9c586f64e7 (patch) | |
| tree | 6b02d2c57e043f43c98a793553abd1be641d38b7 | |
| parent | 2a6936059a1f393d828274bf5d33dd54c0a3c882 (diff) | |
| parent | a61da72bda80e09f36afbc9037a8c8b63b482de4 (diff) | |
| download | talos-obmc-uboot-f78cb2ab1ee9206cf72d0dad044dcc9c586f64e7.tar.gz talos-obmc-uboot-f78cb2ab1ee9206cf72d0dad044dcc9c586f64e7.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mmc
| -rw-r--r-- | drivers/mmc/dw_mmc.c | 1 | ||||
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 8 |
2 files changed, 4 insertions, 5 deletions
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 5da20eda55..684a2a8df7 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -23,7 +23,6 @@ #include <malloc.h> #include <mmc.h> #include <dwmmc.h> -#include <asm/arch/clk.h> #include <asm-generic/errno.h> #define PAGE_SIZE 4096 diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 973b19f337..eba1de3294 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -100,7 +100,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#ifdef CONFIG_MX53 +#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif @@ -470,7 +470,7 @@ static int esdhc_init(struct mmc *mmc) int timeout = 1000; /* Reset the entire host controller */ - esdhc_write32(®s->sysctl, SYSCTL_RSTA); + esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); /* Wait until the controller is available */ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) @@ -481,7 +481,7 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(®s->scr, 0x00000040); #endif - esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); + esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); @@ -515,7 +515,7 @@ static void esdhc_reset(struct fsl_esdhc *regs) unsigned long timeout = 100; /* wait max 100 ms */ /* reset the controller */ - esdhc_write32(®s->sysctl, SYSCTL_RSTA); + esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); /* hardware clears the bit when it is done */ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) |
