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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-08-29 13:10:38 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:13:11 -0700 |
| commit | e982746844605e5155fbd2e0ce13c3ecf7fafe48 (patch) | |
| tree | 2889b68a69a0976bca54441caa9fe6839451ac56 | |
| parent | 0e61077b215aff9228a4d6ca746761b49380713c (diff) | |
| download | talos-obmc-uboot-e982746844605e5155fbd2e0ce13c3ecf7fafe48.tar.gz talos-obmc-uboot-e982746844605e5155fbd2e0ce13c3ecf7fafe48.zip | |
powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2
CHASSIS2 architecture never defines type of L2 cache present in SoC.
it is dependent upon the core present in the SoC.
for example,
- e6500 core has L2 cluster (Kibo)
- e5500 core has Backside L2 Cache
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 6036333eaa..a8107a9c08 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -284,7 +284,7 @@ static void __fsl_serdes__init(void) } __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) int enable_cluster_l2(void) { int i = 0; @@ -350,7 +350,7 @@ int cpu_init_r(void) #endif #ifdef CONFIG_L2_CACHE ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; -#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) @@ -533,7 +533,7 @@ int cpu_init_r(void) } skip_l2: -#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (l2cache->l2csr0 & L2CSR0_L2E) print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 533d47ab43..2ccd9c7b95 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -273,7 +273,7 @@ static inline void ft_fixup_l2cache(void *blob) if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) /* Only initialize every eighth thread */ if (reg && !((*reg) % 8)) #else diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index d329aa84ab..6a81fa73e4 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -699,7 +699,7 @@ delete_temp_tlbs: #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: /* * Create a TLB for the MMR location of CCSR |
