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| author | Paul Kocialkowski <contact@paulk.fr> | 2015-05-16 19:52:11 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-05-19 18:46:44 +0200 |
| commit | 8a65f69c9cef09aebc20aca98a4ddbf2b4829995 (patch) | |
| tree | cb822d4355a80482aca76e1845a43525fd6be375 | |
| parent | 5bfdca0d4cebab34d3b81a4a8852d9ec3923b0b9 (diff) | |
| download | talos-obmc-uboot-8a65f69c9cef09aebc20aca98a4ddbf2b4829995.tar.gz talos-obmc-uboot-8a65f69c9cef09aebc20aca98a4ddbf2b4829995.zip | |
sunxi: Cache line size definition
Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores,
which all have 64 bytes cache line size.
This is required to e.g. enable USB gadget.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| -rw-r--r-- | include/configs/sunxi-common.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index f80f006e3d..d829899c07 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -66,6 +66,9 @@ # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif +/* CPU */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* DRAM Base */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_INIT_RAM_ADDR 0x0 |
