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authorSimon Glass <sjg@chromium.org>2016-01-17 16:11:39 -0700
committerBin Meng <bmeng.cn@gmail.com>2016-01-24 12:09:40 +0800
commit865c24eea1fa4bec3106368052edcdcf4711b366 (patch)
treed756856396007b415f8b06175ce97356264c557b
parentddf10c20d24d96ddd016ae926dccd5f4caf86c15 (diff)
downloadtalos-obmc-uboot-865c24eea1fa4bec3106368052edcdcf4711b366.tar.gz
talos-obmc-uboot-865c24eea1fa4bec3106368052edcdcf4711b366.zip
x86: ivybridge: Move lpc_enable() into gma.c
This graphics init code is best placed in the gma init code. Move the code and drop the function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-rw-r--r--arch/x86/cpu/ivybridge/bd82x6x.c1
-rw-r--r--arch/x86/cpu/ivybridge/gma.c4
-rw-r--r--arch/x86/cpu/ivybridge/lpc.c7
-rw-r--r--arch/x86/include/asm/arch-ivybridge/pch.h1
4 files changed, 4 insertions, 9 deletions
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 188b7da4f7..9e7e30aa11 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -29,7 +29,6 @@ static int bd82x6x_probe(struct udevice *dev)
return 0;
hose = pci_bus_to_hose(0);
- lpc_enable(PCH_LPC_DEV);
lpc_init_extra(hose, PCH_LPC_DEV);
/* Cause the SATA device to do its init */
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 1748f7fdce..b94536c7a6 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -806,6 +806,10 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
u32 reg32;
int ret;
+ /* Enable PCH Display Port */
+ writew(0x0010, RCB_REG(DISPBDF));
+ setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
+
ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge);
if (!nbridge)
return -ENODEV;
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 0d85de2a76..44c4825f13 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -602,13 +602,6 @@ int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev)
return 0;
}
-void lpc_enable(pci_dev_t dev)
-{
- /* Enable PCH Display Port */
- writew(0x0010, RCB_REG(DISPBDF));
- setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
-}
-
static int bd82x6x_lpc_early_init(struct udevice *dev)
{
/* Setting up Southbridge. In the northbridge code. */
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index f35803bbf4..682a557fbd 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -471,6 +471,5 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#define TCO2_STS 0x66
int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev);
-void lpc_enable(pci_dev_t dev);
#endif
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