1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
|
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018 Intel Corporation */
#ifndef __LINUX_MFD_INTEL_PECI_CLIENT_H
#define __LINUX_MFD_INTEL_PECI_CLIENT_H
#include <linux/peci.h>
#if IS_ENABLED(CONFIG_X86)
#include <asm/intel-family.h>
#else
/**
* Architectures other than x86 cannot include the header file so define these
* at here. These are needed for detecting type of client x86 CPUs behind a PECI
* connection.
*/
#define INTEL_FAM6_HASWELL_X 0x3F
#define INTEL_FAM6_BROADWELL_X 0x4F
#define INTEL_FAM6_SKYLAKE_X 0x55
#endif
#define CORE_MAX_ON_HSX 18 /* Max number of cores on Haswell */
#define CHAN_RANK_MAX_ON_HSX 8 /* Max number of channel ranks on Haswell */
#define DIMM_IDX_MAX_ON_HSX 3 /* Max DIMM index per channel on Haswell */
#define CORE_MAX_ON_BDX 24 /* Max number of cores on Broadwell */
#define CHAN_RANK_MAX_ON_BDX 4 /* Max number of channel ranks on Broadwell */
#define DIMM_IDX_MAX_ON_BDX 3 /* Max DIMM index per channel on Broadwell */
#define CORE_MAX_ON_SKX 28 /* Max number of cores on Skylake */
#define CHAN_RANK_MAX_ON_SKX 6 /* Max number of channel ranks on Skylake */
#define DIMM_IDX_MAX_ON_SKX 2 /* Max DIMM index per channel on Skylake */
#define CORE_NUMS_MAX CORE_MAX_ON_SKX
#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
#define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
#define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX)
/**
* struct cpu_gen_info - CPU generation specific information
* @family: CPU family ID
* @model: CPU model
* @core_max: max number of cores
* @chan_rank_max: max number of channel ranks
* @dimm_idx_max: max number of DIMM indices
*
* CPU generation specific information to identify maximum number of cores and
* DIMM slots.
*/
struct cpu_gen_info {
u16 family;
u8 model;
uint core_max;
uint chan_rank_max;
uint dimm_idx_max;
};
/**
* struct peci_client_manager - PECI client manager information
* @client; pointer to the PECI client
* @dev: pointer to the struct device
* @name: PECI client manager name
* @gen_info: CPU generation info of the detected CPU
*
* PECI client manager information for managing PECI sideband functions on a CPU
* client.
*/
struct peci_client_manager {
struct peci_client *client;
struct device *dev;
char name[PECI_NAME_SIZE];
const struct cpu_gen_info *gen_info;
};
/**
* peci_client_read_package_config - read from the Package Configuration Space
* @priv: driver private data structure
* @index: encoding index for the requested service
* @param: parameter to specify the exact data being requested
* @data: data buffer to store the result
* Context: can sleep
*
* A generic PECI command that provides read access to the
* "Package Configuration Space" that is maintained by the PCU, including
* various power and thermal management functions. Typical PCS read services
* supported by the processor may include access to temperature data, energy
* status, run time information, DIMM temperatures and so on.
*
* Return: zero on success, else a negative error code.
*/
static inline int
peci_client_read_package_config(struct peci_client_manager *priv,
u8 index, u16 param, u8 *data)
{
struct peci_rd_pkg_cfg_msg msg;
int rc;
msg.addr = priv->client->addr;
msg.index = index;
msg.param = param;
msg.rx_len = 4;
rc = peci_command(priv->client->adapter, PECI_CMD_RD_PKG_CFG, &msg);
if (!rc)
memcpy(data, msg.pkg_config, 4);
return rc;
}
#endif /* __LINUX_MFD_INTEL_PECI_CLIENT_H */
|
