1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
|
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include "skeleton.dtsi"
#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a5";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
sxosc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
fxosc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
aips0: aips-bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
reg = <0x40000000 0x70000>;
ranges;
intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;
};
L2: l2-cache@40006000 {
compatible = "arm,pl310-cache";
reg = <0x40006000 0x1000>;
cache-unified;
cache-level = <2>;
arm,data-latency = <1 1 1>;
arm,tag-latency = <2 2 2>;
};
edma0: dma-controller@40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x40018000 0x2000>,
<0x40024000 0x1000>,
<0x40025000 0x1000>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
<0 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
};
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>,
<&edma0 0 3>;
dma-names = "rx","tx";
status = "disabled";
};
uart1: serial@40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
dmas = <&edma0 0 4>,
<&edma0 0 5>;
dma-names = "rx","tx";
status = "disabled";
};
uart2: serial@40029000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40029000 0x1000>;
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART2>;
clock-names = "ipg";
dmas = <&edma0 0 6>,
<&edma0 0 7>;
dma-names = "rx","tx";
status = "disabled";
};
uart3: serial@4002a000 {
compatible = "fsl,vf610-lpuart";
reg = <0x4002a000 0x1000>;
interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART3>;
clock-names = "ipg";
dmas = <&edma0 0 8>,
<&edma0 0 9>;
dma-names = "rx","tx";
status = "disabled";
};
dspi0: dspi0@4002c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <5>;
status = "disabled";
};
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI2>;
clock-names = "sai";
dma-names = "tx", "rx";
dmas = <&edma0 0 21>,
<&edma0 0 20>;
status = "disabled";
};
pit: pit@40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
adc0: adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
interrupts = <0 53 0x04>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
status = "disabled";
};
wdog@4003e000 {
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
reg = <0x4003e000 0x1000>;
clocks = <&clks VF610_CLK_WDT>;
clock-names = "wdog";
};
qspi0: quadspi@40044000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_QSPI0_EN>,
<&clks VF610_CLK_QSPI0>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
iomuxc: iomuxc@40048000 {
compatible = "fsl,vf610-iomuxc";
reg = <0x40048000 0x1000>;
#gpio-range-cells = <3>;
};
gpio1: gpio@40049000 {
compatible = "fsl,vf610-gpio";
reg = <0x40049000 0x1000 0x400ff000 0x40>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
};
gpio2: gpio@4004a000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
};
gpio3: gpio@4004b000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 64 32>;
};
gpio4: gpio@4004c000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 96 32>;
};
gpio5: gpio@4004d000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 128 7>;
};
anatop@40050000 {
compatible = "fsl,vf610-anatop";
reg = <0x40050000 0x1000>;
};
i2c0: i2c@40066000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
<&edma0 0 51>;
dma-names = "rx","tx";
status = "disabled";
};
clks: ccm@4006b000 {
compatible = "fsl,vf610-ccm";
reg = <0x4006b000 0x1000>;
#clock-cells = <1>;
};
};
aips1: aips-bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40080000 0x80000>;
ranges;
edma1: dma-controller@40098000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x40098000 0x2000>,
<0x400a1000 0x1000>,
<0x400a2000 0x1000>;
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
<0 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX2>,
<&clks VF610_CLK_DMAMUX3>;
};
uart4: serial@400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
};
uart5: serial@400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
};
adc1: adc@400bb000 {
compatible = "fsl,vf610-adc";
reg = <0x400bb000 0x1000>;
interrupts = <0 54 0x04>;
clocks = <&clks VF610_CLK_ADC1>;
clock-names = "adc";
status = "disabled";
};
esdhc1: esdhc@400b2000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b2000 0x4000>;
interrupts = <0 28 0x04>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC1>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
fec1: ethernet@400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
};
};
};
|
