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path: root/drivers/pinctrl/intel/pinctrl-icelake.c
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* pinctrl: icelake: Code formatting fixesAndy Shevchenko2018-11-081-1/+1
| | | | | | | | Remove comma from terminator line to allow compiler fail in case an entry has been put in a wrong place by any weird reason. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: icelake: Get rid of unneeded ->probe() stubAndy Shevchenko2018-11-081-7/+2
| | | | | | | | | | | The local ->probe() stub does nothing except calling a generic Intel pin control probe function. Thus, it's not needed and generic function may be called directly. Convert the driver accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* pinctrl: intel: Move linux/pm.h to the local headerAndy Shevchenko2018-09-181-1/+1
| | | | | | | | | | | | We now using a common macro for PM operations in pin control drivers for Intel SoCs, and since that macro relies on the definition and macro from linux/pm.h header file, it's logical to include it directly in pinctrl-intel.h. Otherwise it's a bit fragile and requires a proper ordering of header inclusion in C files. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: icelake: Define PM ops via INTEL_PINCTRL_PM_OPS()Andy Shevchenko2018-08-311-4/+1
| | | | | | | | | | | Instead of open coding same structure definition for PM operations, replace it with a common macro. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Ice Lake PCH pin controller supportAndy Shevchenko2018-06-291-0/+436
This adds pinctrl/GPIO support for Intel Ice Lake PCH. The Ice Lake PCH GPIO is based on the same version of the Intel GPIO hardware than Intel Cannon Lake with different set of pins and ACPI ID. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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