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path: root/drivers/gpu/drm/i915/intel_pm.c
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* drm/i915/chv: Use 16 and 32 for low and high drain latency precision.Rodrigo Vivi2014-10-241-15/+25
* drm/i915/bdw: Remove BDW preproduction W/As until C stepping.Rodrigo Vivi2014-10-241-10/+0
* drm/i915: Do not export RC6p and RC6pp if they don't existRodrigo Vivi2014-10-241-5/+10
* Merge branch 'drm-intel-next-fixes' into drm-intel-nextDaniel Vetter2014-10-211-197/+46
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| * drm/i915: Don't spam dmesg with rps messages on vlv/chvVille Syrjälä2014-09-291-6/+7
| * Revert "drm/i915/bdw: BDW Software Turbo"Daniel Vetter2014-09-291-191/+39
* | drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/Daniel Vetter2014-10-031-1/+0
* | drm/i915: Extract intel_runtime_pm.cDaniel Vetter2014-10-011-1160/+0
* | Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter2014-09-301-2/+28
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| * | drm/i915/skl: Move gen9 pm initialization into its own branchDamien Lespiau2014-09-241-3/+3
| * | drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:sklDamien Lespiau2014-09-241-0/+8
| * | drm/i915/skl: Implement Wa4x4STCOptimizationDisable:sklDamien Lespiau2014-09-241-0/+4
| * | drm/i915/skl: Implement WaDisableSDEUnitClockGating:sklDamien Lespiau2014-09-241-0/+8
| * | drm/i915/skl: Restore pipe B/C interruptsSatheeshakrishna M2014-09-241-1/+1
| * | drm/i915/skl: Provide a placeholder for init_clock_gating()Damien Lespiau2014-09-241-0/+6
* | | drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.Rodrigo Vivi2014-09-291-1/+1
* | | drm/i915: add SW tracking to FBC enablingPaulo Zanoni2014-09-231-11/+20
* | | drm/i915: extract intel_init_fbc()Paulo Zanoni2014-09-231-22/+28
* | | drm/i915: Avoid reading fbc registers in vain when fbc was never enabled.Rodrigo Vivi2014-09-191-0/+6
* | | drm/i915: Only flush fbc on sw when fbc is enabled.Rodrigo Vivi2014-09-191-0/+3
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* | drm/i915: Limit the watermark to at least 8 entries on gen2/3Ville Syrjälä2014-09-191-0/+11
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* drm/i915: Reset power sequencer pipe tracking when disp2d is offVille Syrjälä2014-09-041-0/+2
* drm/i915: Rename global latency_ns variableChris Wilson2014-09-031-18/+18
* drm/i915: Disable trickle feed for gen2/3Ville Syrjälä2014-09-031-0/+10
* drm/i915: Fix gen2 planes B and C max watermark valueVille Syrjälä2014-09-031-4/+20
* drm/i915: Init some CHV workarounds via LRIs in ring->init_context()Ville Syrjälä2014-09-031-14/+0
* drm/i915: Warn about odd rps values on CHVVille Syrjälä2014-09-031-0/+11
* drm/i915/bdw: BDW Software TurboDaisy Sun2014-09-031-39/+191
* drm/i915: Populate mem_freq in init_gt_powerwave()Ville Syrjälä2014-09-031-47/+43
* drm/i915/bdw: Apply workarounds in render ring init functionArun Siluvery2014-09-031-48/+0
* drm/i915: FBC flush nuke for BDWRodrigo Vivi2014-09-031-0/+10
* drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gatingPaulo Zanoni2014-09-031-2/+2
* drm/i915: call lpt_init_clock_gating on BDW tooPaulo Zanoni2014-09-031-0/+2
* drm/i915: Bring UP Power Wells before disabling RC6.Deepak S2014-09-031-0/+6
* drm/i915: Use dev_priv as first argument of for_each_pipe()Damien Lespiau2014-09-031-9/+8
* drm/i915: Add 180 degree primary plane rotation supportSonika Jindal2014-09-031-0/+6
* Merge tag 'drm-intel-next-2014-09-01' of git://anongit.freedesktop.org/drm-in...Dave Airlie2014-09-031-2/+0
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| * drm/i915: Remove set but unused 'gt_perf_status'Damien Lespiau2014-08-111-2/+0
* | Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-in...Dave Airlie2014-08-261-54/+474
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| * drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat2014-08-081-0/+33
| * drm/i915: Round-up clock and limit drain latencyGajanan Bhat2014-08-081-1/+4
| * drm/i915: Generalize drain latency computationGajanan Bhat2014-08-081-37/+50
| * drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä2014-08-081-4/+4
| * drm/i915: Hack to tie both common lanes together on chvVille Syrjälä2014-08-081-2/+12
| * drm/i915: Add cherryview_update_wm()Ville Syrjälä2014-08-081-1/+80
| * drm/i915: Update DDL only for current CRTCGajanan Bhat2014-08-081-16/+9
| * drm/i915: Parametrize VLV_DDL registersVille Syrjälä2014-08-081-29/+23
| * drm/i915: Fill out the FWx watermark register definesVille Syrjälä2014-08-081-4/+7
| * drm/i915: Introduce FBC False Color for debug purposes.Rodrigo Vivi2014-08-081-0/+3
| * drm/i915: Split a few long debug printsVille Syrjälä2014-08-081-2/+4
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