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path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
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* drm/i915/cnl: Dump the right pll registers when dumping pipe config.Rodrigo Vivi2017-08-111-1/+10
* drm/i915/cnl: make function cnl_ddi_dp_set_dpll_hw_state staticColin Ian King2017-06-151-2/+3
* drm/i915/cnl: Enable wrpll computation for CNLKahola, Mika2017-06-121-2/+138
* drm/i915/cnl: Initialize PLLsRodrigo Vivi2017-06-121-2/+298
* drm/i915: Remove unused function intel_ddi_get_link_dpll()Ander Conselvan de Oliveira2017-02-101-44/+8
* drm/i915/bxt: Add MST support when do DPLL calculationLee, Shawn C2017-02-031-1/+2
* drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.Rodrigo Vivi2017-01-241-1/+1
* drm/i915: Move intel_atomic_get_shared_dpll_state() to intel_dpll_mgr.cAnder Conselvan de Oliveira2017-01-021-0/+31
* drm/i915: Add dpll entrypoint for dumping hw stateAnder Conselvan de Oliveira2016-12-301-0/+79
* drm/i915: Update kerneldoc for intel_dpll_mgr.cAnder Conselvan de Oliveira2016-12-301-5/+86
* drm/i915: Rename intel_shared_dpll->mode_set() to prepare()Ander Conselvan de Oliveira2016-12-301-4/+4
* drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_stateAnder Conselvan de Oliveira2016-12-301-36/+36
* drm/i915: Rename intel_shared_dpll_commit() to _swap_state()Ander Conselvan de Oliveira2016-12-301-1/+6
* drm/i915: Introduce intel_release_shared_dpll()Ander Conselvan de Oliveira2016-12-301-23/+18
* drm/i915/glk: Update Port PLL enable sequence for GeminilkaeMadhav Chauhan2016-12-021-0/+20
* drm/i915/glk: Set DCC delay range 2 in PLL enable sequenceAnder Conselvan de Oliveira2016-12-021-0/+6
* drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira2016-12-021-2/+2
* drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira2016-12-021-1/+1
* drm/i915: Assorted INTEL_INFO(dev) cleanupsTvrtko Ursulin2016-11-171-3/+2
* drm/i915: Address broxton phy registers based on phy and channel numberAnder Conselvan de Oliveira2016-10-281-38/+46
* drm/i915: Make IS_BROXTON only take dev_privTvrtko Ursulin2016-10-141-1/+1
* drm/i915: Make IS_KABYLAKE only take dev_privTvrtko Ursulin2016-10-141-1/+1
* drm/i915: Make INTEL_PCH_TYPE & co only take dev_privTvrtko Ursulin2016-10-141-1/+1
* drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_privTvrtko Ursulin2016-10-141-2/+2
* drm/i915/bxt: Fix HDMI DPLL configurationImre Deak2016-09-271-5/+16
* drm/i915: do not use 'false' as a NULL pointerJani Nikula2016-09-161-2/+2
* drm/i915/dp: Add a standalone function to obtain shared dpll for HSW/BDW/SKL/BXTJim Bride2016-09-091-0/+38
* drm/i915: Split hsw_get_dpll()Manasi Navare2016-09-071-33/+57
* drm/i915: Split skl_get_dpll()Jim Bride2016-09-071-48/+83
* drm/i915: Split bxt_ddi_pll_select()Durgadoss R2016-09-071-66/+102
* drm/i915: Remove ddi_pll_sel from intel_crtc_stateAnder Conselvan de Oliveira2016-09-071-27/+0
* drm/i915: handle DP_MST correctly in bxt_get_dpllMaarten Lankhorst2016-08-231-2/+8
* drm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/Ville Syrjälä2016-07-071-3/+3
* drm/i915: Convert dev_priv->dev backpointers to dev_priv->drmChris Wilson2016-07-051-1/+1
* drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson2016-07-041-6/+6
* drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson2016-06-301-1/+5
* drm/i915/bxt: Avoid early timeout during PLL enableImre Deak2016-06-281-2/+2
* drm/i915: Use crtc->name in debug messagesVille Syrjälä2016-05-301-8/+8
* drm/i915: Fix NULL pointer deference when out of PLLs in IVBAnder Conselvan de Oliveira2016-05-261-0/+3
* drm/i915: Unify SKL cdclk init pathsVille Syrjälä2016-05-231-9/+2
* drm/i915: Keep track of preferred cdclk vco frequency on SKLVille Syrjälä2016-05-231-0/+5
* drm/i915: Actually read out DPLL0 vco on skl from hardwareVille Syrjälä2016-05-231-6/+0
* drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()Ville Syrjälä2016-05-231-4/+0
* drm/i915/skl: SKL CDCLK change on modeset tracking VCOClint Taylor2016-05-231-4/+5
* drm/i915: Remove intel_clock_t typedefAnder Conselvan de Oliveira2016-05-131-1/+1
* drm/i915: s/DPPL/DPLL/ for SKL DPLLsVille Syrjälä2016-05-121-3/+3
* drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variationsDongwon Kim2016-04-151-10/+2
* drm/i915/bxt: Don't toggle power well 1 on-demandImre Deak2016-04-151-4/+1
* drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpersImre Deak2016-04-151-2/+2
* drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bitDongwon Kim2016-04-111-1/+9
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