summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_reg.h
Commit message (Expand)AuthorAgeFilesLines
* drm/i915/bdw: BWGTLB clock gate disableBen Widawsky2013-11-081-0/+1
* drm/i915/bdw: Implement edp PSR workaroundsBen Widawsky2013-11-081-0/+6
* drm/i915/bdw: Support eDP PSRBen Widawsky2013-11-081-2/+2
* drm/i915/bdw: Use The GT mailbox for IPS enable/disableBen Widawsky2013-11-081-0/+1
* drm/i915/bdw: Add Broadwell display FIFO limitsVille Syrjälä2013-11-081-0/+1
* drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasisPaulo Zanoni2013-11-081-0/+11
* drm/i915/bdw: get the correct LCPLL frequency on BroadwellPaulo Zanoni2013-11-081-0/+3
* drm/i915/bdw: Broadwell has PIPEMISCPaulo Zanoni2013-11-081-0/+12
* drm/i915/bdw: Implement PPGTT enableBen Widawsky2013-11-081-0/+3
* drm/i915/bdw: Support BDW cachingBen Widawsky2013-11-081-0/+1
* drm/i915/bdw: dispatch updates (64b related)Ben Widawsky2013-11-081-0/+1
* drm/i915/bdw: Implement interrupt changesBen Widawsky2013-11-081-0/+68
* drm/i915/bdw: display stuffBen Widawsky2013-11-081-0/+1
* drm/i915/bdw: HW context supportBen Widawsky2013-11-081-0/+3
* drm/i915/bdw: Swizzling supportBen Widawsky2013-11-081-0/+2
* Merge tag 'v3.12' into drm-intel-nextDaniel Vetter2013-11-041-0/+12
|\
| * drm/i915: Disable GGTT PTEs on GEN6+ suspendBen Widawsky2013-10-181-0/+4
| * drm/i915: disable LVDS clock gating on CPT v2Jesse Barnes2013-10-151-0/+2
| * drm/i915/hsw: Disable L3 caching of atomic memory operations.Francisco Jerez2013-10-031-0/+6
* | drm/i915: scramble reset support for DP port CRC on g4xDaniel Vetter2013-11-011-0/+8
* | drm/i915/vlv: Fix typo in the DPIO register define.Chon Ming Lee2013-10-311-1/+1
* | drm/i915: refactor ilk display interrupt handlingDaniel Vetter2013-10-301-2/+5
* | drm/i915: Capture batchbuffer state upon GPU hangChris Wilson2013-10-301-0/+1
* | drm/i915: Remove WaFbcDisableDpfcClockGating on HSWBen Widawsky2013-10-271-3/+0
* | drm/i915: Convert straggling MCHBAR registersBen Widawsky2013-10-271-4/+4
* | drm/i915: Wire up gen2 CRC supportDaniel Vetter2013-10-211-0/+1
* | drm/i915: Fix PIPE_CRC_CTL for vlvDaniel Vetter2013-10-211-2/+1
* | drm/i915: CRC source selection #defines for gmch/vlv chipsDaniel Vetter2013-10-211-0/+22
* | drm/i915: Adjust CRC capture for pre-gen5/vlvDaniel Vetter2013-10-211-15/+15
* | drm/i915: crc support for hswDaniel Vetter2013-10-181-0/+1
* | drm/i915: wire up CRC interrupt for ilk/snbDaniel Vetter2013-10-181-0/+2
* | drm/i915: add CRC #defines for ilk/snbDaniel Vetter2013-10-181-11/+35
* | drm/i915: set HDMI pixel clock in audio configurationJani Nikula2013-10-181-1/+11
* | drm/i915: Expose latest 200 CRC value for pipe through debugfsShuang He2013-10-161-1/+35
* | drm/i915: Adjust watermark register masksVille Syrjälä2013-10-151-5/+5
* | drm/i915: Fix VLV frame counter registersVille Syrjälä2013-10-111-8/+8
* | drm/i915/vlv: Turn off power gate for BIOS-less system.Chon Ming Lee2013-10-041-0/+9
* | drm/i915/vlv: reset DPIO on load and resume v2Jesse Barnes2013-10-041-1/+1
* | drm/i915: Tweak RPS thresholds to more aggressively downclockChris Wilson2013-10-031-1/+1
* | drm/i915/vlv: use correct units for rc6 residency v2Jesse Barnes2013-10-011-0/+3
* | drm/i915/vlv: use lower precision RC6 counterJesse Barnes2013-10-011-0/+4
* | drm/i915: Program GMBUS Frequency based on the CDCLK for VLV.Chon Ming Lee2013-10-011-0/+8
* | drm/i915: precendence bug in GT_PARITY_ERROR()Dan Carpenter2013-10-011-1/+1
* | drm/i915: Calculate PSR register offsets from base + genBen Widawsky2013-10-011-10/+11
* | drm/i915: Add second slice l3 remappingBen Widawsky2013-09-191-0/+7
* | drm/i915: write D_COMP using the mailboxPaulo Zanoni2013-09-191-0/+4
* | drm/i915: Fix port_clock and adjusted_mode.clock readout all overVille Syrjälä2013-09-161-0/+1
* | drm/i915: clean up power sequencing register port select definitionsJani Nikula2013-09-061-6/+2
* | drm/i915: Report enabled slices on Haswell GT3Rodrigo Vivi2013-09-041-0/+5
* | drm/i915: add VLV DSI PLL Calculationsymohanma2013-09-041-0/+32
OpenPOWER on IntegriCloud