summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
* clk: npcm7xx: fix return value check in npcm7xx_clk_init()Wei Yongjun2018-05-181-1/+1
* clk: aspeed: Add 24MHz fixed clockLei YU2018-05-181-1/+7
* clk: aspeed: Fix reset assert logicJae Hyun Yoo2018-04-261-1/+1
* clk: aspeed: Support second reset registerJoel Stanley2018-04-191-8/+36
* clk: npcm7xx: add clock controllerTali Perry2018-04-112-0/+723
* clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as criticalJoel Stanley2018-03-281-2/+2
* clk: aspeed: Fix is_enabled for certain clocksEddie James2018-03-131-1/+2
* clk: aspeed: Prevent reset if clock is enabledEddie James2018-03-081-2/+13
* clk: aspeed: Handle inverse polarity of USB port 1 clock gateBenjamin Herrenschmidt2018-02-201-3/+12
* clk: aspeed: Fix return value check in aspeed_cc_init()Wei Yongjun2018-02-201-1/+1
* clk: aspeed: Use mdelay instead of msleepJoel Stanley2018-02-201-3/+2
* clk: aspeed: Add number of clocks defineJoel Stanley2018-01-181-0/+2
* Merge tag 'v4.13.16' into dev-4.13Joel Stanley2017-11-281-0/+15
|\
| * clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycleMarek Szyprowski2017-10-121-0/+15
* | clk: aspeed: Pull in latest version of driverJoel Stanley2017-11-271-34/+2
* | clk: aspeed: Add reset controllerJoel Stanley2017-10-091-1/+81
* | clk: aspeed: Register gated clocksJoel Stanley2017-10-091-0/+130
* | clk: aspeed: Add platform driver and register PLLsJoel Stanley2017-10-091-0/+163
* | clk: aspeed: Register core clocksJoel Stanley2017-10-091-0/+177
* | clk: Add clock driver for ASPEED BMC SoCsJoel Stanley2017-10-093-0/+161
|/
* clk: keystone: sci-clk: Fix sci_clk_getTero Kristo2017-08-021-24/+42
* Merge tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/...Stephen Boyd2017-08-021-1/+1
|\
| * clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clockMaxime Ripard2017-07-241-1/+1
* | Merge tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-...Stephen Boyd2017-08-024-0/+18
|\ \
| * | clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet2017-08-014-0/+18
| |/
* | clk: samsung: exynos5420: The EPLL rate table correctionsSylwester Nawrocki2017-07-311-8/+8
* | clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione2017-07-181-0/+7
* | clk: gemini: Fix reset regressionLinus Walleij2017-07-171-0/+14
|/
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2017-07-155-0/+115
|\
| * clk: boston: Add a driver for MIPS Boston board clocksPaul Burton2017-07-115-0/+115
* | clk: gemini: Read status before using the valueJoel Stanley2017-06-291-0/+1
* | clk: scpi: error when clock fails to registerJerome Brunet2017-06-291-3/+5
* | clk: at91: Add sama5d2 suspend/resumeAlexandre Belloni2017-06-294-1/+140
* | clk: keystone: TI_SCI_PROTOCOL is needed for clk driverArnd Bergmann2017-06-221-1/+2
* | clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLLKrzysztof Kozlowski2017-06-221-0/+1
* | clk: uniphier: provide NAND controller clock rateMasahiro Yamada2017-06-211-4/+11
* | clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue2017-06-211-0/+21
* | clk: Add Gemini SoC clock controllerLinus Walleij2017-06-213-0/+464
* | clk: iproc: Remove __init marking on iproc_pll_clk_setup()Stephen Boyd2017-06-211-6/+6
* | clk: bcm: Add clocks for Stingray SOCSandeep Tripathy2017-06-193-0/+336
* | clk: mediatek: export cpu multiplexer clock for MT8173 SoCsSean Wang2017-06-191-0/+23
* | clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang2017-06-191-0/+8
* | clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't workSean Wang2017-06-193-1/+151
* | clk: renesas: cpg-mssr: Use of_device_get_match_data() helperGeert Uytterhoeven2017-06-191-1/+1
* | clk: hi6220: add acpu clockZhangfei Gao2017-06-191-0/+22
* | clk: zx296718: export I2S mux clocksShawn Guo2017-06-191-4/+4
* | clk: imx7d: create clocks behind rawnand clock gateStefan Agner2017-06-191-2/+4
* | clk: hi3660: Set PPLL2 to 2880MZhong Kaihua2017-06-191-2/+2
* | clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun2017-06-191-0/+40
* | clk: hi3660: fix wrong parent name of clk_mux_sysbusChen Jun2017-06-191-2/+4
OpenPOWER on IntegriCloud