Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | clk: sprd: add divider clock support | Chunyan Zhang | 2017-12-21 | 1 | -0/+75 |
This is a feature that can also be found in sprd composite clocks, provide a bunch of helpers that can be reused later on. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |