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path: root/drivers/clk/renesas/rcar-gen3-cpg.c
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*-. Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and ↵Stephen Boyd2018-12-141-22/+33
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-rockchip' into clk-next * clk-renesas: clk: renesas: rcar-gen3: Add HS400 quirk for SD clock clk: renesas: rcar-gen3: Add documentation for SD clocks clk: renesas: rcar-gen3: Set state when registering SD clocks clk: renesas: r8a77995: Simplify PLL3 multiplier/divider clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77990: Correct parent clock of DU clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a774a1: Add CPEX clock dt-bindings: clock: r8a7796: Remove CSIREF clock dt-bindings: clock: r8a7795: Remove CSIREF clock clk: renesas: Mark rza2_cpg_clk_register static clk: renesas: r7s9210: Add USB clocks clk: renesas: r8a77970: Add RPC clocks clk: renesas: r7s9210: Add SDHI clocks * clk-allwinner: clk: sunxi-ng: a64: Allow parent change for VE clock clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL clk: sunxi-ng: h3: Allow parent change for ve clock clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: h6: Set video PLLs limits clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock * clk-tegra: clk: tegra: Return the exact clock rate from clk_round_rate clk: tegra30: Use Tegra CPU powergate helper function soc/tegra: pmc: Drop SMP dependency from CPU APIs clk: tegra: Fix maximum audio sync clock for Tegra124/210 clk: tegra: get rid of duplicate defines clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC clk: tegra20: Turn EMC clock gate into divider * clk-meson: (25 commits) clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: Mark some things static clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width clk: meson: meson8b: add the CPU clock post divider clocks clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 clk: meson: clk-regmap: add read-only gate ops clk: meson: meson8b: allow changing the CPU clock tree clk: meson: meson8b: run from the XTAL when changing the CPU frequency clk: meson: meson8b: add support for more M/N values in sys_pll clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel clk: meson: clk-pll: check if the clock is already enabled clk: meson: meson8b: fix the width of the cpu_scale_div clock clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table clk: meson: meson8b: use the HHI syscon if available dt-bindings: clock: meson8b: use the registers from the HHI syscon ... * clk-rockchip: clk: rockchip: add clock-id to gate of ACODEC for rk3328 clk: rockchip: add clock ID of ACODEC for rk3328 clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328 clk: rockchip: fix I2S1 clock gate register for rk3328 clk: rockchip: make rk3188 hclk_vio_bus critical clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering clk: rockchip: fix rk3188 sclk_smc gate data clk: rockchip: fix typo in rk3188 spdif_frac parent
| * | clk: renesas: rcar-gen3: Add HS400 quirk for SD clockNiklas Söderlund2018-12-071-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400 needs a quirk to function properly. The reason for the quirk is that there are two settings which produces same divider value for the SDn clock. On the effected boards the one currently selected results in HS400 not working. This change uses the same method as the Gen2 CPG driver and simply ignores the first clock setting as this is the offending one when selecting the settings. Which of the two possible settings is used have no effect for SDR104. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | clk: renesas: rcar-gen3: Add documentation for SD clocksNiklas Söderlund2018-12-071-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document the known use cases of the different clock settings. This is useful as different SoC and ES versions use different settings to do the same thing as there is more than one combination to achieve the same SDn clock speed. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | clk: renesas: rcar-gen3: Set state when registering SD clocksNiklas Söderlund2018-12-071-12/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver tries to figure out which state a SD clock is in when the clock is registered, instead of setting a known state. This can be problematic for two reasons. 1. If the clock driver can't figure out the state of the clock, registration of the clock fails, and setting of a known state by a clock user is not possible. 2. The state of the clock depends on if and how the bootloader configured it. The driver only checks that the rate is known, not if the clock is stopped or not for example. Fix this by setting a known state and making sure the clock is stopped. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* / clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd2018-12-101-1/+1
|/ | | | | | | | | | | This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: <linux-renesas-soc@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-181-9/+31
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
| * clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven2018-08-271-6/+4
| | | | | | | | | | | | | | | | | | Make the existing support for selecting between clean and SSCG clocks using MD12 more generic, to allow using other mode pins for arbitrary clock selection. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: rcar-gen3: Add support for RCKSEL clock selectionGeert Uytterhoeven2018-08-271-3/+20
| | | | | | | | | | | | | | | | Add a clock type and macro for defining clocks where the parent and divider are selected based on the value of the RCKCR.CKSEL bit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: rcar-gen3: Add support for OSC EXTAL predividerGeert Uytterhoeven2018-08-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a clock type and macro for defining clocks using the OSC EXTAL predivider combined with a fixed divider. On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and thus must be specified in the configuration structure. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* | clk: renesas: use SPDX identifier for Renesas driversWolfram Sang2018-08-301-4/+1
|/ | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: renesas: rcar-gen3: Always use readl()/writel()Geert Uytterhoeven2018-03-211-7/+7
| | | | | | | | | | | | The R-Car Gen3 CPG/MSSR driver (again) uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use readl()/writel()"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Add Z2 clock divider supportTakeshi Kihara2018-02-121-6/+16
| | | | | | | | This patch adds Z2 clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Add Z clock divider supportTakeshi Kihara2018-02-121-0/+133
| | | | | | | | This patch adds Z clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Restore R clock during resumeGeert Uytterhoeven2017-10-201-2/+11
| | | | | | | | | On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing clock configuration. Register a notifier to save/restore the RCKCR register during system suspend/resume. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* clk: renesas: rcar-gen3: Restore SDHI clocks during resumeGeert Uytterhoeven2017-10-201-13/+50
| | | | | | | | | | | | | On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing clock configuration. Register a notifier to save/restore SDHI clock registers during system suspend/resume. This is implemented using the cpg_simple_notifier abstraction, which can be reused for others clocks that just need to save/restore a single register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* clk: renesas: cpg-mssr: Add support to restore core clocks during resumeGeert Uytterhoeven2017-10-201-1/+2
| | | | | | | | | | | | | On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly losing clock configuration. Hence add a notifier chain that can be used by core clocks to save/restore clock state during system suspend/resume. The implementation of the actual clock state save/restore operations is clock-specific, and to be registered with the notifier chain in the SoC or family-specific cpg_mssr_info.cpg_clk_register() callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven2017-08-161-1/+19
| | | | | | | | | | | | | On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car D3), a peripheral clock divider has been added, to select between clean and spread spectrum parents. Add a new clock type to the R-Car Gen3 driver core to handle this. To avoid increasing the size of struct cpg_core_clk, both parents and dividers are stored in the existing parent resp. div fields. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven2017-08-161-0/+2
| | | | | | | | | | | On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider value different from one. Extend struct rcar_gen3_cpg_pll_config to handle this. As all multipliers and dividers are small, table size increase can be kept limited by storing them in u8s instead of unsigned ints, which saves ca. 0.5 KiB for a generic kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang2017-07-191-26/+20
| | | | | | | | | Do the checks for accessing the SD divider table only when the rate gets updated, namely on init and set_rate. In all other cases, reuse the last value. This simplifies code, runtime load, and error reporting. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang2017-07-191-2/+1
| | | | | | | 'rate' is not used, so we can use 'parent_rate' directly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0Geert Uytterhoeven2017-03-301-11/+27
| | | | | | | | | | | | Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28. Add support for that, but retain the old behavior for R-Car H3 ES1.x and M3-W ES1.0 using a quirk. Inspired by a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
* clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0Geert Uytterhoeven2017-03-211-0/+24
| | | | | | | | | | Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and PLL4 clock frequencies are off by a factor of two. Inspired by a patch by Dien Pham in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Dien Pham <dien.pham.ry@renesas.com>
* clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven2017-03-211-1/+3
| | | | | | | | Pass the mode pin states from the SoC-specific CPG/MSSR driver to the R-Car Gen3 CPG driver core, as their state will be needed to make some core clock configuration decisions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Merge branch 'rcar-rst' into clk-renesas-for-v4.10Geert Uytterhoeven2016-11-021-17/+0
|\ | | | | | | soc: renesas: Add R-Car RST driver for obtaining mode pin state
| * clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()Geert Uytterhoeven2016-11-021-17/+0
| | | | | | | | | | | | | | | | | | All R-Car Gen3 clock drivers now obtain the values of the mode pins from the R-Car RST driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* | clk: renesas: rcar-gen3-cpg: Always use readl()/writel()Geert Uytterhoeven2016-10-171-7/+7
|/ | | | | | | | | The R-Car Gen3 CPG/MSSR driver uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: cpg-mssr: Extract common R-Car Gen3 support codeGeert Uytterhoeven2016-06-061-0/+359
Extract the code to support parts common to all members of the R-Car Gen3 SoC family into a separate file, to ease sharing among SoC-specific drivers. Note that while the cpg_pll_configs[] arrays and the selection of the config based on the MODE bits are identical on R-Car H3 and R-Car M3-W, they are not common, and may be different on other R-Car Gen3 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
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