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path: root/drivers/clk/meson/gxbb.c
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* clk: meson: add gen_clkJerome Brunet2018-07-091-0/+66
* clk: meson: stop rate propagation for audio clocksJerome Brunet2018-07-091-9/+7
* clk: meson: remove obsolete register accessJerome Brunet2018-07-091-34/+2
* clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong2018-06-191-0/+1
* clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-181-14/+1
* clk: meson: gxbb: add the video decoder clocksMaxime Jourdan2018-05-151-0/+114
* clk: meson: Drop unused local variable and add staticStephen Boyd2018-03-141-2/+2
* clk: meson: clean-up clk81 clocksJerome Brunet2018-03-131-4/+2
* clk: meson: add fdiv clock gatesJerome Brunet2018-03-131-10/+90
* clk: meson: add mpll pre-dividerJerome Brunet2018-03-131-3/+20
* clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet2018-03-131-1/+6
* clk: meson: remove special gp0 lock loopJerome Brunet2018-03-131-1/+0
* clk: meson: poke pll CNTL lastJerome Brunet2018-03-131-2/+2
* clk: meson: use hhi syscon if availableJerome Brunet2018-03-131-11/+28
* clk: meson: split divider and gate part of mpllJerome Brunet2018-03-131-21/+57
* clk: meson: migrate plls clocks to clk_regmapJerome Brunet2018-03-131-185/+239
* clk: meson: migrate the audio divider clock to clk_regmapJerome Brunet2018-03-131-21/+9
* clk: meson: migrate mplls clocks to clk_regmapJerome Brunet2018-03-131-84/+77
* clk: meson: migrate muxes to clk_regmapJerome Brunet2018-03-131-160/+150
* clk: meson: migrate dividers to clk_regmapJerome Brunet2018-03-131-109/+108
* clk: meson: migrate gates to clk_regmapJerome Brunet2018-03-131-129/+137
* clk: meson: add regmap to the clock controllersJerome Brunet2018-03-131-10/+23
* clk: meson: remove obsolete commentsJerome Brunet2018-03-131-6/+0
* clk: meson: only one loop index is necessary in probeJerome Brunet2018-03-131-7/+6
* clk: meson: use devm_of_clk_add_hw_providerJerome Brunet2018-03-131-2/+3
* clk: meson: use dev pointer where possibleJerome Brunet2018-03-131-1/+1
* clk: meson: gxbb: add the fractional part of the fixed_pllJerome Brunet2018-02-121-0/+5
* clk: meson: fix rate calculation of plls with a fractional partJerome Brunet2018-02-121-1/+13
* clk: meson: add the gxl hdmi pllJerome Brunet2018-02-121-2/+48
* clk: meson: add od3 to the pll driverJerome Brunet2018-02-121-0/+5
* clk: meson: remove useless pll rate params tablesJerome Brunet2018-02-121-94/+0
* clk: meson: make the spinlock naming more specificYixun Lan2017-12-141-56/+56
* clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocksJerome Brunet2017-12-081-13/+3
* clk: meson: gxbb: fix wrong clock for SARADC/SANAYixun Lan2017-11-271-2/+2
* clk: meson: gxbb: Add VPU and VAPB clocks dataNeil Armstrong2017-10-201-0/+292
* Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd2017-08-231-4/+185
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| * clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet2017-08-041-0/+177
| * clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet2017-08-041-3/+4
| * clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet2017-08-041-1/+2
| * clk: meson: gxbb: fix protection against undefined clksJerome Brunet2017-08-041-0/+2
* | clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet2017-08-011-0/+5
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* Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ...Stephen Boyd2017-06-161-5/+8
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| * clk: meson: gxbb: add all clk81 parentsJerome Brunet2017-06-161-5/+8
* | clk: meson-gxbb: Add const to some parent name arraysStephen Boyd2017-06-021-3/+3
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* clk: meson-gxbb: Add EE 32K Clock for CECNeil Armstrong2017-05-291-0/+54
* clk: gxbb: remove CLK_IGNORE_UNUSED from clk81Jerome Brunet2017-05-291-1/+1
* clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driverMartin Blumenstingl2017-05-291-61/+3
* clk: meson: gxbb: add cts_i958 clockJerome Brunet2017-04-071-0/+21
* clk: meson: gxbb: add cts_mclk_i958Jerome Brunet2017-04-071-0/+52
* clk: meson: gxbb: add cts_amclkJerome Brunet2017-04-071-0/+67
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