| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: meson: add axg audio sclk divider driver | Jerome Brunet | 2018-07-09 | 1 | -0/+8 |
| | | | | | | | | | | | | | | | | Add a driver to control the clock divider found in the sample clock generator of the axg audio clock controller. The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> | ||||
| * | clk: meson: add triple phase clock driver | Jerome Brunet | 2018-07-09 | 1 | -0/+20 |
| Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> | |||||
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index : talos-obmc-linux | |
| Talos™ II Linux sources for OpenBMC | Raptor Computing Systems |
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