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* dt-bindings: iio: adc: meson-saradc: add temperature sensor supportMartin Blumenstingl2018-11-111-0/+6
| | | | | | | | | | | | The 32-bit Meson8 SoC can use the SAR ADC to read the chip temperature. This requires setting the correct TSC (temperature sensor coefficient), which is programmed into the eFuse during the manufacturing process. Meson8b and Meson8m2 are not supported yet because they have a 5-bit TSC and only the first four bits are stored inside the SAR ADC registers. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* dt-bindings: iio: adc: add Meson8m2 supportMartin Blumenstingl2018-07-231-0/+1
| | | | | | | | | The Amlogic Meson SAR ADC implementation on the Meson8m2 SoC is identical to the Meson8b variant. Add a compatible string to indicate that we support the SAR ADC on the Meson8m2 SoC. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* dt-bindings: iio: adc: document the Meson AXG supportXingyu Chen2018-03-301-0/+1
| | | | | | | | | Update the documentation to expicitly support the Meson-AXG SoC. Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* dt-bindings: iio: adc: update the doc for SAR ADCXingyu Chen2017-12-021-1/+0
| | | | | | | | | Update the doc as the SAR ADC modules doesn't require "sana" clock. Singed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* dt-bindings: iio: adc: add Meson8 and Meson8b supportMartin Blumenstingl2017-05-071-0/+2
| | | | | | | | | | | | The Amlogic Meson SAR ADC driver can be used on Meson8 and Meson8b (probably on earlier SoC generations as well, but I don't have any hardware available for testing that). Add a separate compatible for Meson8 and Meson8b because it does not need any of the BL30 magic (unlike the GX SoCs). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* iio: adc: meson-saradc: switch from polling to interrupt modeHeiner Kallweit2017-02-191-0/+2
| | | | | | | | | | | Switch from polling to interrupt mode. Successfully tested on a S905GXBB-based Odroid C2. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* Documentation: dt-bindings: add the Amlogic Meson SAR ADC documentationMartin Blumenstingl2017-01-281-0/+32
This adds the devicetree binding documentation for the SAR ADC found in Amlogic Meson SoCs. Currently only the GXBB, GXL and GXM SoCs are supported. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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