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path: root/drivers/gpu/drm/nouveau/nvkm/subdev
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-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c34
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c26
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c84
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c28
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c80
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c38
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c54
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h2
15 files changed, 204 insertions, 204 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
index 5cc7dd24a213..4338e437bcc3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
@@ -29,47 +29,47 @@
int
_nvkm_devinit_fini(struct nvkm_object *object, bool suspend)
{
- struct nvkm_devinit *devinit = (void *)object;
+ struct nvkm_devinit *init = (void *)object;
/* force full reinit on resume */
if (suspend)
- devinit->post = true;
+ init->post = true;
/* unlock the extended vga crtc regs */
- nv_lockvgac(devinit, false);
+ nv_lockvgac(init, false);
- return nvkm_subdev_fini(&devinit->base, suspend);
+ return nvkm_subdev_fini(&init->subdev, suspend);
}
int
_nvkm_devinit_init(struct nvkm_object *object)
{
struct nvkm_devinit_impl *impl = (void *)object->oclass;
- struct nvkm_devinit *devinit = (void *)object;
+ struct nvkm_devinit *init = (void *)object;
int ret;
- ret = nvkm_subdev_init(&devinit->base);
+ ret = nvkm_subdev_init(&init->subdev);
if (ret)
return ret;
- ret = impl->post(&devinit->base, devinit->post);
+ ret = impl->post(&init->subdev, init->post);
if (ret)
return ret;
if (impl->disable)
- nv_device(devinit)->disable_mask |= impl->disable(devinit);
+ nv_device(init)->disable_mask |= impl->disable(init);
return 0;
}
void
_nvkm_devinit_dtor(struct nvkm_object *object)
{
- struct nvkm_devinit *devinit = (void *)object;
+ struct nvkm_devinit *init = (void *)object;
/* lock crtc regs */
- nv_lockvgac(devinit, true);
+ nv_lockvgac(init, true);
- nvkm_subdev_destroy(&devinit->base);
+ nvkm_subdev_destroy(&init->subdev);
}
int
@@ -78,18 +78,18 @@ nvkm_devinit_create_(struct nvkm_object *parent, struct nvkm_object *engine,
{
struct nvkm_devinit_impl *impl = (void *)oclass;
struct nvkm_device *device = nv_device(parent);
- struct nvkm_devinit *devinit;
+ struct nvkm_devinit *init;
int ret;
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "DEVINIT",
"init", size, pobject);
- devinit = *pobject;
+ init = *pobject;
if (ret)
return ret;
- devinit->post = nvkm_boolopt(device->cfgopt, "NvForcePost", false);
- devinit->meminit = impl->meminit;
- devinit->pll_set = impl->pll_set;
- devinit->mmio = impl->mmio;
+ init->post = nvkm_boolopt(device->cfgopt, "NvForcePost", false);
+ init->meminit = impl->meminit;
+ init->pll_set = impl->pll_set;
+ init->mmio = impl->mmio;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
index ca776ce75f4f..69f28feda861 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
@@ -29,9 +29,9 @@
static u64
g84_devinit_disable(struct nvkm_devinit *devinit)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- u32 r001540 = nv_rd32(priv, 0x001540);
- u32 r00154c = nv_rd32(priv, 0x00154c);
+ struct nv50_devinit *init = (void *)devinit;
+ u32 r001540 = nv_rd32(init, 0x001540);
+ u32 r00154c = nv_rd32(init, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
index d29bacee65ee..06a269c0ac05 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
@@ -29,9 +29,9 @@
static u64
g98_devinit_disable(struct nvkm_devinit *devinit)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- u32 r001540 = nv_rd32(priv, 0x001540);
- u32 r00154c = nv_rd32(priv, 0x00154c);
+ struct nv50_devinit *init = (void *)devinit;
+ u32 r001540 = nv_rd32(init, 0x001540);
+ u32 r00154c = nv_rd32(init, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
index c61102f70805..b6eb2540fcbd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
@@ -31,8 +31,8 @@
int
gf100_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nv50_devinit *init = (void *)devinit;
+ struct nvkm_bios *bios = nvkm_bios(init);
struct nvbios_pll info;
int N, fN, M, P;
int ret;
@@ -50,12 +50,12 @@ gf100_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
case PLL_VPLL1:
case PLL_VPLL2:
case PLL_VPLL3:
- nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100);
- nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M);
- nv_wr32(priv, info.reg + 0x10, fN << 16);
+ nv_mask(init, info.reg + 0x0c, 0x00000000, 0x00000100);
+ nv_wr32(init, info.reg + 0x04, (P << 16) | (N << 8) | M);
+ nv_wr32(init, info.reg + 0x10, fN << 16);
break;
default:
- nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
+ nv_warn(init, "0x%08x/%dKhz unimplemented\n", type, freq);
ret = -EINVAL;
break;
}
@@ -66,8 +66,8 @@ gf100_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
static u64
gf100_devinit_disable(struct nvkm_devinit *devinit)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- u32 r022500 = nv_rd32(priv, 0x022500);
+ struct nv50_devinit *init = (void *)devinit;
+ u32 r022500 = nv_rd32(init, 0x022500);
u64 disable = 0ULL;
if (r022500 & 0x00000001)
@@ -96,18 +96,18 @@ gf100_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_object **pobject)
{
struct nvkm_devinit_impl *impl = (void *)oclass;
- struct nv50_devinit_priv *priv;
+ struct nv50_devinit *init;
u64 disable;
int ret;
- ret = nvkm_devinit_create(parent, engine, oclass, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_devinit_create(parent, engine, oclass, &init);
+ *pobject = nv_object(init);
if (ret)
return ret;
- disable = impl->disable(&priv->base);
+ disable = impl->disable(&init->base);
if (disable & (1ULL << NVDEV_ENGINE_DISP))
- priv->base.post = true;
+ init->base.post = true;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
index 87ca0ece37b4..16150177f6c6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
@@ -29,9 +29,9 @@
u64
gm107_devinit_disable(struct nvkm_devinit *devinit)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- u32 r021c00 = nv_rd32(priv, 0x021c00);
- u32 r021c04 = nv_rd32(priv, 0x021c04);
+ struct nv50_devinit *init = (void *)devinit;
+ u32 r021c00 = nv_rd32(init, 0x021c00);
+ u32 r021c04 = nv_rd32(init, 0x021c04);
u64 disable = 0ULL;
if (r021c00 & 0x00000001)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
index 1076fcf0d716..3c513be9817f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
@@ -28,69 +28,69 @@
#include <subdev/bios/pmu.h>
static void
-pmu_code(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len, bool sec)
+pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
{
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(init);
int i;
- nv_wr32(priv, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
+ nv_wr32(init, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
for (i = 0; i < len; i += 4) {
if ((i & 0xff) == 0)
- nv_wr32(priv, 0x10a188, (pmu + i) >> 8);
- nv_wr32(priv, 0x10a184, nv_ro32(bios, img + i));
+ nv_wr32(init, 0x10a188, (pmu + i) >> 8);
+ nv_wr32(init, 0x10a184, nv_ro32(bios, img + i));
}
while (i & 0xff) {
- nv_wr32(priv, 0x10a184, 0x00000000);
+ nv_wr32(init, 0x10a184, 0x00000000);
i += 4;
}
}
static void
-pmu_data(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len)
+pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len)
{
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(init);
int i;
- nv_wr32(priv, 0x10a1c0, 0x01000000 | pmu);
+ nv_wr32(init, 0x10a1c0, 0x01000000 | pmu);
for (i = 0; i < len; i += 4)
- nv_wr32(priv, 0x10a1c4, nv_ro32(bios, img + i));
+ nv_wr32(init, 0x10a1c4, nv_ro32(bios, img + i));
}
static u32
-pmu_args(struct nv50_devinit_priv *priv, u32 argp, u32 argi)
+pmu_args(struct nv50_devinit *init, u32 argp, u32 argi)
{
- nv_wr32(priv, 0x10a1c0, argp);
- nv_wr32(priv, 0x10a1c0, nv_rd32(priv, 0x10a1c4) + argi);
- return nv_rd32(priv, 0x10a1c4);
+ nv_wr32(init, 0x10a1c0, argp);
+ nv_wr32(init, 0x10a1c0, nv_rd32(init, 0x10a1c4) + argi);
+ return nv_rd32(init, 0x10a1c4);
}
static void
-pmu_exec(struct nv50_devinit_priv *priv, u32 init_addr)
+pmu_exec(struct nv50_devinit *init, u32 init_addr)
{
- nv_wr32(priv, 0x10a104, init_addr);
- nv_wr32(priv, 0x10a10c, 0x00000000);
- nv_wr32(priv, 0x10a100, 0x00000002);
+ nv_wr32(init, 0x10a104, init_addr);
+ nv_wr32(init, 0x10a10c, 0x00000000);
+ nv_wr32(init, 0x10a100, 0x00000002);
}
static int
-pmu_load(struct nv50_devinit_priv *priv, u8 type, bool post,
+pmu_load(struct nv50_devinit *init, u8 type, bool post,
u32 *init_addr_pmu, u32 *args_addr_pmu)
{
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(init);
struct nvbios_pmuR pmu;
if (!nvbios_pmuRm(bios, type, &pmu)) {
- nv_error(priv, "VBIOS PMU fuc %02x not found\n", type);
+ nv_error(init, "VBIOS PMU fuc %02x not found\n", type);
return -EINVAL;
}
if (!post)
return 0;
- pmu_code(priv, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false);
- pmu_code(priv, pmu.code_addr_pmu, pmu.code_addr, pmu.code_size, true);
- pmu_data(priv, pmu.data_addr_pmu, pmu.data_addr, pmu.data_size);
+ pmu_code(init, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false);
+ pmu_code(init, pmu.code_addr_pmu, pmu.code_addr, pmu.code_size, true);
+ pmu_data(init, pmu.data_addr_pmu, pmu.data_addr, pmu.data_size);
if (init_addr_pmu) {
*init_addr_pmu = pmu.init_addr_pmu;
@@ -98,63 +98,63 @@ pmu_load(struct nv50_devinit_priv *priv, u8 type, bool post,
return 0;
}
- return pmu_exec(priv, pmu.init_addr_pmu), 0;
+ return pmu_exec(init, pmu.init_addr_pmu), 0;
}
static int
gm204_devinit_post(struct nvkm_subdev *subdev, bool post)
{
- struct nv50_devinit_priv *priv = (void *)nvkm_devinit(subdev);
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nv50_devinit *init = (void *)nvkm_devinit(subdev);
+ struct nvkm_bios *bios = nvkm_bios(init);
struct bit_entry bit_I;
- u32 init, args;
+ u32 exec, args;
int ret;
if (bit_entry(bios, 'I', &bit_I) || bit_I.version != 1 ||
bit_I.length < 0x1c) {
- nv_error(priv, "VBIOS PMU init data not found\n");
+ nv_error(init, "VBIOS PMU init data not found\n");
return -EINVAL;
}
/* reset PMU and load init table parser ucode */
if (post) {
- nv_mask(priv, 0x000200, 0x00002000, 0x00000000);
- nv_mask(priv, 0x000200, 0x00002000, 0x00002000);
- nv_rd32(priv, 0x000200);
- while (nv_rd32(priv, 0x10a10c) & 0x00000006) {
+ nv_mask(init, 0x000200, 0x00002000, 0x00000000);
+ nv_mask(init, 0x000200, 0x00002000, 0x00002000);
+ nv_rd32(init, 0x000200);
+ while (nv_rd32(init, 0x10a10c) & 0x00000006) {
}
}
- ret = pmu_load(priv, 0x04, post, &init, &args);
+ ret = pmu_load(init, 0x04, post, &exec, &args);
if (ret)
return ret;
/* upload first chunk of init data */
if (post) {
- u32 pmu = pmu_args(priv, args + 0x08, 0x08);
+ u32 pmu = pmu_args(init, args + 0x08, 0x08);
u32 img = nv_ro16(bios, bit_I.offset + 0x14);
u32 len = nv_ro16(bios, bit_I.offset + 0x16);
- pmu_data(priv, pmu, img, len);
+ pmu_data(init, pmu, img, len);
}
/* upload second chunk of init data */
if (post) {
- u32 pmu = pmu_args(priv, args + 0x08, 0x10);
+ u32 pmu = pmu_args(init, args + 0x08, 0x10);
u32 img = nv_ro16(bios, bit_I.offset + 0x18);
u32 len = nv_ro16(bios, bit_I.offset + 0x1a);
- pmu_data(priv, pmu, img, len);
+ pmu_data(init, pmu, img, len);
}
/* execute init tables */
if (post) {
- nv_wr32(priv, 0x10a040, 0x00005000);
- pmu_exec(priv, init);
- while (!(nv_rd32(priv, 0x10a040) & 0x00002000)) {
+ nv_wr32(init, 0x10a040, 0x00005000);
+ pmu_exec(init, exec);
+ while (!(nv_rd32(init, 0x10a040) & 0x00002000)) {
}
}
/* load and execute some other ucode image (bios therm?) */
- return pmu_load(priv, 0x01, post, NULL, NULL);
+ return pmu_load(init, 0x01, post, NULL, NULL);
}
struct nvkm_oclass *
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
index 6a3e8d4efed7..ffe3828c23c8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
@@ -31,8 +31,8 @@
int
gt215_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nv50_devinit *init = (void *)devinit;
+ struct nvkm_bios *bios = nvkm_bios(init);
struct nvbios_pll info;
int N, fN, M, P;
int ret;
@@ -48,13 +48,13 @@ gt215_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
switch (info.type) {
case PLL_VPLL0:
case PLL_VPLL1:
- nv_wr32(priv, info.reg + 0, 0x50000610);
- nv_mask(priv, info.reg + 4, 0x003fffff,
+ nv_wr32(init, info.reg + 0, 0x50000610);
+ nv_mask(init, info.reg + 4, 0x003fffff,
(P << 16) | (M << 8) | N);
- nv_wr32(priv, info.reg + 8, fN);
+ nv_wr32(init, info.reg + 8, fN);
break;
default:
- nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
+ nv_warn(init, "0x%08x/%dKhz unimplemented\n", type, freq);
ret = -EINVAL;
break;
}
@@ -65,9 +65,9 @@ gt215_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
static u64
gt215_devinit_disable(struct nvkm_devinit *devinit)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- u32 r001540 = nv_rd32(priv, 0x001540);
- u32 r00154c = nv_rd32(priv, 0x00154c);
+ struct nv50_devinit *init = (void *)devinit;
+ u32 r001540 = nv_rd32(init, 0x001540);
+ u32 r00154c = nv_rd32(init, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
@@ -101,7 +101,7 @@ gt215_devinit_mmio_part[] = {
static u32
gt215_devinit_mmio(struct nvkm_devinit *devinit, u32 addr)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
+ struct nv50_devinit *init = (void *)devinit;
u32 *mmio = gt215_devinit_mmio_part;
/* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP
@@ -113,7 +113,7 @@ gt215_devinit_mmio(struct nvkm_devinit *devinit, u32 addr)
*
* the binary driver avoids touching these registers at all, however,
* the video bios doesn't care and does what the scripts say. it's
- * presumed that the io-port access to priv registers isn't effected
+ * presumed that the io-port access to init registers isn't effected
* by the screw-up bug mentioned above.
*
* really, a new opcode should've been invented to handle these
@@ -122,9 +122,9 @@ gt215_devinit_mmio(struct nvkm_devinit *devinit, u32 addr)
while (mmio[0]) {
if (addr >= mmio[0] && addr <= mmio[1]) {
u32 part = (addr / mmio[2]) & 7;
- if (!priv->r001540)
- priv->r001540 = nv_rd32(priv, 0x001540);
- if (part >= hweight8((priv->r001540 >> 16) & 0xff))
+ if (!init->r001540)
+ init->r001540 = nv_rd32(init, 0x001540);
+ if (part >= hweight8((init->r001540 >> 16) & 0xff))
return ~0;
return addr;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
index 55cf48bbca1c..27085758b67b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
@@ -29,9 +29,9 @@
static u64
mcp89_devinit_disable(struct nvkm_devinit *devinit)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- u32 r001540 = nv_rd32(priv, 0x001540);
- u32 r00154c = nv_rd32(priv, 0x00154c);
+ struct nv50_devinit *init = (void *)devinit;
+ u32 r001540 = nv_rd32(init, 0x001540);
+ u32 r00154c = nv_rd32(init, 0x00154c);
u64 disable = 0;
if (!(r001540 & 0x40000000)) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
index 03a0da834244..28cb38160ce1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
@@ -35,23 +35,23 @@
static void
nv04_devinit_meminit(struct nvkm_devinit *devinit)
{
- struct nv04_devinit_priv *priv = (void *)devinit;
+ struct nv04_devinit *init = (void *)devinit;
u32 patt = 0xdeadbeef;
struct io_mapping *fb;
int i;
/* Map the framebuffer aperture */
- fb = fbmem_init(nv_device(priv));
+ fb = fbmem_init(nv_device(init));
if (!fb) {
- nv_error(priv, "failed to map fb\n");
+ nv_error(init, "failed to map fb\n");
return;
}
/* Sequencer and refresh off */
- nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
- nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
+ nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) | 0x20);
+ nv_mask(init, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
- nv_mask(priv, NV04_PFB_BOOT_0, ~0,
+ nv_mask(init, NV04_PFB_BOOT_0, ~0,
NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
NV04_PFB_BOOT_0_RAM_WIDTH_128 |
NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
@@ -62,49 +62,49 @@ nv04_devinit_meminit(struct nvkm_devinit *devinit)
fbmem_poke(fb, 0x400000, patt + 1);
if (fbmem_peek(fb, 0) == patt + 1) {
- nv_mask(priv, NV04_PFB_BOOT_0,
+ nv_mask(init, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_TYPE,
NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
- nv_mask(priv, NV04_PFB_DEBUG_0,
+ nv_mask(init, NV04_PFB_DEBUG_0,
NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
for (i = 0; i < 4; i++)
fbmem_poke(fb, 4 * i, patt);
if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))
- nv_mask(priv, NV04_PFB_BOOT_0,
+ nv_mask(init, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_WIDTH_128 |
NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
} else
if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {
- nv_mask(priv, NV04_PFB_BOOT_0,
+ nv_mask(init, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_WIDTH_128 |
NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
} else
if (fbmem_peek(fb, 0) != patt) {
if (fbmem_readback(fb, 0x800000, patt))
- nv_mask(priv, NV04_PFB_BOOT_0,
+ nv_mask(init, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
else
- nv_mask(priv, NV04_PFB_BOOT_0,
+ nv_mask(init, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
+ nv_mask(init, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
} else
if (!fbmem_readback(fb, 0x800000, patt)) {
- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
+ nv_mask(init, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
}
/* Refresh on, sequencer on */
- nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
- nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
+ nv_mask(init, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
+ nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) & ~0x20);
fbmem_fini(fb);
}
@@ -390,52 +390,52 @@ nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
int
nv04_devinit_fini(struct nvkm_object *object, bool suspend)
{
- struct nv04_devinit_priv *priv = (void *)object;
+ struct nv04_devinit *init = (void *)object;
int ret;
/* make i2c busses accessible */
- nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
+ nv_mask(init, 0x000200, 0x00000001, 0x00000001);
- ret = nvkm_devinit_fini(&priv->base, suspend);
+ ret = nvkm_devinit_fini(&init->base, suspend);
if (ret)
return ret;
/* unslave crtcs */
- if (priv->owner < 0)
- priv->owner = nv_rdvgaowner(priv);
- nv_wrvgaowner(priv, 0);
+ if (init->owner < 0)
+ init->owner = nv_rdvgaowner(init);
+ nv_wrvgaowner(init, 0);
return 0;
}
int
nv04_devinit_init(struct nvkm_object *object)
{
- struct nv04_devinit_priv *priv = (void *)object;
-
- if (!priv->base.post) {
- u32 htotal = nv_rdvgac(priv, 0, 0x06);
- htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8;
- htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4;
- htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10;
- htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11;
+ struct nv04_devinit *init = (void *)object;
+
+ if (!init->base.post) {
+ u32 htotal = nv_rdvgac(init, 0, 0x06);
+ htotal |= (nv_rdvgac(init, 0, 0x07) & 0x01) << 8;
+ htotal |= (nv_rdvgac(init, 0, 0x07) & 0x20) << 4;
+ htotal |= (nv_rdvgac(init, 0, 0x25) & 0x01) << 10;
+ htotal |= (nv_rdvgac(init, 0, 0x41) & 0x01) << 11;
if (!htotal) {
- nv_info(priv, "adaptor not initialised\n");
- priv->base.post = true;
+ nv_info(init, "adaptor not initialised\n");
+ init->base.post = true;
}
}
- return nvkm_devinit_init(&priv->base);
+ return nvkm_devinit_init(&init->base);
}
void
nv04_devinit_dtor(struct nvkm_object *object)
{
- struct nv04_devinit_priv *priv = (void *)object;
+ struct nv04_devinit *init = (void *)object;
/* restore vga owner saved at first init */
- nv_wrvgaowner(priv, priv->owner);
+ nv_wrvgaowner(init, init->owner);
- nvkm_devinit_destroy(&priv->base);
+ nvkm_devinit_destroy(&init->base);
}
int
@@ -443,15 +443,15 @@ nv04_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv04_devinit_priv *priv;
+ struct nv04_devinit *init;
int ret;
- ret = nvkm_devinit_create(parent, engine, oclass, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_devinit_create(parent, engine, oclass, &init);
+ *pobject = nv_object(init);
if (ret)
return ret;
- priv->owner = -1;
+ init->owner = -1;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
index 7c63abf11e22..abf6748c072e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
@@ -3,7 +3,7 @@
#include "priv.h"
struct nvkm_pll_vals;
-struct nv04_devinit_priv {
+struct nv04_devinit {
struct nvkm_devinit base;
int owner;
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
index def8649216c2..2659b9c37df4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
@@ -44,8 +44,8 @@ nv05_devinit_meminit(struct nvkm_devinit *devinit)
{ 0x06, 0x00 },
{ 0x00, 0x00 }
};
- struct nv04_devinit_priv *priv = (void *)devinit;
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nv04_devinit *init = (void *)devinit;
+ struct nvkm_bios *bios = nvkm_bios(init);
struct io_mapping *fb;
u32 patt = 0xdeadbeef;
u16 data;
@@ -53,13 +53,13 @@ nv05_devinit_meminit(struct nvkm_devinit *devinit)
int i, v;
/* Map the framebuffer aperture */
- fb = fbmem_init(nv_device(priv));
+ fb = fbmem_init(nv_device(init));
if (!fb) {
- nv_error(priv, "failed to map fb\n");
+ nv_error(init, "failed to map fb\n");
return;
}
- strap = (nv_rd32(priv, 0x101000) & 0x0000003c) >> 2;
+ strap = (nv_rd32(init, 0x101000) & 0x0000003c) >> 2;
if ((data = bmp_mem_init_table(bios))) {
ramcfg[0] = nv_ro08(bios, data + 2 * strap + 0);
ramcfg[1] = nv_ro08(bios, data + 2 * strap + 1);
@@ -69,59 +69,59 @@ nv05_devinit_meminit(struct nvkm_devinit *devinit)
}
/* Sequencer off */
- nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
+ nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) | 0x20);
- if (nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
+ if (nv_rd32(init, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
goto out;
- nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
+ nv_mask(init, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
/* If present load the hardcoded scrambling table */
if (data) {
for (i = 0, data += 0x10; i < 8; i++, data += 4) {
u32 scramble = nv_ro32(bios, data);
- nv_wr32(priv, NV04_PFB_SCRAMBLE(i), scramble);
+ nv_wr32(init, NV04_PFB_SCRAMBLE(i), scramble);
}
}
/* Set memory type/width/length defaults depending on the straps */
- nv_mask(priv, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
+ nv_mask(init, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
if (ramcfg[1] & 0x80)
- nv_mask(priv, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
+ nv_mask(init, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
- nv_mask(priv, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
- nv_mask(priv, NV04_PFB_CFG1, 0, 1);
+ nv_mask(init, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
+ nv_mask(init, NV04_PFB_CFG1, 0, 1);
/* Probe memory bus width */
for (i = 0; i < 4; i++)
fbmem_poke(fb, 4 * i, patt);
if (fbmem_peek(fb, 0xc) != patt)
- nv_mask(priv, NV04_PFB_BOOT_0,
+ nv_mask(init, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
/* Probe memory length */
- v = nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
+ v = nv_rd32(init, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
(!fbmem_readback(fb, 0x1000000, ++patt) ||
!fbmem_readback(fb, 0, ++patt)))
- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
+ nv_mask(init, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
!fbmem_readback(fb, 0x800000, ++patt))
- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
+ nv_mask(init, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
if (!fbmem_readback(fb, 0x400000, ++patt))
- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
+ nv_mask(init, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
out:
/* Sequencer on */
- nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
+ nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) & ~0x20);
fbmem_fini(fb);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
index 7aabc1bf0640..bbf791eaa0ab 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
@@ -32,31 +32,31 @@
static void
nv10_devinit_meminit(struct nvkm_devinit *devinit)
{
- struct nv04_devinit_priv *priv = (void *)devinit;
+ struct nv04_devinit *init = (void *)devinit;
static const int mem_width[] = { 0x10, 0x00, 0x20 };
int mem_width_count;
uint32_t patt = 0xdeadbeef;
struct io_mapping *fb;
int i, j, k;
- if (nv_device(priv)->card_type >= NV_11 &&
- nv_device(priv)->chipset >= 0x17)
+ if (nv_device(init)->card_type >= NV_11 &&
+ nv_device(init)->chipset >= 0x17)
mem_width_count = 3;
else
mem_width_count = 2;
/* Map the framebuffer aperture */
- fb = fbmem_init(nv_device(priv));
+ fb = fbmem_init(nv_device(init));
if (!fb) {
- nv_error(priv, "failed to map fb\n");
+ nv_error(init, "failed to map fb\n");
return;
}
- nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
+ nv_wr32(init, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
/* Probe memory bus width */
for (i = 0; i < mem_width_count; i++) {
- nv_mask(priv, NV04_PFB_CFG0, 0x30, mem_width[i]);
+ nv_mask(init, NV04_PFB_CFG0, 0x30, mem_width[i]);
for (j = 0; j < 4; j++) {
for (k = 0; k < 4; k++)
@@ -75,7 +75,7 @@ mem_width_found:
/* Probe amount of installed memory */
for (i = 0; i < 4; i++) {
- int off = nv_rd32(priv, 0x10020c) - 0x100000;
+ int off = nv_rd32(init, 0x10020c) - 0x100000;
fbmem_poke(fb, off, patt);
fbmem_poke(fb, 0, 0);
@@ -90,7 +90,7 @@ mem_width_found:
}
/* IC missing - disable the upper half memory space. */
- nv_mask(priv, NV04_PFB_CFG0, 0x1000, 0);
+ nv_mask(init, NV04_PFB_CFG0, 0x1000, 0);
amount_found:
fbmem_fini(fb);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
index 02fcfd921c42..50f9849cdfb5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
@@ -32,32 +32,32 @@
static void
nv20_devinit_meminit(struct nvkm_devinit *devinit)
{
- struct nv04_devinit_priv *priv = (void *)devinit;
- struct nvkm_device *device = nv_device(priv);
+ struct nv04_devinit *init = (void *)devinit;
+ struct nvkm_device *device = nv_device(init);
uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900);
uint32_t amount, off;
struct io_mapping *fb;
/* Map the framebuffer aperture */
- fb = fbmem_init(nv_device(priv));
+ fb = fbmem_init(nv_device(init));
if (!fb) {
- nv_error(priv, "failed to map fb\n");
+ nv_error(init, "failed to map fb\n");
return;
}
- nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
+ nv_wr32(init, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
/* Allow full addressing */
- nv_mask(priv, NV04_PFB_CFG0, 0, mask);
+ nv_mask(init, NV04_PFB_CFG0, 0, mask);
- amount = nv_rd32(priv, 0x10020c);
+ amount = nv_rd32(init, 0x10020c);
for (off = amount; off > 0x2000000; off -= 0x2000000)
fbmem_poke(fb, off - 4, off);
- amount = nv_rd32(priv, 0x10020c);
+ amount = nv_rd32(init, 0x10020c);
if (amount != fbmem_peek(fb, amount - 4))
/* IC missing - disable the upper half memory space. */
- nv_mask(priv, NV04_PFB_CFG0, mask, 0);
+ nv_mask(init, NV04_PFB_CFG0, mask, 0);
fbmem_fini(fb);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
index 26b7cb13e167..8e9633096bec 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
@@ -35,8 +35,8 @@
int
nv50_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- struct nvkm_bios *bios = nvkm_bios(priv);
+ struct nv50_devinit *init = (void *)devinit;
+ struct nvkm_bios *bios = nvkm_bios(init);
struct nvbios_pll info;
int N1, M1, N2, M2, P;
int ret;
@@ -56,20 +56,20 @@ nv50_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
switch (info.type) {
case PLL_VPLL0:
case PLL_VPLL1:
- nv_wr32(priv, info.reg + 0, 0x10000611);
- nv_mask(priv, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
- nv_mask(priv, info.reg + 8, 0x7fff00ff, (P << 28) |
+ nv_wr32(init, info.reg + 0, 0x10000611);
+ nv_mask(init, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
+ nv_mask(init, info.reg + 8, 0x7fff00ff, (P << 28) |
(M2 << 16) | N2);
break;
case PLL_MEMORY:
- nv_mask(priv, info.reg + 0, 0x01ff0000, (P << 22) |
+ nv_mask(init, info.reg + 0, 0x01ff0000, (P << 22) |
(info.bias_p << 19) |
(P << 16));
- nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
+ nv_wr32(init, info.reg + 4, (N1 << 8) | M1);
break;
default:
- nv_mask(priv, info.reg + 0, 0x00070000, (P << 16));
- nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
+ nv_mask(init, info.reg + 0, 0x00070000, (P << 16));
+ nv_wr32(init, info.reg + 4, (N1 << 8) | M1);
break;
}
@@ -79,8 +79,8 @@ nv50_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
static u64
nv50_devinit_disable(struct nvkm_devinit *devinit)
{
- struct nv50_devinit_priv *priv = (void *)devinit;
- u32 r001540 = nv_rd32(priv, 0x001540);
+ struct nv50_devinit *init = (void *)devinit;
+ u32 r001540 = nv_rd32(init, 0x001540);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000))
@@ -94,28 +94,28 @@ nv50_devinit_init(struct nvkm_object *object)
{
struct nvkm_bios *bios = nvkm_bios(object);
struct nvkm_ibus *ibus = nvkm_ibus(object);
- struct nv50_devinit_priv *priv = (void *)object;
+ struct nv50_devinit *init = (void *)object;
struct nvbios_outp info;
struct dcb_output outp;
u8 ver = 0xff, hdr, cnt, len;
int ret, i = 0;
- if (!priv->base.post) {
- if (!nv_rdvgac(priv, 0, 0x00) &&
- !nv_rdvgac(priv, 0, 0x1a)) {
- nv_info(priv, "adaptor not initialised\n");
- priv->base.post = true;
+ if (!init->base.post) {
+ if (!nv_rdvgac(init, 0, 0x00) &&
+ !nv_rdvgac(init, 0, 0x1a)) {
+ nv_info(init, "adaptor not initialised\n");
+ init->base.post = true;
}
}
- /* some boards appear to require certain priv register timeouts
+ /* some boards appear to require certain init register timeouts
* to be bumped before runing devinit scripts. not a clue why
* the vbios engineers didn't make the scripts just work...
*/
- if (priv->base.post && ibus)
+ if (init->base.post && ibus)
nv_ofuncs(ibus)->init(nv_object(ibus));
- ret = nvkm_devinit_init(&priv->base);
+ ret = nvkm_devinit_init(&init->base);
if (ret)
return ret;
@@ -123,11 +123,11 @@ nv50_devinit_init(struct nvkm_object *object)
* pointer of each dcb entry's display encoder table in order
* to properly initialise each encoder.
*/
- while (priv->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) {
+ while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) {
if (nvbios_outp_match(bios, outp.hasht, outp.hashm,
&ver, &hdr, &cnt, &len, &info)) {
- struct nvbios_init init = {
- .subdev = nv_subdev(priv),
+ struct nvbios_init exec = {
+ .subdev = nv_subdev(init),
.bios = bios,
.offset = info.script[0],
.outp = &outp,
@@ -135,7 +135,7 @@ nv50_devinit_init(struct nvkm_object *object)
.execute = 1,
};
- nvbios_exec(&init);
+ nvbios_exec(&exec);
}
i++;
}
@@ -148,11 +148,11 @@ nv50_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
- struct nv50_devinit_priv *priv;
+ struct nv50_devinit *init;
int ret;
- ret = nvkm_devinit_create(parent, engine, oclass, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_devinit_create(parent, engine, oclass, &init);
+ *pobject = nv_object(init);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
index 9243521c80ac..c132fb4ae4f5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
@@ -2,7 +2,7 @@
#define __NVKM_DEVINIT_NV50_H__
#include "priv.h"
-struct nv50_devinit_priv {
+struct nv50_devinit {
struct nvkm_devinit base;
u32 r001540;
};
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