diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/base.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 136 |
1 files changed, 68 insertions, 68 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index ea3e8902f458..62395ab742c5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -88,7 +88,7 @@ nv4_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv04_fifo_new, + .fifo = nv04_fifo_new, // .gr = nv04_gr_new, // .sw = nv04_sw_new, }; @@ -108,7 +108,7 @@ nv5_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv04_fifo_new, + .fifo = nv04_fifo_new, // .gr = nv04_gr_new, // .sw = nv04_sw_new, }; @@ -148,7 +148,7 @@ nv11_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv10_fifo_new, + .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -169,7 +169,7 @@ nv15_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv10_fifo_new, + .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -190,7 +190,7 @@ nv17_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -211,7 +211,7 @@ nv18_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -232,7 +232,7 @@ nv1a_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv10_fifo_new, + .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -253,7 +253,7 @@ nv1f_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -274,7 +274,7 @@ nv20_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv20_gr_new, // .sw = nv10_sw_new, }; @@ -295,7 +295,7 @@ nv25_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv25_gr_new, // .sw = nv10_sw_new, }; @@ -316,7 +316,7 @@ nv28_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv25_gr_new, // .sw = nv10_sw_new, }; @@ -337,7 +337,7 @@ nv2a_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv2a_gr_new, // .sw = nv10_sw_new, }; @@ -358,7 +358,7 @@ nv30_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv30_gr_new, // .sw = nv10_sw_new, }; @@ -379,7 +379,7 @@ nv31_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv30_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, @@ -401,7 +401,7 @@ nv34_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv34_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, @@ -423,7 +423,7 @@ nv35_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv35_gr_new, // .sw = nv10_sw_new, }; @@ -444,7 +444,7 @@ nv36_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv35_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, @@ -468,7 +468,7 @@ nv40_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, @@ -493,7 +493,7 @@ nv41_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, @@ -518,7 +518,7 @@ nv42_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, @@ -543,7 +543,7 @@ nv43_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, @@ -568,7 +568,7 @@ nv44_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -593,7 +593,7 @@ nv45_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -618,7 +618,7 @@ nv46_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -643,7 +643,7 @@ nv47_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -668,7 +668,7 @@ nv49_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -693,7 +693,7 @@ nv4a_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -718,7 +718,7 @@ nv4b_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -743,7 +743,7 @@ nv4c_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -768,7 +768,7 @@ nv4e_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -796,7 +796,7 @@ nv50_chipset = { .volt = nv40_volt_new, .disp = nv50_disp_new, .dma = nv50_dma_new, -// .fifo = nv50_fifo_new, + .fifo = nv50_fifo_new, // .gr = nv50_gr_new, // .mpeg = nv50_mpeg_new, // .pm = nv50_pm_new, @@ -821,7 +821,7 @@ nv63_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -846,7 +846,7 @@ nv67_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -871,7 +871,7 @@ nv68_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -901,7 +901,7 @@ nv84_chipset = { .cipher = g84_cipher_new, .disp = g84_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, @@ -932,7 +932,7 @@ nv86_chipset = { .cipher = g84_cipher_new, .disp = g84_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, @@ -963,7 +963,7 @@ nv92_chipset = { .cipher = g84_cipher_new, .disp = g84_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, @@ -994,7 +994,7 @@ nv94_chipset = { .cipher = g84_cipher_new, .disp = g94_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, @@ -1022,7 +1022,7 @@ nv96_chipset = { .bar = g84_bar_new, .volt = nv40_volt_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .sw = nv50_sw_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, @@ -1053,7 +1053,7 @@ nv98_chipset = { .bar = g84_bar_new, .volt = nv40_volt_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .sw = nv50_sw_new, // .gr = nv50_gr_new, .mspdec = g98_mspdec_new, @@ -1087,7 +1087,7 @@ nva0_chipset = { .cipher = g84_cipher_new, .disp = gt200_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = gt200_pm_new, @@ -1118,7 +1118,7 @@ nva3_chipset = { .ce[0] = gt215_ce_new, .disp = gt215_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, .mspdec = gt215_mspdec_new, @@ -1151,7 +1151,7 @@ nva5_chipset = { .ce[0] = gt215_ce_new, .disp = gt215_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, @@ -1183,7 +1183,7 @@ nva8_chipset = { .ce[0] = gt215_ce_new, .disp = gt215_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, @@ -1213,7 +1213,7 @@ nvaa_chipset = { .volt = nv40_volt_new, .disp = g94_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, @@ -1244,7 +1244,7 @@ nvac_chipset = { .volt = nv40_volt_new, .disp = g94_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, @@ -1277,7 +1277,7 @@ nvaf_chipset = { .ce[0] = gt215_ce_new, .disp = gt215_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, @@ -1312,7 +1312,7 @@ nvc0_chipset = { .ce[1] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf100_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1346,7 +1346,7 @@ nvc1_chipset = { .ce[0] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf108_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1380,7 +1380,7 @@ nvc3_chipset = { .ce[0] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1415,7 +1415,7 @@ nvc4_chipset = { .ce[1] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1450,7 +1450,7 @@ nvc8_chipset = { .ce[1] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf110_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1485,7 +1485,7 @@ nvce_chipset = { .ce[1] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1519,7 +1519,7 @@ nvcf_chipset = { .ce[0] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1551,7 +1551,7 @@ nvd7_chipset = { .ce[0] = gf100_ce_new, .disp = gf119_disp_new, .dma = gf119_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf117_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1585,7 +1585,7 @@ nvd9_chipset = { .ce[0] = gf100_ce_new, .disp = gf119_disp_new, .dma = gf119_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf119_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1621,7 +1621,7 @@ nve4_chipset = { .ce[2] = gk104_ce_new, .disp = gk104_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1657,7 +1657,7 @@ nve6_chipset = { .ce[2] = gk104_ce_new, .disp = gk104_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1693,7 +1693,7 @@ nve7_chipset = { .ce[2] = gk104_ce_new, .disp = gk104_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1720,7 +1720,7 @@ nvea_chipset = { .volt = gk20a_volt_new, .ce[2] = gk104_ce_new, .dma = gf119_dma_new, -// .fifo = gk20a_fifo_new, + .fifo = gk20a_fifo_new, // .gr = gk20a_gr_new, // .pm = gk104_pm_new, // .sw = gf100_sw_new, @@ -1753,7 +1753,7 @@ nvf0_chipset = { .ce[2] = gk104_ce_new, .disp = gk110_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk110_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1789,7 +1789,7 @@ nvf1_chipset = { .ce[2] = gk104_ce_new, .disp = gk110_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk110b_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1825,7 +1825,7 @@ nv106_chipset = { .ce[2] = gk104_ce_new, .disp = gk110_disp_new, .dma = gf119_dma_new, -// .fifo = gk208_fifo_new, + .fifo = gk208_fifo_new, // .gr = gk208_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1860,7 +1860,7 @@ nv108_chipset = { .ce[2] = gk104_ce_new, .disp = gk110_disp_new, .dma = gf119_dma_new, -// .fifo = gk208_fifo_new, + .fifo = gk208_fifo_new, // .gr = gk208_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1893,7 +1893,7 @@ nv117_chipset = { .ce[2] = gk104_ce_new, .disp = gm107_disp_new, .dma = gf119_dma_new, -// .fifo = gk208_fifo_new, + .fifo = gk208_fifo_new, // .gr = gm107_gr_new, // .sw = gf100_sw_new, }; @@ -1922,7 +1922,7 @@ nv124_chipset = { .ce[2] = gm204_ce_new, .disp = gm204_disp_new, .dma = gf119_dma_new, -// .fifo = gm204_fifo_new, + .fifo = gm204_fifo_new, // .gr = gm204_gr_new, // .sw = gf100_sw_new, }; @@ -1951,7 +1951,7 @@ nv126_chipset = { .ce[2] = gm204_ce_new, .disp = gm204_disp_new, .dma = gf119_dma_new, -// .fifo = gm204_fifo_new, + .fifo = gm204_fifo_new, // .gr = gm206_gr_new, // .sw = gf100_sw_new, }; @@ -1972,7 +1972,7 @@ nv12b_chipset = { .timer = gk20a_timer_new, .ce[2] = gm204_ce_new, .dma = gf119_dma_new, -// .fifo = gm20b_fifo_new, + .fifo = gm20b_fifo_new, // .gr = gm20b_gr_new, // .sw = gf100_sw_new, }; |
