diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h new file mode 100644 index 000000000000..9a0149370d26 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -0,0 +1,43 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef RAVEN_INC_H +#define RAVEN_INC_H + + +#include "asic_reg/raven1/MP/mp_10_0_default.h" +#include "asic_reg/raven1/MP/mp_10_0_offset.h" +#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h" + +#include "asic_reg/raven1/NBIO/nbio_7_0_default.h" +#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h" +#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h" + +#include "asic_reg/raven1/THM/thm_10_0_default.h" +#include "asic_reg/raven1/THM/thm_10_0_offset.h" +#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h" + + +#define ixDDI_PHY_GEN_STATUS 0x3FCE8 + +#endif |