diff options
Diffstat (limited to 'arch/mn10300/proc-mn2ws0050')
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/Makefile | 5 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/cache.h | 49 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/clock.h | 20 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h | 103 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h | 30 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/irq.h | 49 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h | 120 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/proc.h | 18 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h | 51 | ||||
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/proc-init.c | 134 |
10 files changed, 0 insertions, 579 deletions
diff --git a/arch/mn10300/proc-mn2ws0050/Makefile b/arch/mn10300/proc-mn2ws0050/Makefile deleted file mode 100644 index d4ca13309a85..000000000000 --- a/arch/mn10300/proc-mn2ws0050/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-y := proc-init.o diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h deleted file mode 100644 index bcb5df2d892f..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Cache specification - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 13-Nov-2006 MEI Add L1_CACHE_SHIFT_MAX definition. - * 29-Jul-2008 MEI Add define for MN10300_HAS_AREAPURGE_REG. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CACHE_H -#define _ASM_PROC_CACHE_H - -/* - * L1 cache - */ -#define L1_CACHE_NWAYS 4 /* number of ways in caches */ -#define L1_CACHE_NENTRIES 128 /* number of entries in each way */ -#define L1_CACHE_BYTES 32 /* bytes per entry */ -#define L1_CACHE_SHIFT 5 /* shift for bytes per entry */ -#define L1_CACHE_WAYDISP 0x1000 /* distance from one way to the next */ - -#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */ -#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ -#define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */ -#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ -#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY) - -/* - * specification of the interval between interrupt checking intervals whilst - * managing the cache with the interrupts disabled - */ -#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4 - -/* - * The size of range at which it becomes more economical to just flush the - * whole cache rather than trying to flush the specified range. - */ -#define MN10300_DCACHE_FLUSH_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) -#define MN10300_DCACHE_FLUSH_INV_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) - -#endif /* _ASM_PROC_CACHE_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/clock.h b/arch/mn10300/proc-mn2ws0050/include/proc/clock.h deleted file mode 100644 index fe4c0a4a53a2..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/clock.h +++ /dev/null @@ -1,20 +0,0 @@ -/* clock.h: proc-specific clocks - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 23-Feb-2007 MEI Delete define for watchdog timer. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CLOCK_H -#define _ASM_PROC_CLOCK_H - -#include <unit/clock.h> - -#endif /* _ASM_PROC_CLOCK_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h deleted file mode 100644 index 4c4319e241d1..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h +++ /dev/null @@ -1,103 +0,0 @@ -/* MN2WS0050 on-board DMA controller registers - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - */ - -#ifndef _ASM_PROC_DMACTL_REGS_H -#define _ASM_PROC_DMACTL_REGS_H - -#include <asm/cpu-regs.h> - -#ifdef __KERNEL__ - -/* DMA registers */ -#define DMxCTR(N) __SYSREG(0xd4005000+(N*0x100), u32) /* control reg */ -#define DMxCTR_BG 0x0000001f /* transfer request source */ -#define DMxCTR_BG_SOFT 0x00000000 /* - software source */ -#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */ -#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */ -#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */ -#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */ -#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */ -#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */ -#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */ -#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */ -#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */ -#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */ -#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */ -#define DMxCTR_BG_RYBY 0x0000000d /* - NAND Flash RY/BY request source */ -#define DMxCTR_BG_RMC 0x0000000e /* - remote controller output */ -#define DMxCTR_BG_XIRQ12 0x00000011 /* - XIRQ12 pin interrupt source */ -#define DMxCTR_BG_XIRQ13 0x00000012 /* - XIRQ13 pin interrupt source */ -#define DMxCTR_BG_TCK 0x00000014 /* - tick timer underflow */ -#define DMxCTR_BG_SC4TX 0x00000019 /* - serial port4 transmission */ -#define DMxCTR_BG_SC4RX 0x0000001a /* - serial port4 reception */ -#define DMxCTR_BG_SC5TX 0x0000001b /* - serial port5 transmission */ -#define DMxCTR_BG_SC5RX 0x0000001c /* - serial port5 reception */ -#define DMxCTR_BG_SC6TX 0x0000001d /* - serial port6 transmission */ -#define DMxCTR_BG_SC6RX 0x0000001e /* - serial port6 reception */ -#define DMxCTR_BG_TMSUFLOW 0x0000001f /* - timestamp timer underflow */ -#define DMxCTR_SAM 0x00000060 /* DMA transfer src addr mode */ -#define DMxCTR_SAM_INCR 0x00000000 /* - increment */ -#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */ -#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */ -#define DMxCTR_DAM 0x00000300 /* DMA transfer dest addr mode */ -#define DMxCTR_DAM_INCR 0x00000000 /* - increment */ -#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */ -#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */ -#define DMxCTR_UT 0x00006000 /* DMA transfer unit */ -#define DMxCTR_UT_1 0x00000000 /* - 1 byte */ -#define DMxCTR_UT_2 0x00002000 /* - 2 byte */ -#define DMxCTR_UT_4 0x00004000 /* - 4 byte */ -#define DMxCTR_UT_16 0x00006000 /* - 16 byte */ -#define DMxCTR_RRE 0x00008000 /* DMA round robin enable */ -#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */ -#define DMxCTR_RQM 0x00060000 /* external request input source mode */ -#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */ -#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */ -#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */ -#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */ -#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */ -#define DMxCTR_PERR 0x40000000 /* DMA transfer parameter error flag */ -#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */ - -#define DMxSRC(N) __SYSREG(0xd4005004+(N*0x100), u32) /* control reg */ - -#define DMxDST(N) __SYSREG(0xd4005008+(N*0x100), u32) /* source addr reg */ - -#define DMxSIZ(N) __SYSREG(0xd400500c+(N*0x100), u32) /* dest addr reg */ -#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */ - -#define DMxCYC(N) __SYSREG(0xd4005010+(N*0x100), u32) /* intermittent size reg */ -#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */ - -#define DM0IRQ 16 /* DMA channel 0 complete IRQ */ -#define DM1IRQ 17 /* DMA channel 1 complete IRQ */ -#define DM2IRQ 18 /* DMA channel 2 complete IRQ */ -#define DM3IRQ 19 /* DMA channel 3 complete IRQ */ - -#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */ -#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */ -#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */ -#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */ - -#ifndef __ASSEMBLY__ - -struct mn10300_dmactl_regs { - u32 ctr; - const void *src; - void *dst; - u32 siz; - u32 cyc; -} __attribute__((aligned(0x100))); - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_PROC_DMACTL_REGS_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h deleted file mode 100644 index 4d4084ea6694..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_PROC_INTCTL_REGS_H -#define _ASM_PROC_INTCTL_REGS_H - -#ifndef _ASM_INTCTL_REGS_H -# error "please don't include this file directly" -#endif - -/* intr acceptance group reg */ -#define IAGR __SYSREG(0xd4000100, u16) - -/* group number register */ -#define IAGR_GN 0x003fc - -#define __GET_XIRQ_TRIGGER(X, Z) (((Z) >> ((X) * 2)) & 3) - -#define __SET_XIRQ_TRIGGER(X, Y, Z) \ -({ \ - typeof(Z) x = (Z); \ - x &= ~(3 << ((X) * 2)); \ - x |= ((Y) & 3) << ((X) * 2); \ - (Z) = x; \ -}) - -/* external pin intr spec reg */ -#define EXTMD0 __SYSREG(0xd4000200, u32) -#define GET_XIRQ_TRIGGER(X) __GET_XIRQ_TRIGGER(X, EXTMD0) -#define SET_XIRQ_TRIGGER(X, Y) __SET_XIRQ_TRIGGER(X, Y, EXTMD0) - -#endif /* _ASM_PROC_INTCTL_REGS_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/irq.h b/arch/mn10300/proc-mn2ws0050/include/proc/irq.h deleted file mode 100644 index 37777a85ab6f..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/irq.h +++ /dev/null @@ -1,49 +0,0 @@ -/* MN2WS0050 on-board interrupt controller registers - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 13-Nov-2006 MEI Define extended IRQ number for SMP support. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _PROC_IRQ_H -#define _PROC_IRQ_H - -#ifdef __KERNEL__ - -#define GxICR_NUM_IRQS 163 -#ifdef CONFIG_SMP -#define GxICR_NUM_EXT_IRQS 197 -#endif /* CONFIG_SMP */ - -#define GxICR_NUM_XIRQS 16 - -#define XIRQ0 34 -#define XIRQ1 35 -#define XIRQ2 36 -#define XIRQ3 37 -#define XIRQ4 38 -#define XIRQ5 39 -#define XIRQ6 40 -#define XIRQ7 41 -#define XIRQ8 42 -#define XIRQ9 43 -#define XIRQ10 44 -#define XIRQ11 45 -#define XIRQ12 46 -#define XIRQ13 47 -#define XIRQ14 48 -#define XIRQ15 49 - -#define XIRQ2IRQ(num) (XIRQ0 + num) - -#endif /* __KERNEL__ */ - -#endif /* _PROC_IRQ_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h deleted file mode 100644 index 84448f3828b3..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h +++ /dev/null @@ -1,120 +0,0 @@ -/* NAND flash interface register definitions - * - * Copyright (C) 2008-2009 Panasonic Corporation - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PROC_NAND_REGS_H_ -#define _PROC_NAND_REGS_H_ - -/* command register */ -#define FCOMMAND_0 __SYSREG(0xd8f00000, u8) /* fcommand[24:31] */ -#define FCOMMAND_1 __SYSREG(0xd8f00001, u8) /* fcommand[16:23] */ -#define FCOMMAND_2 __SYSREG(0xd8f00002, u8) /* fcommand[8:15] */ -#define FCOMMAND_3 __SYSREG(0xd8f00003, u8) /* fcommand[0:7] */ - -/* for dma 16 byte trans, use FCOMMAND2 register */ -#define FCOMMAND2_0 __SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */ -#define FCOMMAND2_1 __SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */ -#define FCOMMAND2_2 __SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */ -#define FCOMMAND2_3 __SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */ - -#define FCOMMAND_FIEN 0x80 /* nand flash I/F enable */ -#define FCOMMAND_BW_8BIT 0x00 /* 8bit bus width */ -#define FCOMMAND_BW_16BIT 0x40 /* 16bit bus width */ -#define FCOMMAND_BLOCKSZ_SMALL 0x00 /* small block */ -#define FCOMMAND_BLOCKSZ_LARGE 0x20 /* large block */ -#define FCOMMAND_DMASTART 0x10 /* dma start */ -#define FCOMMAND_RYBY 0x08 /* ready/busy flag */ -#define FCOMMAND_RYBYINTMSK 0x04 /* mask ready/busy interrupt */ -#define FCOMMAND_XFWP 0x02 /* write protect enable */ -#define FCOMMAND_XFCE 0x01 /* flash device disable */ -#define FCOMMAND_SEQKILL 0x10 /* stop seq-read */ -#define FCOMMAND_ANUM 0x07 /* address cycle */ -#define FCOMMAND_ANUM_NONE 0x00 /* address cycle none */ -#define FCOMMAND_ANUM_1CYC 0x01 /* address cycle 1cycle */ -#define FCOMMAND_ANUM_2CYC 0x02 /* address cycle 2cycle */ -#define FCOMMAND_ANUM_3CYC 0x03 /* address cycle 3cycle */ -#define FCOMMAND_ANUM_4CYC 0x04 /* address cycle 4cycle */ -#define FCOMMAND_ANUM_5CYC 0x05 /* address cycle 5cycle */ -#define FCOMMAND_FCMD_READ0 0x00 /* read1 command */ -#define FCOMMAND_FCMD_SEQIN 0x80 /* page program 1st command */ -#define FCOMMAND_FCMD_PAGEPROG 0x10 /* page program 2nd command */ -#define FCOMMAND_FCMD_RESET 0xff /* reset command */ -#define FCOMMAND_FCMD_ERASE1 0x60 /* erase 1st command */ -#define FCOMMAND_FCMD_ERASE2 0xd0 /* erase 2nd command */ -#define FCOMMAND_FCMD_STATUS 0x70 /* read status command */ -#define FCOMMAND_FCMD_READID 0x90 /* read id command */ -#define FCOMMAND_FCMD_READOOB 0x50 /* read3 command */ -/* address register */ -#define FADD __SYSREG(0xd8f00004, u32) -/* address register 2 */ -#define FADD2 __SYSREG(0xd8f00008, u32) -/* error judgement register */ -#define FJUDGE __SYSREG(0xd8f0000c, u32) -#define FJUDGE_NOERR 0x0 /* no error */ -#define FJUDGE_1BITERR 0x1 /* 1bit error in data area */ -#define FJUDGE_PARITYERR 0x2 /* parity error */ -#define FJUDGE_UNCORRECTABLE 0x3 /* uncorrectable error */ -#define FJUDGE_ERRJDG_MSK 0x3 /* mask of judgement result */ -/* 1st ECC store register */ -#define FECC11 __SYSREG(0xd8f00010, u32) -/* 2nd ECC store register */ -#define FECC12 __SYSREG(0xd8f00014, u32) -/* 3rd ECC store register */ -#define FECC21 __SYSREG(0xd8f00018, u32) -/* 4th ECC store register */ -#define FECC22 __SYSREG(0xd8f0001c, u32) -/* 5th ECC store register */ -#define FECC31 __SYSREG(0xd8f00020, u32) -/* 6th ECC store register */ -#define FECC32 __SYSREG(0xd8f00024, u32) -/* 7th ECC store register */ -#define FECC41 __SYSREG(0xd8f00028, u32) -/* 8th ECC store register */ -#define FECC42 __SYSREG(0xd8f0002c, u32) -/* data register */ -#define FDATA __SYSREG(0xd8f00030, u32) -/* access pulse register */ -#define FPWS __SYSREG(0xd8f00100, u32) -#define FPWS_PWS1W_2CLK 0x00000000 /* write pulse width 1clock */ -#define FPWS_PWS1W_3CLK 0x01000000 /* write pulse width 2clock */ -#define FPWS_PWS1W_4CLK 0x02000000 /* write pulse width 4clock */ -#define FPWS_PWS1W_5CLK 0x03000000 /* write pulse width 5clock */ -#define FPWS_PWS1W_6CLK 0x04000000 /* write pulse width 6clock */ -#define FPWS_PWS1W_7CLK 0x05000000 /* write pulse width 7clock */ -#define FPWS_PWS1W_8CLK 0x06000000 /* write pulse width 8clock */ -#define FPWS_PWS1R_3CLK 0x00010000 /* read pulse width 3clock */ -#define FPWS_PWS1R_4CLK 0x00020000 /* read pulse width 4clock */ -#define FPWS_PWS1R_5CLK 0x00030000 /* read pulse width 5clock */ -#define FPWS_PWS1R_6CLK 0x00040000 /* read pulse width 6clock */ -#define FPWS_PWS1R_7CLK 0x00050000 /* read pulse width 7clock */ -#define FPWS_PWS1R_8CLK 0x00060000 /* read pulse width 8clock */ -#define FPWS_PWS2W_2CLK 0x00000100 /* write pulse interval 2clock */ -#define FPWS_PWS2W_3CLK 0x00000200 /* write pulse interval 3clock */ -#define FPWS_PWS2W_4CLK 0x00000300 /* write pulse interval 4clock */ -#define FPWS_PWS2W_5CLK 0x00000400 /* write pulse interval 5clock */ -#define FPWS_PWS2W_6CLK 0x00000500 /* write pulse interval 6clock */ -#define FPWS_PWS2R_2CLK 0x00000001 /* read pulse interval 2clock */ -#define FPWS_PWS2R_3CLK 0x00000002 /* read pulse interval 3clock */ -#define FPWS_PWS2R_4CLK 0x00000003 /* read pulse interval 4clock */ -#define FPWS_PWS2R_5CLK 0x00000004 /* read pulse interval 5clock */ -#define FPWS_PWS2R_6CLK 0x00000005 /* read pulse interval 6clock */ -/* command register 2 */ -#define FCOMMAND2 __SYSREG(0xd8f00110, u32) -/* transfer frequency register */ -#define FNUM __SYSREG(0xd8f00114, u32) -#define FSDATA_ADDR 0xd8f00400 -/* active data register */ -#define FSDATA __SYSREG(FSDATA_ADDR, u32) - -#endif /* _PROC_NAND_REGS_H_ */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/proc.h b/arch/mn10300/proc-mn2ws0050/include/proc/proc.h deleted file mode 100644 index 90d5cadd05bd..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/proc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* proc.h: MN2WS0050 processor description - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_PROC_H -#define _ASM_PROC_PROC_H - -#define PROCESSOR_VENDOR_NAME "Panasonic" -#define PROCESSOR_MODEL_NAME "mn2ws0050" - -#endif /* _ASM_PROC_PROC_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h deleted file mode 100644 index 22f277fbb4de..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h +++ /dev/null @@ -1,51 +0,0 @@ -/* MN10300/AM33v2 Microcontroller SMP registers - * - * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd. - * All Rights Reserved. - * Created: - * 13-Nov-2006 MEI Add extended cache and atomic operation register - * for SMP support. - * 23-Feb-2007 MEI Add define for gdbstub SMP. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_SMP_REGS_H -#define _ASM_PROC_SMP_REGS_H - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -#include <linux/types.h> -#endif -#include <asm/cpu-regs.h> - -/* - * Reference to the interrupt controllers of other CPUs - */ -#define CROSS_ICR_CPU_SHIFT 16 - -#define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ - ((X) >= 64 && (X) < 192) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u16) -#define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ - (((X) >= 64) && ((X) < 192)) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u8) - -/* CPU ID register */ -#define CPUID __SYSREGC(0xc0000054, u32) -#define CPUID_MASK 0x00000007 /* CPU ID mask */ - -/* extended cache control register */ -#define ECHCTR __SYSREG(0xc0000c20, u32) -#define ECHCTR_IBCM 0x00000001 /* instruction cache broad cast mask */ -#define ECHCTR_DBCM 0x00000002 /* data cache broad cast mask */ -#define ECHCTR_ISPM 0x00000004 /* instruction cache snoop mask */ -#define ECHCTR_DSPM 0x00000008 /* data cache snoop mask */ - -#define NMIAGR __SYSREG(0xd400013c, u16) -#define NMIAGR_GN 0x03fc - -#endif /* __KERNEL__ */ -#endif /* _ASM_PROC_SMP_REGS_H */ diff --git a/arch/mn10300/proc-mn2ws0050/proc-init.c b/arch/mn10300/proc-mn2ws0050/proc-init.c deleted file mode 100644 index 25b1b453c515..000000000000 --- a/arch/mn10300/proc-mn2ws0050/proc-init.c +++ /dev/null @@ -1,134 +0,0 @@ -/* MN2WS0050 processor initialisation - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/interrupt.h> - -#include <asm/cacheflush.h> -#include <asm/processor.h> -#include <linux/uaccess.h> -#include <asm/io.h> -#include <linux/atomic.h> -#include <asm/smp.h> -#include <asm/pgalloc.h> -#include <asm/busctl-regs.h> -#include <unit/timex.h> -#include <asm/fpu.h> -#include <asm/rtc.h> - -#define MEMCONF __SYSREGC(0xdf800400, u32) - -/* - * initialise the on-silicon processor peripherals - */ -asmlinkage void __init processor_init(void) -{ - int loop; - - /* set up the exception table first */ - for (loop = 0x000; loop < 0x400; loop += 8) - __set_intr_stub(loop, __common_exception); - - __set_intr_stub(EXCEP_ITLBMISS, itlb_miss); - __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss); - __set_intr_stub(EXCEP_IAERROR, itlb_aerror); - __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); - __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); - __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); - __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled); - __set_intr_stub(EXCEP_SYSCALL0, system_call); - - __set_intr_stub(EXCEP_NMI, nmi_handler); - __set_intr_stub(EXCEP_WDT, nmi_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler); - - IVAR0 = EXCEP_IRQ_LEVEL0; - IVAR1 = EXCEP_IRQ_LEVEL1; - IVAR2 = EXCEP_IRQ_LEVEL2; - IVAR3 = EXCEP_IRQ_LEVEL3; - IVAR4 = EXCEP_IRQ_LEVEL4; - IVAR5 = EXCEP_IRQ_LEVEL5; - IVAR6 = EXCEP_IRQ_LEVEL6; - -#ifndef CONFIG_MN10300_HAS_CACHE_SNOOP - mn10300_dcache_flush_inv(); - mn10300_icache_inv(); -#endif - - /* disable all interrupts and set to priority 6 (lowest) */ -#ifdef CONFIG_SMP - for (loop = 0; loop < GxICR_NUM_IRQS; loop++) - GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; -#else /* !CONFIG_SMP */ - for (loop = 0; loop < NR_IRQS; loop++) - GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; -#endif /* !CONFIG_SMP */ - - /* clear the timers */ - TM0MD = 0; - TM1MD = 0; - TM2MD = 0; - TM3MD = 0; - TM4MD = 0; - TM5MD = 0; - TM6MD = 0; - TM6MDA = 0; - TM6MDB = 0; - TM7MD = 0; - TM8MD = 0; - TM9MD = 0; - TM10MD = 0; - TM11MD = 0; - TM12MD = 0; - TM13MD = 0; - TM14MD = 0; - TM15MD = 0; - - calibrate_clock(); -} - -/* - * determine the memory size and base from the memory controller regs - */ -void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size) -{ - unsigned long memconf = MEMCONF; - unsigned long size = 0; /* order: MByte */ - - *mem_base = 0x90000000; /* fixed address */ - - switch (memconf & 0x00000003) { - case 0x01: - size = 256 / 8; /* 256 Mbit per chip */ - break; - case 0x02: - size = 512 / 8; /* 512 Mbit per chip */ - break; - case 0x03: - size = 1024 / 8; /* 1 Gbit per chip */ - break; - default: - panic("Invalid SDRAM size"); - break; - } - - printk(KERN_INFO "DDR2-SDRAM: %luMB x 2 @%08lx\n", size, *mem_base); - - *mem_size = (size * 2) << 20; -} |
