diff options
Diffstat (limited to 'arch/m68k/include')
| -rw-r--r-- | arch/m68k/include/asm/m5206sim.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m525xsim.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5272sim.h | 8 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5307sim.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5407sim.h | 4 |
6 files changed, 14 insertions, 14 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index d67ce08e508d..02a91f489cbf 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -46,8 +46,8 @@ #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ -#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ +#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */ +#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */ #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index e57785de8a2a..7229fd872348 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -27,8 +27,8 @@ */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ +#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h index 05876cc95dde..b0fccd9d7102 100644 --- a/arch/m68k/include/asm/m525xsim.h +++ b/arch/m68k/include/asm/m525xsim.h @@ -28,8 +28,8 @@ */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ +#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 378a6d971eed..39834046e699 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -37,10 +37,10 @@ #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */ #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */ -#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ -#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ -#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ -#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ +#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */ +#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */ +#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ +#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ #define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ #define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 5709de5b8289..a328e1806feb 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -25,8 +25,8 @@ */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ +#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ #define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 622ebface9b3..023f5f64ccd5 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -25,8 +25,8 @@ */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ +#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ #define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ |
