Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.16 kernel cycle.
  Like with GPIO it is actually a bit calm this time.

  Core changes:

   - After lengthy discussions and partly due to my ignorance, we have
     merged a patch making pinctrl_force_default() and
     pinctrl_force_sleep() reprogram the states into the hardware of any
     hogged pins, even if they are already in the desired state.

     This only apply to hogged pins since groups of pins owned by
     drivers need to be managed by each driver, lest they could not do
     things like runtime PM and put pins to sleeping state even if the
     system as a whole is not in sleep.

  New drivers:

   - New driver for the Microsemi Ocelot SoC. This is used in ethernet
     switches.

   - The X-Powers AXP209 GPIO driver was extended to also deal with pin
     control and moved over from the GPIO subsystem. This circuit is a
     mixed-mode integrated circuit which is part of AllWinner designs.

   - New subdriver for the Qualcomm MSM8998 SoC, core of a high end
     mobile devices (phones) chipset.

   - New subdriver for the ST Microelectronics STM32MP157 MPU and
     STM32F769 MCU from the STM32 family.

   - New subdriver for the MediaTek MT7622 SoC. This is used for
     routers, repeater, gateways and such network infrastructure.

   - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC
     has multimedia features and target "smart devices", I guess in-car
     entertainment, in-flight entertainment, industrial control panels
     etc.

  General improvements:

   - Incremental improvements on the SH-PFC subdrivers for things like
     the CAN bus.

   - Enable the glitch filter on Baytrail GPIOs used for interrupts.

   - Proper handling of pins to GPIO ranges on the Semtec SX150X

   - An IRQ setup ordering fix on MCP23S08.

   - A good set of janitorial coding style fixes"

* tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits)
  pinctrl: mcp23s08: fix irq setup order
  pinctrl: Forward declare struct device
  pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
  pinctrl: stm32: add STM32F769 MCU support
  pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping
  pinctrl: sx150x: Register pinctrl before adding the gpiochip
  pinctrl: sx150x: Unregister the pinctrl on release
  pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe()
  pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show()
  pinctrl: pinmux: Use seq_putc() in pinmux_pins_show()
  pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show()
  pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call
  pinctrl: mediatek: mt7622: fix potential uninitialized value being returned
  pinctrl: uniphier: refactor drive strength get/set functions
  pinctrl: imx7ulp: constify struct imx_cfg_params_decode
  pinctrl: imx: constify struct imx_pinctrl_soc_info
  pinctrl: imx7d: simplify imx7d_pinctrl_probe
  pinctrl: imx: use struct imx_pinctrl_soc_info as a const
  pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly.
  pinctrl: qcom: Add msm8998 pinctrl driver
  ...

1 files changed, 116 insertions, 0 deletions

diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h
new file mode 100644
index 000000000000..25bb1fffa97a
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-axg-gpio.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
+#define _DT_BINDINGS_MESON_AXG_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0	0
+#define GPIOAO_1	1
+#define GPIOAO_2	2
+#define GPIOAO_3	3
+#define GPIOAO_4	4
+#define GPIOAO_5	5
+#define GPIOAO_6	6
+#define GPIOAO_7	7
+#define GPIOAO_8	8
+#define GPIOAO_9	9
+#define GPIOAO_10	10
+#define GPIOAO_11	11
+#define GPIOAO_12	12
+#define GPIOAO_13	13
+#define GPIO_TEST_N 14
+
+/* Second GPIO chip */
+#define GPIOZ_0		0
+#define GPIOZ_1		1
+#define GPIOZ_2		2
+#define GPIOZ_3		3
+#define GPIOZ_4		4
+#define GPIOZ_5		5
+#define GPIOZ_6		6
+#define GPIOZ_7		7
+#define GPIOZ_8		8
+#define GPIOZ_9		9
+#define GPIOZ_10	10
+#define BOOT_0		11
+#define BOOT_1		12
+#define BOOT_2		13
+#define BOOT_3		14
+#define BOOT_4		15
+#define BOOT_5		16
+#define BOOT_6		17
+#define BOOT_7		18
+#define BOOT_8		19
+#define BOOT_9		20
+#define BOOT_10		21
+#define BOOT_11		22
+#define BOOT_12		23
+#define BOOT_13		24
+#define BOOT_14		25
+#define GPIOA_0	    26
+#define GPIOA_1		27
+#define GPIOA_2		28
+#define GPIOA_3		29
+#define GPIOA_4		30
+#define GPIOA_5		31
+#define GPIOA_6		32
+#define GPIOA_7		33
+#define GPIOA_8		34
+#define GPIOA_9		35
+#define GPIOA_10	36
+#define GPIOA_11	37
+#define GPIOA_12	38
+#define GPIOA_13	39
+#define GPIOA_14	40
+#define GPIOA_15	41
+#define GPIOA_16	42
+#define GPIOA_17	43
+#define GPIOA_18	44
+#define GPIOA_19	45
+#define GPIOA_20	46
+#define GPIOX_0		47
+#define GPIOX_1		48
+#define GPIOX_2		49
+#define GPIOX_3		50
+#define GPIOX_4		51
+#define GPIOX_5		52
+#define GPIOX_6		53
+#define GPIOX_7		54
+#define GPIOX_8		55
+#define GPIOX_9		56
+#define GPIOX_10	57
+#define GPIOX_11	58
+#define GPIOX_12	59
+#define GPIOX_13	60
+#define GPIOX_14	61
+#define GPIOX_15	62
+#define GPIOX_16	63
+#define GPIOX_17	64
+#define GPIOX_18	65
+#define GPIOX_19	66
+#define GPIOX_20	67
+#define GPIOX_21	68
+#define GPIOX_22	69
+#define GPIOY_0		70
+#define GPIOY_1		71
+#define GPIOY_2		72
+#define GPIOY_3		73
+#define GPIOY_4		74
+#define GPIOY_5		75
+#define GPIOY_6		76
+#define GPIOY_7		77
+#define GPIOY_8		78
+#define GPIOY_9		79
+#define GPIOY_10	80
+#define GPIOY_11	81
+#define GPIOY_12	82
+#define GPIOY_13	83
+#define GPIOY_14	84
+#define GPIOY_15	85
+
+#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */