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authorNishanth Menon <nm@ti.com>2012-02-22 20:03:45 -0600
committerSamuel Ortiz <sameo@linux.intel.com>2012-03-06 18:46:48 +0100
commit3f8349e6e98ba0455437724589072523865eae5e (patch)
tree2d7c157d86aa6345e1c3cf8719e41b3897531fb3 /fs/reiserfs/dir.c
parent91d6a9a6c0d98ef6daeaf229e5acada652b4f6f0 (diff)
downloadtalos-obmc-linux-3f8349e6e98ba0455437724589072523865eae5e.tar.gz
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mfd: Clear twl6030 IRQ status register only once
TWL6030 family of PMIC use a shadow interrupt status register while kernel processes the current interrupt event. However, any write(0 or 1) to register INT_STS_A, INT_STS_B or INT_STS_C clears all 3 interrupt status registers. Since clear of the interrupt is done on 32k clk, depending on I2C bus speed, we could in-adverently clear the status of a interrupt status pending on shadow register in the current implementation. This is due to the fact that multi-byte i2c write operation into three seperate status register could result in multiple load and clear of status and result in lost interrupts. Instead, doing a single byte write to INT_STS_A register with 0x0 will clear all three interrupt status registers without the related risk. Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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