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authorSuzuki K Poulose <suzuki.poulose@arm.com>2017-08-02 10:22:16 -0600
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-08-28 16:05:49 +0200
commitf2e931a2deab1ab426085f0357285410644f2945 (patch)
treeb61f1b5849575d47e3cb71f3d7bb9e0ab99ef611 /fs/file.c
parentebab6a7db2c599b5c29d033f3a20f86016d9a9b8 (diff)
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coresight tmc: Support for save-restore in ETR
The Coresight SoC 600 TMC ETR supports save-restore feature, where the values of the RRP/RWP and STS.Full are retained when it leaves the Disabled state. Hence, we must program the RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP to the base address of the buffer and clear the STS.Full register. This can be later exploited for proper save-restore of ETR trace contexts (e.g, perf). Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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