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authorSuzuki K Poulose <suzuki.poulose@arm.com>2017-08-02 10:22:15 -0600
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-08-28 16:05:49 +0200
commitebab6a7db2c599b5c29d033f3a20f86016d9a9b8 (patch)
treee366e6fdf34fdef7c5c530a4f96c1636ef3f85cf /fs/devpts
parentcd407abd5efd6f36b6372d615fbab486936e90f4 (diff)
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coresight tmc etr: Setup AXI cache encoding for read transfers
If the ETR supports split cache encoding (i.e, separate bits for read and write transfers) unlike the older version (where read and write transfers use the same encoding in AXICTL[2-5]). This feature is not advertised and has to be described by the static mask associated with the device id. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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