diff options
| author | David Brownell <david-b@pacbell.net> | 2005-09-02 18:58:09 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2005-09-12 12:23:43 -0700 |
| commit | f7201c3dcd7799f2aa3d6ec427b194225360ecee (patch) | |
| tree | 1abe4c11c210f88de270e230a61d3e0d7e96b107 /drivers | |
| parent | 10f6524a8ef1413a8cbd952673997013183fe2a9 (diff) | |
| download | talos-obmc-linux-f7201c3dcd7799f2aa3d6ec427b194225360ecee.tar.gz talos-obmc-linux-f7201c3dcd7799f2aa3d6ec427b194225360ecee.zip | |
[PATCH] USB: EHCI workaround for NForce and mem > 2GB
NVidia reports (via Mark Overby) that some of their EHCI controllers
don't like certain data structure addresses beyond the 2GB mark.
He provided an earlier version of this patch.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/usb/host/ehci-hcd.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 2f7037c62e88..ae5ba4ddfb40 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -400,6 +400,23 @@ static int ehci_hc_reset (struct usb_hcd *hcd) return -EIO; } break; + case PCI_VENDOR_ID_NVIDIA: + /* NVidia reports that certain chips don't handle + * QH, ITD, or SITD addresses above 2GB. (But TD, + * data buffer, and periodic schedule are normal.) + */ + switch (pdev->device) { + case 0x003c: /* MCP04 */ + case 0x005b: /* CK804 */ + case 0x00d8: /* CK8 */ + case 0x00e8: /* CK8S */ + if (pci_set_consistent_dma_mask(pdev, + DMA_31BIT_MASK) < 0) + ehci_warn (ehci, "can't enable NVidia " + "workaround for >2GB RAM\n"); + break; + } + break; } /* optional debug port, normally in the first BAR */ |
