diff options
| author | John Youn <johnyoun@synopsys.com> | 2016-11-10 17:23:25 -0800 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2016-11-18 13:54:17 +0200 |
| commit | 5fb6fdaf38f71ad15ae85b1c4b4d94e8865e7284 (patch) | |
| tree | e14397a951e8b9efabb23ed0fd48599da5d87735 /drivers/usb/dwc3 | |
| parent | 3c22037050aceddab0564b5f8e7bdec568c50efd (diff) | |
| download | talos-obmc-linux-5fb6fdaf38f71ad15ae85b1c4b4d94e8865e7284.tar.gz talos-obmc-linux-5fb6fdaf38f71ad15ae85b1c4b4d94e8865e7284.zip | |
usb: dwc3: gadget: Fix dead code writing GCTL.RAMCLKSEL
The register programming code in dwc2_updated_ram_clk_sel() will never
be executed. And in fact the entire function can be removed as there is
no way to override the default value of GCTL.RAMCLKSEL. Remove the
function and add a comment explaining where GCTL.RAMCLKSEL should be
programmed if needed in the future.
This fixes dead code warnings in coverity.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/dwc3')
| -rw-r--r-- | drivers/usb/dwc3/gadget.c | 35 |
1 files changed, 8 insertions, 27 deletions
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 22ccc346af2f..230ffa395dc3 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2468,32 +2468,6 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_DCFG, reg); } -static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) -{ - u32 reg; - u32 usb30_clock = DWC3_GCTL_CLK_BUS; - - /* - * We change the clock only at SS but I dunno why I would want to do - * this. Maybe it becomes part of the power saving plan. - */ - - if ((speed != DWC3_DSTS_SUPERSPEED) && - (speed != DWC3_DSTS_SUPERSPEED_PLUS)) - return; - - /* - * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed - * each time on Connect Done. - */ - if (!usb30_clock) - return; - - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); - dwc3_writel(dwc->regs, DWC3_GCTL, reg); -} - static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) { struct dwc3_ep *dep; @@ -2505,7 +2479,14 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) speed = reg & DWC3_DSTS_CONNECTSPD; dwc->speed = speed; - dwc3_update_ram_clk_sel(dwc, speed); + /* + * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed + * each time on Connect Done. + * + * Currently we always use the reset value. If any platform + * wants to set this to a different value, we need to add a + * setting and update GCTL.RAMCLKSEL here. + */ switch (speed) { case DWC3_DSTS_SUPERSPEED_PLUS: |
